CN113242167B

CN113242167B - Semi-asynchronous CAN bus control method and controller based on single bit synchronization

Info

Publication number: CN113242167B
Application number: CN202110389847.3A
Authority: CN
Inventors: 孙旭; 吴鹏; 于文卓; 陈琴
Original assignee: Chengdu Nisheng Technology Co ltd
Current assignee: Chengdu Nisheng Technology Co ltd
Priority date: 2021-04-12
Filing date: 2021-04-12
Publication date: 2023-04-25
Anticipated expiration: 2041-04-12
Also published as: CN113242167A

Abstract

The invention discloses a semi-asynchronous CAN bus control method and a controller based on single bit synchronization. The semi-asynchronous CAN bus control method based on single bit synchronization comprises the following steps: generating a communication clock in a frequency division mode; the communication clock collects the start bit of the signal to be synchronized, the start bit is a single-bit dominant signal, and the frequency divider is triggered to reset when the synchronizing signal is collected, so that the initial phase of the communication clock is synchronized with the synchronizing signal. The asynchronous communication does not require a clock but requires frequency so as to realize unequal interval communication, so that the communication efficiency is improved, the semi-synchronous communication flexibly changes the phase of the clock on the basis of synchronous communication so as to realize the unequal interval communication function similar to the asynchronous communication.

Description

Semi-asynchronous CAN bus control method and controller based on single bit synchronization

Technical Field

The invention relates to the field of network communication, in particular to a semi-asynchronous CAN bus control method and a controller based on single bit synchronization.

Background

The controller area network (Controller Area Network, CAN or CAN bus for short) is a vehicle bus standard with rich functions. Which is designed to allow a single chip microcomputer and instruments on a network to communicate with each other without the need for a Host (Host). Based on the message transmission protocol, the multiplexing communication cable is adopted on the vehicle at the beginning of design so as to reduce the use amount of copper wires, and is also used by other industries later.

CAN is created on a broadcast mechanism (Broadcast Communication Mechanism) based on information-oriented transport agreements. It uses information identifiers (Message Identifier), each unique across the network, to define the priority of content and messages for delivery, rather than assigning a specific Station Address, based on the content of the information. Therefore, the CAN has good elastic adjustment capability, and nodes CAN be added in the existing network without adjustment on software and hardware. In addition, the message transmission is not based on the special type of nodes, so that the convenience of upgrading the network is improved.

The CAN bus has strict standard protocol and physical specification, is a high-stability bus protocol, and has the functions of autonomous verification, error correction, error reporting and node priority sequencing in the communication process required by the protocol, and the versions of the protocols which are commonly used at present are CAN2.0A and CAN2.0B.

The CAN bus protocol is a high-stability asynchronous communication means, because the CAN bus protocol belongs to an asynchronous communication protocol, errors caused by skew of sampling points in the communication process are unavoidable, namely, the sampling points are positioned near 90% or near 10%, in the traditional CAN bus protocol, once the sampling points are skewed, the CRC check is in error, the nodes for transmitting data resend the group of data, so that the normal operation of the system is ensured, and communication delay caused by the transmission of error codes is unavoidable.

Disclosure of Invention

In view of the above problems, the present invention aims to provide a semi-asynchronous CAN bus control method and a controller based on single bit synchronization. The semi-asynchronous CAN bus control method based on single bit synchronization comprises the following steps:

generating a communication clock in a frequency division mode;

the communication clock collects the start bit of a signal to be synchronized, the start bit is a single-bit dominant signal, and the frequency divider is triggered to reset when the synchronizing signal is collected, so that the initial phase of the communication clock is synchronized with the synchronizing signal.

In an embodiment, the semi-asynchronous CAN bus control method based on single bit synchronization adopts programmable multi-level buffering, and multi-level division is performed in the same size buffer area.

The invention also discloses a semi-asynchronous CAN bus controller based on single bit synchronization, which is characterized by comprising the following components:

the clock module is used for generating a communication clock in a frequency division mode; the communication clock collects the start bit of a signal to be synchronized, the start bit is a single-bit dominant signal, and the frequency divider is triggered to reset when the synchronizing signal is collected, so that the initial phase of the communication clock is synchronized with the synchronizing signal.

In an embodiment, the method further comprises a data buffer zone, wherein the data buffer zone adopts programmable multilevel buffering based on a single-bit synchronous semi-asynchronous CAN bus control method, and multilevel division is carried out in the buffer zone with the same size.

The semi-asynchronous CAN bus controller based on single bit synchronization is realized by designing on an FPGA.

Compared with the prior art, the application has the advantages that:

the semi-asynchronous communication mode is a novel special communication mode, namely, the recovered approximate clock is used as a synchronous clock in the asynchronous communication process, which is different from the existing synchronous communication, asynchronous communication and semi-synchronous communication, the synchronous communication requires a host to provide a clock for a slave to recover data, the asynchronous communication does not require the clock and requires the frequency to realize unequal interval communication, so that the communication efficiency is improved, the semi-synchronous communication flexibly changes the phase of the clock on the basis of the synchronous communication to realize the unequal interval communication function similar to the asynchronous communication, and the semi-asynchronous communication in the invention recovers the synchronous clock from the data based on the asynchronous communication to realize pseudo signal synchronization, namely, the inaccurate synchronous clock solves the error code problem in the asynchronous communication process.

The adoption of the single bit synchronous method for semi-asynchronous communication greatly reduces the error code condition generated by the characteristics of the asynchronous communication in the communication process, and the communication in the mode can improve the communication efficiency and reduce the problems of brake failure, key out of control, logic error and the like of the electric automobile caused by communication in practical application.

The sequence detection clock module is used as a core clock, and the total clock is switched under a specific sequence, so that the controller only works under the condition of needing to be used, the use loss of devices is reduced, and the power consumption of the controller is greatly reduced.

The FIFO of a single buffer area or a bipolar buffer area is subjected to multi-stage array, and complex logic in the communication process is realized through multi-priority configuration.

Specific embodiments of the invention are disclosed in detail below with reference to the following description and drawings, indicating the manner in which the principles of the invention may be employed. It should be understood that the embodiments of the invention are not limited in scope thereby. The embodiments of the invention include many variations, modifications and equivalents within the spirit and scope of the appended claims.

Features that are described and/or illustrated with respect to one embodiment may be used in the same way or in a similar way in one or more other embodiments in combination with or instead of the features of the other embodiments.

It should be emphasized that the term "comprises/comprising" when used herein is taken to specify the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps or components.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the invention, and that other drawings can be obtained from these drawings without inventive faculty for a person skilled in the art.

FIG. 1 is a flow chart of a half-asynchronous CAN bus control method based on single bit synchronization of the invention;

FIG. 2 is a schematic diagram of the structure of a CAN bus controller IP core;

FIG. 3 is a timing diagram of a controller receiving data according to an embodiment of the present invention;

FIG. 4 is a timing diagram of data transmission by a controller according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a controller provided by an embodiment of the present invention;

fig. 6 is a module package test chart according to an embodiment of the present invention.

Detailed Description

The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and the specific embodiments, it should be understood that these embodiments are only for illustrating the present invention and not for limiting the scope of the present invention, and various modifications of equivalent forms of the present invention will fall within the scope of the appended claims of the present application after reading the present invention.

Referring to fig. 1, the semi-asynchronous CAN bus control method based on single bit synchronization of the present invention specifically includes the steps of:

s101: generating a communication clock in a frequency division mode;

s102: the communication clock collects the start bit of a signal to be synchronized, the start bit is a single-bit dominant signal, and the frequency divider is triggered to reset when the synchronizing signal is collected, so that the initial phase of the communication clock is synchronized with the synchronizing signal.

The semi-asynchronous communication mode is a novel communication mode provided by the invention, namely, the approximate clock is recovered to be used as a synchronous clock in the asynchronous communication process. Asynchronous communication and semi-synchronous communication are different from the existing synchronous communication, synchronous communication requires a master to provide a clock for a slave to recover data, and asynchronous communication requires no clock but requires frequency to realize unequal interval communication, thereby improving communication efficiency.

Semi-synchronous communication flexibly changes the phase of a clock based on synchronous communication to realize an unequal interval communication function similar to asynchronous communication. The semi-asynchronous communication in the invention is based on asynchronous communication, and the synchronous clock is recovered from the data so as to realize pseudo signal synchronization, namely inaccurate synchronous clock, and the scheme is realized by a single bit synchronization method.

The single bit synchronization is carried out by adopting a bit synchronization principle in the coding communication process, and the generation of a communication clock is realized by a bit synchronization clock through a frequency division mode. In the synchronization process, a clock module collects a start bit of a signal to be synchronized, and the start bit is a single-bit dominant signal in a CAN bus. The frequency divider is triggered to reset immediately when the signal is acquired, so that the initial phase of the clock is synchronized with the signal to be synchronized. Because CAN bus communication itself belongs to asynchronous communication, the communication clock frequency is known, so that the phase synchronization in one frame communication CAN be ensured only by carrying out phase synchronization on the start bit of each frame. The scheme can ensure that the sampling point can stably fall at 50% of sampling positions in the first frame sampling process, and the sampling point offset is not more than 10% under the condition of certain clock frequency division phase noise of the end frame, so that the sampling point stability can be realized in one frame.

In the clock module, except the single bit synchronous module, the single enabling mode is modified into the enabling mode of sequence detection, the sequence detection is carried out on the received data, the clock generation is carried out in a semi-asynchronous mode, the accuracy of the sequence detection is guaranteed, and the initial frame, the end frame and the error frame are distinguished through the sequence detection. According to the CAN2.0 standard protocol, when a start frame is received in a bus idle state, the start frame needs to enter a working state, when a stop frame is received in the working state, the transmission is stopped, an error frame indicates that data needs to be retransmitted in error, a clock is turned on when the start frame and the error frame are started, and the clock is turned off when the stop frame is stopped, so that the power consumption design CAN be optimized.

In the data buffer area, the common CAN bus controller only has 1-level buffer area, the data transmission queue is completed through the buffer area, the CAN bus control IP core of the Xilinx company adopts two-level buffer, high and low priority is used for distinguishing, under the condition that the low priority queue is full, the emergency signal transmission is limited by using a high priority channel for the safety control under the situations of emergency braking, emergency shutdown, braking and the like, but the invention adopts programmable multilevel buffer, carries out multilevel division in the buffer area with the same size, and adopts a deep storage depth instead of the high priority channel, so that the buffer area array is formed by adopting a depth-to-breadth method, the scheme CAN save logic resources more under the condition that the design needs to be single, CAN allocate multiple priority designs, and provides a more flexible research and development strategy for research personnel.

The multi-stage buffer zone designed by the method has the advantages that: more flexible communication interrupt priority configuration is provided for developers to realize safer logic.

The advantages of the above scheme are also:

The invention also discloses a semi-asynchronous CAN bus controller based on single bit synchronization, which comprises:

the clock module is used for generating a communication clock in a frequency division mode; the communication clock collects the start bit of a signal to be synchronized, the start bit is a single-bit dominant signal, and the frequency divider is triggered to reset when the synchronizing signal is collected, so that the initial phase of the communication clock is synchronized with the synchronizing signal. For example, referring to fig. 3 and 4, a timing diagram of the controller receiving and transmitting data is shown. Fig. 4 is a schematic diagram of a controller, in which can_phy is a physical layer module, tx_rom is a multi-level priority configuration transmit buffer channel, and receive_fifo is a receive buffer channel.

The technical scheme of the invention finally forms an IP core form (see fig. 2), the IP core CAN be installed on any FPGA in the market, the IP core is completely compatible with CAN2.0 standard protocol, and the interior of the IP core is composed of three large modules, namely a physical layer module, a multi-level priority sending buffer module and a receiving buffer module.

The receiving and transmitting physical layer module is divided into a transmitting channel and a receiving channel, the two channels share a core clock, the core clock consists of a sleep control and a single bit synchronous clock and is respectively used for signal synchronization and sleep control, and the receiving and transmitting channels are used for filling received data into a buffer area and transmitting data in the buffer area.

The multi-level priority buffer module consists of a common channel with the lowest priority and a high priority channel with multi-priority configuration, wherein the common channel is used for buffering normal transmission data, and the high priority channel is used for emergently processing interrupt events. The receive buffer module has no priority determination capability and therefore uses a common single stage FIFO buffer module.

Fig. 6 is a module packaging test chart, in which serial numbers 0 to 17 are data sent by an upper computer, and the module packaging test chart comprises multiple types of frames of two protocols, namely can2.0a and can2.0b, and serial numbers 18 to 35 are the same data frames forwarded after the controller receives the data, so that the data are not bad in the communication process.

It is to be understood that the above description is intended to be illustrative, and not restrictive. Many embodiments and many applications other than the examples provided will be apparent to those of skill in the art upon reading the above description. The scope of the present teachings should, therefore, be determined not with reference to the above description, but instead should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. The disclosures of all articles and references, including patent applications and publications, are incorporated herein by reference for the purpose of completeness. The omission of any aspect of the subject matter disclosed herein in the claims that follows is not intended to forego the subject matter, nor should the inventors regard that the subject matter as part of the disclosed subject matter.

Claims

1. A semi-asynchronous CAN bus control method based on single bit synchronization is characterized by comprising the following steps:

the bit synchronous clock generates a communication clock in a frequency division mode;

the communication clock acquires a start bit of a signal to be synchronized, the start bit is a single-bit dominant signal, and the frequency divider is triggered to reset immediately when the start bit of the signal to be synchronized is acquired, so that the initial phase of the communication clock is synchronized with the synchronization signal, namely, an approximate clock is recovered in an asynchronous communication process to be used as the synchronization clock;

the method comprises the steps of carrying out phase synchronization on a start bit of each frame, so that the phases are synchronized in one frame of communication, and a sampling point can stably fall at 50% of sampling in the sampling process of a first frame;

performing sequence detection on the received data by adopting an enabling mode of sequence detection;

clock generation is carried out in a semi-asynchronous mode, and a start frame, a stop frame and an error frame are distinguished through sequence detection;

according to CAN2.0 standard protocol, the bus enters into working state when receiving initial frame in idle state, and when receiving termination frame in working state, the bus indicates that the transmission is terminated, and the error frame indicates that the data is needed to be retransmitted in error; opening the clock at the start frame and the error frame, and closing the clock at the end frame;

the semi-asynchronous CAN bus control method based on single bit synchronization adopts programmable multi-stage buffering, and performs multi-stage division in the buffer areas with the same size;

the buffer area array is formed into multi-stage FIFO by adopting a depth-to-breadth method, namely the FIFO of a single buffer area or a bipolar buffer area is subjected to multi-stage array, and complex logic in the communication process is realized through multi-priority configuration.

2. A half-asynchronous CAN bus controller based on single bit synchronization, comprising:

the clock module is used for generating a communication clock by the bit synchronous clock in a frequency division mode; the communication clock acquires a start bit of a signal to be synchronized, the start bit is a single-bit dominant signal, and the frequency divider is triggered to reset immediately when the start bit of the signal to be synchronized is acquired, so that the initial phase of the communication clock is synchronized with the synchronization signal;

the data buffer area adopts programmable multilevel buffering based on a single-bit synchronous semi-asynchronous CAN bus control method, and is divided into multiple levels in the buffer areas with the same size;

the clock module and the data buffer area form an IP core, and the IP core is internally composed of a physical layer module, a multi-level priority sending buffer module and a multi-level priority receiving buffer module;

the physical layer module is divided into a transmitting channel and a receiving channel, the two channels share a core clock, the core clock consists of a sleep control clock and a single-bit synchronous clock and is respectively used for signal synchronization and sleep control, and the two channels are used for filling received data into a buffer area and sending data in the buffer area;

the multi-priority sending buffer module consists of a common channel with the lowest priority and a high-priority channel with multi-priority configuration, wherein the common channel is used for buffering normal sending data, and the high-priority channel is used for emergently processing an interrupt event; the receive buffer module uses a common single stage FIFO buffer module.

3. The half-asynchronous CAN bus controller based on single bit synchronization according to claim 2, wherein the half-asynchronous CAN bus controller based on single bit synchronization is realized by designing on an FPGA.