CN115695553A

CN115695553A - Data transmission system and method for synchronous surface and management surface between FPGA chips

Info

Publication number: CN115695553A
Application number: CN202211336334.7A
Authority: CN
Inventors: 雷洪涛
Original assignee: Sichuan Hengwan Technology Co Ltd
Current assignee: Sichuan Hengwan Technology Co Ltd
Priority date: 2022-10-28
Filing date: 2022-10-28
Publication date: 2023-02-03

Abstract

The invention provides a data transmission system and method for an FPGA (field programmable gate array) inter-chip synchronization plane and a management plane, and relates to the technical field of 5G communication. In the data transmission process from the FPGA to the main FPGA, control plane and user plane data in a data packet are filtered out firstly, and the data packet containing synchronous plane and management plane data is obtained. And then caching the filtered data packet and corresponding frame head, frame length and frame tail information thereof. And sequentially reading the data packets through a framing state machine, and framing the data packets by combining with corresponding information to obtain a to-be-deframed data packet and sending the to-be-deframed data packet to the main FPGA. And the main FPGA sequentially performs deframing processing and caching on the data packets to be deframed through the deframing state machine, and finally transmits the data to the DDR unit of the main system. And the data transmission from the master FPGA to the slave FPGA is similar, so that the bidirectional high-speed transmission of the data of the synchronous surface and the management surface among the FPGA chips is realized, and the simultaneous operation of a single network port or double network ports is supported.

Description

Data transmission system and method for synchronous surface and management surface between FPGA chips

Technical Field

The invention relates to the technical field of 5G communication, in particular to a data transmission system and method for an FPGA (field programmable gate array) inter-chip synchronous surface and a management surface.

Background

The 5G NR is a global 5G standard designed based on a new air interface of OFDM (Orthogonal Frequency Division Multiplexing, mainly used for parallel transmission of high-speed serial data), and is also an important cellular mobile technology of the next generation. One key technology of 5G is the Massive antenna technology, namely Massive MIMO. The number of antennas of a conventional TDD network is usually 2 antennas, 4 antennas or 8 antennas, and the number of channels of Massive MIMO can reach 64 antennas. With the increase of the number of antennas, the system capacity is also multiplied, but correspondingly, the complexity of system implementation is also multiplied, so that multiple FPGAs (programmable devices) are usually required to complete the logic implementation of the Massive MIMO system.

In a multi-FPGA system, in order to meet the timing requirements between FPGAs, a centralized control manner is usually adopted, that is, one of the FPGAs is responsible for overall control and scheduling, so that the problem of high-speed transmission and bidirectional transmission of synchronous plane information and management plane information between the FPGA slices is faced.

Disclosure of Invention

The invention aims to provide a data transmission system and a data transmission method for a synchronous surface and a management surface among FPGA (field programmable gate array) chips, which realize high-speed transmission of the synchronous surface and the management surface data among the FPGA chips by filtering, extracting, framing, unframing and the like of the synchronous surface and the management surface information of the data and support the simultaneous operation of a single network port or double network ports.

The embodiment of the invention is realized by the following steps:

in a first aspect, an embodiment of the present application provides a data transmission system for an FPGA inter-chip synchronization plane and a management plane, including a slave FPGA and a master FPGA, wherein:

the slave FPGA comprises: the Ethernet module is used for deserializing the received serial data to obtain an initial data packet and sending the initial data packet to the message filtering module; the message filtering module is used for filtering control plane and user plane data in the data packet to obtain a data packet containing synchronous plane and management plane data; the FIFO cache module is used for caching the filtered data packet and the corresponding frame head, frame length and frame tail information thereof; the framing state machine is used for sequentially detecting and reading the data packets in the FIFO cache module, and framing the data packets by combining the frame head, the frame length and the frame tail information corresponding to the data packets to obtain data packets to be deframed and sending the data packets to the main FPGA;

the main FPGA comprises: the FIFO buffer module is used for buffering the data packet of the frame to be decoded; the de-framing state machine is used for sequentially de-framing the data packets to be de-framed and storing the data packets into the corresponding FIFO cache modules according to the frame headers; and the switch is used for forwarding the data packet after being deframed to the destination port.

Based on the first aspect, in some embodiments of the present invention, the main FPGA further includes a high-speed interconnection module, configured to split data according to a TDEST flag in a data packet, and store parallel data streams into corresponding FIFO buffer modules respectively.

In a second aspect, an embodiment of the present application provides a method for transmitting data of an FPGA inter-chip synchronization plane and a management plane, including:

in the slave FPGA, control plane and user plane data in a data packet are filtered through a message filtering module to obtain a data packet containing synchronous plane and management plane data;

caching the filtered data packet and corresponding frame head, frame length and frame tail information thereof through an FIFO (first in first out) caching module;

sequentially detecting and reading the data packets in the FIFO cache module through a framing state machine, and framing the data packets by combining frame head, frame length and frame tail information corresponding to the data packets to obtain data packets to be unframed and sending the data packets to a main FPGA;

in the main FPGA, caching data packets to be deframed through an FIFO (first in first out) caching module, deframing the data packets to be deframed in sequence through a deframing state machine, and storing the data packets into corresponding FIFO caching modules according to frame headers;

and transmitting the data packet after being deframed to a DDR unit of a main system for storage.

Based on the second aspect, in some embodiments of the present invention, the step of caching the filtered data packet and its corresponding frame header, frame length, and frame tail information by using the FIFO buffer module includes:

storing the data packet into a corresponding AXIS _ FIFO _0 module/AXIS _ FIFO _1 module;

and extracting frame head, frame length and frame tail information corresponding to the data packet, and correspondingly storing the frame head, frame length and frame tail information into a NATIVE _ FIFO _0 module/NATIVE _ FIFO _1 module.

Based on the second aspect, in some embodiments of the present invention, the step of sequentially detecting and reading the data packets in the FIFO buffer module by the framing state machine, and performing framing processing by combining the frame header, the frame length, and the frame end information corresponding to the data packets to obtain the data packets to be deframed includes:

and the framing state machine reads out the data packet after detecting the data packet in the FIFO cache module, sequentially adds a frame head, a frame length and a frame tail corresponding to the data packet to the front of the data frame of the data packet, and inserts a reserved field between the frame tail and the data frame of the data packet to obtain the data packet to be deframed.

Based on the second aspect, in some embodiments of the invention, the manner of detecting whether there is a packet in the FIFO buffer module by the framing state machine is as follows:

the framing state machine judges whether a data packet exists in the FIFO cache module according to the Tvalid state output by the FIFO cache module; and if the Tvalid state is not 0, reading the data and performing framing processing.

Based on the second aspect, in some embodiments of the present invention, the sequentially deframing the data packets to be deframed by the deframing state machine, and the step of storing the data packets into the corresponding FIFO buffer module according to the frame header includes:

the deframing state machine determines the corresponding data packet to be deframed according to the detected frame header information;

checking whether reserved fields in a data packet to be deframed are matched, and if the reserved fields in the data packet to be deframed are matched, receiving the data packet according to the frame length information of the data packet; if not, quitting the state machine and reporting error;

after receiving the data packet, different data packets are respectively stored in the AXIS _ FIFO _0 module and the AXIS _ FIFO _1 module according to the frame header information.

In a third aspect, an embodiment of the present application provides an electronic device, which includes a memory for storing one or more programs; a processor. The one or more programs, when executed by the processor, implement the method as described above in any of the second aspects.

In a fourth aspect, embodiments of the present application provide a computer-readable storage medium, on which a computer program is stored, which, when executed by a processor, implements the method as described above in any one of the second aspects.

Compared with the prior art, the embodiment of the invention has at least the following advantages or beneficial effects:

the embodiment of the application provides a data transmission system and a data transmission method for an FPGA (field programmable gate array) inter-chip synchronization plane and a management plane. In a downlink transmission link of data, firstly, a received data packet is deserialized through an Ethernet module of an FPGA to obtain two parallel data packets, and control plane and user plane data in the data packet are filtered through a message filtering module according to frame header information of the data packet to obtain the data packet containing synchronous plane and management plane data. Then, the frame head, frame length and frame tail information corresponding to the data packet are extracted and stored into the FIFO cache module corresponding to the source data. And then, framing the data packet by combining the frame head, the frame length and the frame tail information corresponding to the data packet through a framing state machine to obtain a data packet to be unframed and sending the data packet to the main FPGA. After receiving the data packet to be deframed, the main FPGA branches the data packet through the high-speed interconnection module and stores the data packet into the corresponding FIFO cache module, and then deframes the data packet through the deframed state machine according to the frame head, the frame length and the frame tail information corresponding to the data packet, restores the data packet to be deframed into source data and stores the source data into the corresponding FIFO cache module. And finally, transmitting the data to a DDR unit of the main system for storage through a switch, an AXI bus and other equipment. In the uplink transmission link of the data, the master FPGA filters, extracts and frames the message, and the slave FPGA performs the de-framing processing, thereby completing the bidirectional transmission of the data. Overall, the present application implements bidirectional high-speed transmission and bidirectional transmission of data of the synchronization plane and the management plane between the FPGA chips by filtering, extracting, framing, deframing, etc. the synchronous plane and the management plane of the data, and supports simultaneous operation of a single network port or a dual network port.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.

Fig. 1 is a schematic flow diagram of data uplink transmission in an embodiment of a data transmission system for an inter-chip synchronization plane and a management plane of an FPGA according to the present invention;

fig. 2 is a schematic structural diagram of a data frame in an embodiment of a data transmission system for an FPGA inter-chip synchronization plane and a management plane according to the present invention;

fig. 3 is a schematic flow diagram of data downlink transmission in an embodiment of a data transmission system for an inter-chip synchronization plane and a management plane of an FPGA according to the present invention;

fig. 4 is a schematic flowchart of an embodiment of a method for transmitting data of a synchronization plane and a management plane between FPGA chips according to the present invention;

fig. 5 is a block diagram of an electronic device according to an embodiment of the present invention.

Icon: 1. a memory; 2. a processor; 3. a communication interface.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.

Examples

Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments and features of the embodiments described below can be combined with one another without conflict.

Referring to fig. 1, in a first aspect, an embodiment of the present application provides a data transmission system for an FPGA inter-chip synchronization plane and a management plane, where the system includes a slave FPGA and a master FPGA, where:

the main FPGA comprises: the FIFO buffer module is used for buffering the data packet to be decoded; the de-framing state machine is used for sequentially de-framing the data packets to be de-framed and storing the data packets into the corresponding FIFO cache modules according to the frame headers; and the switch is used for forwarding the data packet after being deframed to the destination port.

Further, in some embodiments of the present invention, the main FPGA further includes a high-speed interconnection module, configured to split data according to a TDEST flag in a data packet, and obtain parallel data streams, which are stored in corresponding FIFO buffer modules respectively.

In the technical solution provided by this embodiment, for example, a hardware design framework of the system may be implemented based on 2 Xilinx Ultrascale FPGA chips. The main FPGA used as the overall control can be an FPGA chip of a multi-core heterogeneous SOC (ZYNQ), and the auxiliary FPGA can be an FPGA chip with rich high-speed interface resources.

Specifically, referring to fig. 1, in the downlink of data transmission, the message transmission process of the synchronization plane (S-plane) and the control plane (M-plane) is as follows:

and receiving high-speed serial data from one optical port/two optical ports from the FPGA through an Ethernet module (ETH), decoding the high-speed serial data, and restoring the data into a transmitted signal. For example, when receiving high-speed serial data from two optical ports (received through ETH0 and ETH1, respectively), the data is deserialized first, and the data is restored to correct parallel data, so as to obtain two source packets, and the packets are input to the message filtering module. The message filtering module filters control plane (C-plane) data and user plane (U-plane) data in the data packet according to frame header information corresponding to the data packet to obtain a data packet containing synchronous plane (S-plane) data and management plane (M-plane) data, and then the data packet is input into the FIFO caching module for caching. Wherein, the AXIS _ FIFO _0 submodule is used to store the data packet from ETH 0; the AXIS _ FIFO _1 submodule is used to store the data packets from ETH 1. Meanwhile, the information of the frame head, the frame length and the frame tail (tkeep) of the two data packets is extracted and cached respectively. The NATIVE _ FIFO _0 sub-module is used for storing frame header, frame length and frame tail information corresponding to the data packet from ETH 0; the NATIVE _ FIFO _1 submodule is used for storing the information of the frame head, the frame length and the frame tail corresponding to the data packet from the ETH 1. Then, after the framing state machine detects that there is data in the FIFO buffer module, the framing state machine adds the respective corresponding frame header to the data from different ethernet modules (ETH 0 or ETH 1), and adds information (as shown in fig. 2) such as the frame length and the tkeep of the frame end (the last valid data), to complete the framing process, and obtain the data packet to be deframed. It should be noted that, if data are stored in both the AXIS _ FIFO _0 sub-module and the AXIS _ FIFO _1 sub-module, the data in the AXIS _ FIFO _1 is preferentially framed and transmitted. And transmitting the data packet to be deframed to a high-speed interconnection module after obtaining the data packet to be deframed, and then transmitting the data packet to the high-speed interconnection module of the main FPGA through a high-speed serial link GTY.

After receiving the data packet to be deframed, the high-speed interconnection module in the main FPGA shunts data according to the TDEST mark in the data packet, and the obtained parallel data stream is stored in the FIFO cache module. Then, the deframing state machine can directly distinguish the data packet according to the information such as the frame header and the frame length, judge the source (ETH 0 or ETH 1) of the data packet and the size of the data, extract the message data of the synchronization surface (S surface) and the management surface (M surface) corresponding to the data packet, respectively cache the extracted data in the AXIS _ FIFO _0 sub-module and the AXIS _ FIFO _1 sub-module according to the source (ETH 0 or ETH 1) of the data, complete the deframing process, and recover the data. Finally, the data is transmitted to a DDR unit of a main System (Processing System) through a switch, MCDMA (multi-channel direct memory access), AXI bus, and the like, and stored. Therefore, the downlink high-speed transmission process of the data of the inter-chip synchronous surface and the management surface from the FPGA to the main FPGA is realized.

The uplink high-speed transmission process of the inter-chip synchronization plane and management plane data from the master FPGA to the slave FPGA is shown in fig. 3, and the data transmission process and the logical principle of framing and deframing are basically the same as those of downlink transmission of data, and are not described again here.

In some embodiments of the present invention, the process of framing by the framing state machine specifically includes: and the framing state machine reads the data packet after detecting that the data packet exists in the FIFO cache module, sequentially adds a frame head, a frame length and a frame tail corresponding to the data packet to the front of the data frame of the data packet, and inserts a reserved field between the frame tail and the data frame of the data packet to obtain the data packet to be deframed.

Referring to fig. 2, the obtained data packet to be deframed is composed of a frame data of 8-bit frame header, 2-bit frame length, 1-bit frame tail tkopp, 5-bit reserved field, and synchronization plane (S-plane)/management plane (M-plane). The frame header mainly plays a distinguishing role, and during transmission, the master FPGA/the slave FPGA can distinguish and identify different data packets according to the frame header, so that the processing efficiency is improved. The frame length is mainly used for checking whether the data are completely received or not, so that the integrity of data transmission is ensured, and the probability of frame drop is reduced. The tail tkeep is used to determine the valid bytes of the last beat of data. The reserved field is mainly used for the state checking of the frame decoding state machine during frame decoding, and quitting is performed after the reserved field is not checked.

Specifically, the logic process of the framing state machine is as follows: firstly, the framing state machine judges whether a data packet exists in the FIFO buffer module according to the Tvalid state output by the FIFO buffer module (AXIS _ FIFO _0 sub-module/AXIS _ FIFO _1 sub-module). If the framing state machine detects that Tvalid [1 ] is 0, then framing is not performed; if the state is not 0, the framing procedure is started.

Further, if Tvalid [1 ] =2'b01, it indicates that at least one frame of data from ETH0 has been stored in AXIS _ FIFO _0, the frame header is set to 64' h5555_5555 _555555555555e0; if Tvalid [1 ] =2'b10, it means that at least one frame of data from ETH1 has been stored in AXIS _ FIFO _1, then the frame header is set to 64' h5555_5555 _5555E1. When Tvalid [1 ] =2' b11, it means that at least one frame of data from ETH0 and ETH1 is stored in both AXIS _ FIFO _0 and AXIS _ FIFO _1, and the framing state machine preferentially frames and transmits the data in AXIS _ FIFO _ 1. After the frame header is determined, the framing state machine reads information such as the frame length and the frame tail tkeep from the NATIVE _ FIFO _0 and the NATIVE _ FIFO _1 and integrates the information into a new data frame, and then adds a reserved field between the frame tail tkeep and the data frame, wherein the reserved field can be set to be a fixed value of 40' h55_5555_55ed. Therefore, the data of the synchronous surface (S surface) and the data of the management surface (M surface) are transmitted after the reserved field is transmitted.

In some embodiments of the present invention, the logic process of the above-mentioned deframing state machine is as follows: when the unframe state machine detects a frame header (64 ″ 'h5555_5555_5555_55E0 or 64 ″' h5555_5555 _555555E1), streaming into the state machine begins. The reserved field is checked first, and if the reserved field does not match, the deframing state machine is exited and an error is reported. If the reserved fields are matched, starting to receive data according to the frame length information, and respectively storing the data into the AXIS _ FIFO _0 module and the AXIS _ FIFO _1 module according to different frame headers (ETH 0 or ETH 1).

Referring to fig. 4, in a second aspect, an embodiment of the present application provides a method for transmitting data of an FPGA inter-chip synchronization plane and a management plane, including:

step S1: in the slave FPGA, control plane and user plane data in a data packet are filtered by a message filtering module to obtain a data packet containing synchronous plane and management plane data;

step S2: caching the filtered data packet and corresponding frame head, frame length and frame tail information thereof through an FIFO (first in first out) caching module;

and step S3: sequentially detecting and reading the data packets in the FIFO cache module through a framing state machine, and framing the data packets by combining frame head, frame length and frame tail information corresponding to the data packets to obtain data packets to be unframed and sending the data packets to a main FPGA;

and step S4: in the main FPGA, caching data packets to be deframed through an FIFO (first in first out) caching module, deframing the data packets to be deframed in sequence through a deframing state machine, and storing the data packets into corresponding FIFO caching modules according to frame headers;

step S5: and transmitting the data packet after being deframed to a DDR unit of a main system for storage.

In the embodiment, the method realizes high-speed transmission and bidirectional transmission of the synchronous surface and management surface data among the FPGA chips by filtering, extracting, framing, unframing and the like of the synchronous surface and management surface information of the data, and supports simultaneous operation of a single network port or double network ports. The specific data transmission process and framing and deframing process are already described in detail in the above system flow, and are not described herein again.

Referring to fig. 5, fig. 5 is a block diagram of an electronic device according to an embodiment of the present disclosure. The electronic device comprises a memory 1, a processor 2 and a communication interface 3, wherein the memory 1, the processor 2 and the communication interface 3 are electrically connected with each other directly or indirectly to realize the transmission or interaction of data. For example, the components may be electrically connected to each other via one or more communication buses or signal lines. The memory 1 may be configured to store software programs and modules, such as program instructions/modules corresponding to a data transmission system of an FPGA inter-chip synchronization plane and a management plane provided in an embodiment of the present application, and the processor 2 executes various functional applications and data processing by executing the software programs and modules stored in the memory 1. The communication interface 3 may be used for communication of signaling or data with other node devices.

The Memory 1 may be, but is not limited to, a Random Access Memory (RAM), a Read Only Memory (ROM), a Programmable Read-Only Memory (PROM), an Erasable Read-Only Memory (EPROM), an electrically Erasable Read-Only Memory (EEPROM), and the like.

The processor 2 may be an integrated circuit chip having signal processing capabilities. The Processor 2 may be a general-purpose Processor including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also Digital Signal Processors (DSPs), application Specific Integrated Circuits (ASICs), field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components.

It will be appreciated that the configuration shown in fig. 5 is merely illustrative and that the electronic device may include more or fewer components than shown in fig. 5 or have a different configuration than shown in fig. 1. The components shown in fig. 5 may be implemented in hardware, software, or a combination thereof.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The apparatus embodiments described above are merely illustrative and, for example, the flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition, functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

The functions may be stored in a computer-readable storage medium if they are implemented in the form of software functional modules and sold or used as separate products. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Claims

1. The utility model provides a data transmission system of synchronous face and management face between FPGA piece, includes from FPGA and main FPGA, its characterized in that:

the slave FPGA includes: the Ethernet module is used for deserializing the received serial data to obtain an initial data packet and sending the initial data packet to the message filtering module; the message filtering module is used for filtering control plane and user plane data in the data packet to obtain a data packet containing synchronous plane and management plane data; the FIFO cache module is used for caching the filtered data packet and the corresponding frame head, frame length and frame tail information thereof; the framing state machine is used for sequentially detecting and reading the data packets in the FIFO cache module, combining frame head, frame length and frame tail information corresponding to the data packets to carry out framing processing, obtaining data packets to be deframed and sending the data packets to the main FPGA;

2. The system according to claim 1, wherein the main FPGA further comprises a high-speed interconnect module for distributing data according to the TDEST tag in the data packet, and storing the obtained parallel data streams into the corresponding FIFO buffer modules respectively.

3. The method for transmitting data of the synchronous surface and the management surface between the FPGA chips in the data transmission system of the synchronous surface and the management surface between the FPGA chips as claimed in claim 1 or 2, comprising:

in the slave FPGA, control plane and user plane data in a data packet are filtered by a message filtering module to obtain a data packet containing synchronous plane and management plane data;

in the main FPGA, caching a data packet to be deframed through an FIFO (first in first out) caching module, deframing the data packet to be deframed in sequence through a deframing state machine, and storing the data packet into a corresponding FIFO caching module according to a frame header;

4. The method for transmitting the data of the synchronization plane and the management plane between the FPGA chips according to claim 3, wherein the step of caching the filtered data packet and the corresponding frame header, frame length and frame tail information thereof by the FIFO cache module comprises the steps of:

5. The method for transmitting the data of the synchronization plane and the management plane between the FPGA chips according to claim 3, wherein the step of sequentially detecting and reading the data packets in the FIFO cache module through the framing state machine and framing the data packets by combining the frame head, the frame length and the frame tail information corresponding to the data packets to obtain the data packets to be unframed comprises the following steps:

and the framing state machine reads the data packet after detecting that the data packet exists in the FIFO cache module, sequentially adds a frame head, a frame length and a frame tail corresponding to the data packet to the front of the data frame of the data packet, and inserts a reserved field between the frame tail and the data frame of the data packet to obtain the data packet to be deframed.

6. The method for transmitting data of the synchronous surface and the management surface between the FPGA chips as claimed in claim 5, wherein the way of the framing state machine detecting whether the FIFO buffer module has the data packet is as follows:

7. The method according to claim 3, wherein the step of sequentially deframing the data packets to be deframed by the deframing state machine and storing the data packets into the corresponding FIFO buffer modules according to the frame headers comprises:

the frame decoding state machine determines a corresponding data packet to be decoded according to the detected frame header information;

checking whether reserved fields in the data packet to be deframed are matched or not, and if the reserved fields are matched, receiving the data packet according to the frame length information of the data packet; if not, exiting the decoding state machine and reporting an error;

8. An electronic device, comprising:

a memory for storing one or more programs;

a processor;

the one or more programs, when executed by the processor, implement the method of any of claims 3-7.

9. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 3-7.