CN103345945A - Memory testing device with frequency testing function, as well as memory testing method - Google Patents
Memory testing device with frequency testing function, as well as memory testing method Download PDFInfo
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Abstract
The invention discloses a memory testing device with a frequency testing function. The memory testing device with the frequency testing function comprises a signal collecting module, an analog-to-digital conversion module, a storage module, a counting module as well as a frequency calculating module, wherein the signal collecting module collects to-be-tested signals continuously within a preset frequency so as to obtain sampling signals of a plurality of tested signals; the analog-to-digital conversion module converts the plurality of sampling signals into a plurality of digital signals; the storage module stores the plurality of digital signals in sequence; the counting module begins to count the stored digital signals from the initial digital signal, and the initial digital signal is the digital signal converted by the first obtained sampling signal; the frequency calculating module obtains the cycles and the frequencies of the tested signals according to the counting value of the digital signals in variation for the nth time, the digital values corresponding to the digital signals in variation for the (n+2)th time as well the preset frequency, wherein n is a positive integer greater than or equal to 1. According to the device, the memory chip conventional project testing and the frequency testing can be carried out and completed continuously once on the same device without additionally arranging additional testing circuits.
Description
Technical field
The present invention relates to the memory test technical field, relate in particular to a kind of memory test equipment and memory frequency method of testing with frequency test function.
Background technology
Along with the integrated level of integrated circuit is more and more higher, it is more and more compacter that the distance between device becomes, and storer is disturbed easily and form fault, therefore, is the quality that guarantees that integrated circuit is manufactured, and need carry out strict test and check to memory function.The existing memory test, be by special testing apparatus, as semiconductor automatization test system (ATE), after carrying out addressing at the memory under test chip, by the level signal on the input and output pin, the comparer of the testing apparatus that reads and writes data inside, contrast desired value and actual measurement logical value obtain the result's of PASS/FAIL test process.Because this characteristic makes this class testing equipment not have the frequency test function.If run into component frequency testing requirement in the memory test, must use extra logic testing system to carry out the second road test step of frequency test, can significantly increase testing cost and test technology complexity undoubtedly.
Summary of the invention
The objective of the invention is to overcome the defective of prior art, provide a kind of and can have the memory test equipment of frequency test function and under the condition that does not increase external test circuitry, based on the frequency test method of this memory test equipment.
The present invention is achieved by the following technical solutions:
A kind of memory test equipment with frequency test function, it comprises:
Signal acquisition module is carried out continuous collecting with preset frequency to measured signal, to obtain the sampled signal of a plurality of described measured signals;
Analog-to-digital conversion module is converted to a plurality of digital signals with described a plurality of sampled signals, and described digital signal is first digital signal or second digital signal;
Memory module is stored described a plurality of digital signal in order;
Counting module begins the digital signal of storing is counted from initial digital signal, and described initial digital signal is the digital signal that first sampled signal of obtaining is changed; And
The frequency computation part module, the corresponding count value of digital signal that changes when the corresponding count value of digital signal that changes during according to the n time digital signal change and the n+2 time digital signal change, and described preset frequency, obtain the cycle of described measured signal, and obtain the frequency of described measured signal according to cycle of described measured signal; Wherein said digital signal change is for to be converted to described second digital signal or to be converted to described first digital signal from described second digital signal from described first digital signal, and n is the positive integer more than or equal to 1.
Preferably, described frequency computation part module comprises comparison sub-module, and described comparison sub-module is more described digital signal digital signal previous with it successively, the digital signal that changes when obtaining described digital signal change.
Preferably, described frequency computation part module comprises comparison sub-module, described comparison sub-module is more described digital signal and reference signal successively, the digital signal that changes when obtaining the k time described digital signal change, and k is more than or equal to 1 and smaller or equal to the positive integer of n+2; Wherein when k be greater than 1 the time, the digital signal that described reference signal changes when being the k time digital signal change; When k was 1, described reference signal was described initial digital signal.
Preferably, it is normal period that the cycle that described frequency computation part module is obtained a plurality of described measured signals is got its mean value, and obtains the standard frequency of measured signal according to described normal period.
Preferably, when the output voltage of described sampled signal during more than or equal to threshold voltage, described analog-to-digital conversion module is converted to described first digital signal with described sampled signal; When described output voltage during less than described threshold voltage, described analog-to-digital conversion module is converted to described second digital signal with described sampled signal, described threshold voltage be described output voltage peaked half.
Preferably, set described preset frequency according to the estimated value of described measured signal frequency.
Preferably, described preset frequency is more than or equal to 10 times of the estimated value of described measured signal frequency.
Further, the present invention also provides a kind of memory frequency method of testing, may further comprise the steps:
With preset frequency continuous collecting is carried out in the measured signal of described storer, to obtain the sampled signal of a plurality of described measured signals;
Described a plurality of sampled signals are converted to a plurality of digital signals, and described digital signal is first digital signal or second digital signal;
Store described a plurality of digital signal in order;
Begin the digital signal of storing is counted from initial digital signal, described initial digital signal is the digital signal that first sampled signal of obtaining is changed;
The corresponding count value of digital signal that changes when the corresponding count value of digital signal that changes during according to the n time digital signal change and the n+2 time digital signal change, and described preset frequency, obtain the cycle of described measured signal, and obtain the frequency of described measured signal according to cycle of described measured signal; Wherein said digital signal change is for to be converted to described second digital signal or to be converted to described first digital signal from described second digital signal from described first digital signal, and n is the positive integer more than or equal to 1.
Preferably, by more described digital signal digital signal previous with it successively, the digital signal that changes when obtaining described digital signal change.
Preferably, by more described digital signal and reference signal successively, the digital signal that changes when obtaining the k time described digital signal change, k is more than or equal to 1 and smaller or equal to the positive integer of n+2; Wherein when k be greater than 1 the time, the digital signal that described reference signal changes when being the k time digital signal change; When k was 1, described reference signal was described initial digital signal.
Preferably, it is normal period that the cycle of obtaining a plurality of described measured signals is got its mean value, and obtains the standard frequency of measured signal according to described normal period.
Preferably, when the output voltage of described sampled signal during more than or equal to threshold voltage, described sampled signal is converted to described first digital signal; When described output voltage during less than described threshold voltage, described sampled signal is converted to described second digital signal, described threshold voltage be described output voltage peaked half.
Preferably, set described preset frequency according to the estimated value of described measured signal frequency.
Preferably, described preset frequency is more than or equal to 10 times of the estimated value of described measured signal frequency.
Beneficial effect of the present invention is, by memory test equipment measured signal is converted into the digital signal storage, read digital signal and counting, finally calculate cycle and the frequency of measured signal, expanded the frequency test function of memory test equipment, make testing memory chip conventional project and frequency test can be on same equipment once follow-on test finish, and need not to increase extra test circuit, effectively reduce the complexity of testing cost and test technology.
Description of drawings
Fig. 1 is the calcspar of one embodiment of the invention memory test equipment;
Fig. 2 is the process flow diagram of one embodiment of the invention memory frequency method of testing;
Fig. 3 is the signal schematic representation that one embodiment of the invention memory test equipment carries out frequency test.
Embodiment
For making content of the present invention clear more understandable, below in conjunction with Figure of description, content of the present invention is described further.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art also is encompassed in protection scope of the present invention.
Fig. 1 is a kind of calcspar with memory test equipment 10 of frequency test function of the present invention.Memory test equipment 10 comprises signal acquisition module 11, analog-to-digital conversion module 12, memory module 13, counting module 14 and frequency computation part module 15.Wherein, signal acquisition module is carried out continuous collecting with the measured signal of preset frequency f0, to obtain the sampled signal of a plurality of measured signals.Analog-to-digital conversion module 12 links to each other with signal acquisition module 11, and a plurality of sampled signals are converted to a plurality of digital signal d (0), d (1), d (2) ... the digital signal d (0) that d (n), first sampled signal that wherein obtains change is initial digital signal.Digital signal can be first digital signal " 0 " or second digital signal " 1 ".In one embodiment, analog-to-digital conversion module 12 carries out analog to digital conversion according to the output voltage of sampled signal, when the output voltage of sampled signal during more than or equal to threshold voltage, sampled signal is converted to 1; When output voltage during less than threshold voltage, sampled signal is converted to 0, wherein threshold voltage can be output voltage peaked half.Memory module 13 links to each other with analog-to-digital conversion module 12, and it stores these digital signals d (0) in order, d (1), d (2) ... d (n).Counting module 14 links to each other with memory module 13, begins these digital signals of storing are counted from initial digital signal d (0).Be that 1, d (1) counting is 2 for initialize signal d (0) counting for example ... d (n) counting that is to say that for n+1 the number of 14 pairs of stored digital signals of counting module is counted.Frequency computation part module 15 links to each other with memory module 13 and technology modules 14, the corresponding count value of digital signal that changes during according to the n time digital signal change, the corresponding count value of the digital signal that changes during the n+2 time digital signal change, and preset frequency f0, obtain the cycle of measured signal, and obtain the frequency of measured signal according to cycle of measured signal; Wherein digital signal change refers to from first digital signal " 0 " and is converted to second digital signal " 1 " or is converted to first digital signal " 0 " from second digital signal " 1 ", and n is the positive integer more than or equal to 1.Preferable, frequency computation part module 15 has comparison sub-module, and in one embodiment, comparison sub-module compares each digital signal d (i+1) and previous digital signal d (i) since the 2nd digital signal d (1).When d (i+1) and d (i) are inequality, illustrate that then digital signal d (i+1) changes.In another embodiment of the present invention, whether comparison sub-module changes by the digital signal of relatively judging of digital signal and reference signal.The digital signal that changes when wherein, reference signal is initial digital signal d (0) or last digital signal change.Thus, frequency computation part module 15 in conjunction with the time interval (that is to say the inverse of preset frequency) that sampled signal is gathered, can obtain the period T of measured signal by reading the number that digital signal during three digital signal change takes place.In a preferred embodiment, frequency computation part module 15 is also obtained the period T 1 of a plurality of measured signals, T2 ..., Tn, getting its mean value is normal period, and according to described normal period, gets the standard frequency that its inverse obtains measured signal.
Figure 2 shows that the process flow diagram of memory frequency method of testing of the present invention, Figure 3 shows that and utilize the present invention to carry out the signal schematic representation of frequency test, describe the workflow diagram of memory test equipment of the present invention below with reference to Fig. 2 and Fig. 3 with a specific embodiment in detail.
At first, execution in step S1: with preset frequency continuous collecting is carried out in the measured signal of storer, obtain the sampled signal of a plurality of measured signals.Preferable, preset frequency f0 sets according to the estimated value of measured signal frequency, is the precision that improves frequency test, be generally 10 times of measured signal frequence estimation value and more than.
Then, carry out step S2: a plurality of sampled signals are converted to a plurality of digital signals.Specifically, can according to the size of output voltage, sampled signal be converted to " 1 ", " 0 " two kinds of different digital signals with the output voltage of measured signal as sampled signal.In general, be that output voltage and threshold voltage are compared, if output voltage more than or equal to threshold voltage, then is converted to digital signal " 1 ", otherwise is converted to digital signal " 0 ".
Afterwards, carry out step S3: store a plurality of digital signals in order.As shown in Figure 2, a series of digital signal d (0) after the conversion, d (1), d (2) ... d (n) stores in the storage space of memory test equipment in order.
Then, carry out step S4: begin the digital signal of storing is counted from initial digital signal.Specifically, from the storage space of memory test equipment, read digital signal sequences, and begin counting from initial digital signal d (0).
Next, carry out step S5: the corresponding count value of digital signal that changes when the corresponding count value of digital signal that changes during according to the n time digital signal change and the n+2 time digital signal change, and preset frequency, obtaining the frequency of measured signal, n is the positive integer more than or equal to 1.Specifically, as shown in Figure 2, initial digital signal d (0) is 1, supposes to begin this moment from 1 counting.Digital signal d (3) becomes 0, that is to say the variation that the 1st digital signal taken place, and the corresponding count value of digital signal d (3) is 4; When digital signal d (8), the 2nd variation takes place digital signal is again 1 afterwards, and the corresponding count value of digital signal d (8) is 9; What the 3rd digital signal change (from 1 to 0) took place is digital signal d (14), and its corresponding count value is 15.Thus, according to the 1st digital signal change and the 3rd corresponding count value 4 of digital signal change and 15, the number of digital signal is 12 (comprising d (3) and d (14)) during just can obtaining three signals and changing.
Further, when judging that digital signal changes, in one embodiment, can each digital signal d (i) and previous digital signal d (i-1) be compared to judge that wherein i is the positive integer greater than 1 by since the 2nd digital signal d (1).When d (i) and d (i-1) are inequality, illustrate that then digital signal d (i) changes, the n time variation takes place this moment in record, i=a, the corresponding count value of d (a) is A.Continue successively a back digital signal d (i) to be compared with previous digital signal d (i-1), when d (i) and d (i-1) were inequality again, the n+1 time variation took place at this moment in record again, i=b, and the corresponding count value of d (b) is B; The same, continue again successively a back digital signal d (i) to be compared with previous digital signal d (i-1), when d (i) and d (i-1) were inequality again, the n+2 time variation took place at this moment in record, i=c, the corresponding count value of d (c) is C; According to three count value A of gained, B, C and predetermined sampling frequency f0 can obtain cycle of measured signal, and concrete result of calculation is:
Period T=[(B-A+1)-1] * t+[(C-B+1)-1] * t
=(C-A)*t
Wherein t is the sampling time interval of each sampled signal, t=1/f0.
The cycle of measured signal also just equals the count value of the n+2 time variation and the difference of the count value that the n time changes, with the product of sampling time interval.
Obtain measured signal frequency f=1/T by period T at last.
Certainly, also can directly obtain the measured signal frequency by the count value of the n time digital signal change and the n+2 time digital signal change in conjunction with preset frequency:
Period T=(C-A+1)-1] * t=(C-A) * t.
In another embodiment of the present invention, the digital signal that changes when obtaining the k time digital signal change by digital signal and reference signal, wherein k is more than or equal to 1 and smaller or equal to the positive integer of n+2.Specifically, when k=1, with initial digital signal d (0) as with reference to signal d, will after each digital signal d (i) compare with reference signal d (0).When inequality with d (0), illustrate that then digital signal changes, digital signal change takes place the 1st time this moment in record, i=a, the corresponding count value of d (a) is A.Afterwards, with d (a) as with reference to signal d, will after each digital signal compare with reference signal d (a), until inequality with d (a), the 2nd digital signal change (being k=2) takes place at this moment in record, i=b, the corresponding count value of d (b) is B.Then again with d (b) as with reference to signal d, will after each digital signal compare with reference signal d (b), until inequality with d (b), record and at this moment digital signal change take place the 3rd time, i=c, the corresponding count value of d (c) is C.That is to say that when k=1, reference signal is initial digital signal d (0), when k greater than 1 and during smaller or equal to n+2, the digital signal that reference signal changes when being last digital signal change.At last, by count value A, C and preset frequency can obtain the cycle of measured signal, and then obtain the frequency of measured signal.
In a preferred embodiment of the present invention, can repeat step S1 to S5, obtain the cycle of a plurality of measured signals.As obtaining measured signal period T 1 by the 1st digital signal change and the 3rd digital signal change, obtain measured signal period T 2 by the 3rd digital signal change and the 5th digital signal change, obtain the measured signal period Tn, the mean value of getting these signal periods is normal period, to reduce the generation of error.Afterwards, according to normal period, get the standard frequency that its inverse can obtain measured signal.
Be in the test process of 250KHZ frequency signal to a certain frequency, adopting said method, final measuring error is less than 1%.
In sum, the present invention is converted into digital signal by the memory test equipment with frequency test function with measured signal, and these digital signals are stored, read, the digital signal sequences that reads is carried out a counting number, finally calculate cycle and the frequency of measured signal, expanded the frequency test function of memory test equipment, make testing memory chip conventional project and frequency test can be on same equipment once follow-on test finish, and need not to increase extra test circuit.
Though the present invention discloses as above with preferred embodiment; right described many embodiment only give an example for convenience of explanation; be not in order to limit the present invention; those skilled in the art can do some changes and retouching without departing from the spirit and scope of the present invention, and the protection domain that the present invention advocates should be as the criterion so that claims are described.
Claims (14)
1. the memory test equipment with frequency test function is characterized in that, comprising:
Signal acquisition module is carried out continuous collecting with preset frequency to measured signal, to obtain the sampled signal of a plurality of described measured signals;
Analog-to-digital conversion module is converted to a plurality of digital signals with described a plurality of sampled signals, and described digital signal is first digital signal or second digital signal;
Memory module is stored described a plurality of digital signal in order;
Counting module begins the digital signal of storing is counted from initial digital signal, and described initial digital signal is the digital signal that first sampled signal of obtaining is changed; And
The frequency computation part module, the corresponding count value of digital signal that changes when the corresponding count value of digital signal that changes during according to the n time digital signal change, the n+2 time digital signal change, and described preset frequency, obtain the cycle of described measured signal, and obtain the frequency of described measured signal according to cycle of described measured signal; Wherein said digital signal change is for to be converted to described second digital signal or to be converted to described first digital signal from described second digital signal from described first digital signal, and n is the positive integer more than or equal to 1.
2. memory test equipment according to claim 1, it is characterized in that, described frequency computation part module comprises comparison sub-module, and described comparison sub-module is more described digital signal digital signal previous with it successively, the digital signal that changes when obtaining described digital signal change.
3. memory test equipment according to claim 1, it is characterized in that, described frequency computation part module comprises comparison sub-module, described comparison sub-module is more described digital signal and reference signal successively, the digital signal that changes when obtaining the k time described digital signal change, k is more than or equal to 1 and smaller or equal to the positive integer of n+2; Wherein when k be greater than 1 the time, the digital signal that described reference signal changes when being the k time digital signal change; When k was 1, described reference signal was described initial digital signal.
4. memory test equipment according to claim 1 is characterized in that, it is normal period that the cycle that described frequency computation part module is obtained a plurality of described measured signals is got its mean value, and obtains the standard frequency of measured signal according to described normal period.
5. memory test equipment according to claim 1 is characterized in that, when the output voltage of described sampled signal during more than or equal to threshold voltage, described analog-to-digital conversion module is converted to described first digital signal with described sampled signal; When described output voltage during less than described threshold voltage, described analog-to-digital conversion module is converted to described second digital signal with described sampled signal, described threshold voltage be described output voltage peaked half.
6. memory test equipment according to claim 1 is characterized in that, sets described preset frequency according to the estimated value of described measured signal frequency.
7. memory test equipment according to claim 6 is characterized in that, described preset frequency is more than or equal to 10 times of the estimated value of described measured signal frequency.
8. a memory frequency method of testing is characterized in that, may further comprise the steps:
With preset frequency continuous collecting is carried out in the measured signal of described storer, to obtain the sampled signal of a plurality of described measured signals;
Described a plurality of sampled signals are converted to a plurality of digital signals, and described digital signal is first digital signal or second digital signal;
Store described a plurality of digital signal in order;
Begin the digital signal of storing is counted from initial digital signal, described initial digital signal is the digital signal that first sampled signal of obtaining is changed;
The corresponding count value of digital signal that changes when the corresponding count value of digital signal that changes during according to the n time digital signal change and the n+2 time digital signal change, and described preset frequency, obtain the cycle of described measured signal, and obtain the frequency of described measured signal according to cycle of described measured signal; Wherein said digital signal change is for to be converted to described second digital signal or to be converted to described first digital signal from described second digital signal from described first digital signal, and n is the positive integer more than or equal to 1.
9. memory frequency method of testing according to claim 8 is characterized in that, by more described digital signal digital signal previous with it successively, and the digital signal that changes when obtaining described digital signal change.
10. memory frequency method of testing according to claim 8, it is characterized in that, by more described digital signal and reference signal successively, the digital signal that changes when obtaining the k time described digital signal change, k is more than or equal to 1 and smaller or equal to the positive integer of n+2; Wherein when k be greater than 1 the time, the digital signal that described reference signal changes when being the k time digital signal change; When k was 1, described reference signal was described initial digital signal.
11. memory frequency method of testing according to claim 8 is characterized in that, it is normal period that the cycle of obtaining a plurality of described measured signals is got its mean value, and obtains the standard frequency of measured signal according to described normal period.
12. memory frequency method of testing according to claim 8 is characterized in that, when the output voltage of described sampled signal during more than or equal to threshold voltage, described sampled signal is converted to described first digital signal; When described output voltage during less than described threshold voltage, described sampled signal is converted to described second digital signal, described threshold voltage be described output voltage peaked half.
13. memory frequency method of testing according to claim 8 is characterized in that, sets described preset frequency according to the estimated value of described measured signal frequency.
14. memory frequency method of testing according to claim 13 is characterized in that, described preset frequency is more than or equal to 10 times of the estimated value of described measured signal frequency.
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Application publication date: 20131009 |