CN107505512A - Electronics intelligent fault monitoring method and device based on JTAG technologies - Google Patents
Electronics intelligent fault monitoring method and device based on JTAG technologies Download PDFInfo
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- CN107505512A CN107505512A CN201710288755.XA CN201710288755A CN107505512A CN 107505512 A CN107505512 A CN 107505512A CN 201710288755 A CN201710288755 A CN 201710288755A CN 107505512 A CN107505512 A CN 107505512A
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- self
- jtag
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
Abstract
The invention discloses a kind of electronics intelligent fault monitoring method and device based on JTAG technologies, comprise the following steps：1）Electronics are configured using JTAG Technology designs, acquisition and recording self test data collects as self-test data storehouse, and 2）The self-test data and failure situation accumulated using the analysis of artificial intelligence learning method, structure fault model, 3）With the self-test data storehouse training fault model of electronics, the fault model optimized, 4）Persistent accumulation data and fault diagnosis result, periodicity new model, obtain the fault detection and diagnosis model of Continuous optimization, based on above-mentioned special purpose device, including jtag interface and JTAG self test controllers, specially designed self-test master control borad is provided with JTAG self test controllers, the present invention can improve equipment Self-testability energy, real-time diagnosis abort situation, longtime running can Accurate Prediction equipment failure, may out of order part in task just being changed before equipment is turned out for work.
Description
Technical field
The present invention provides a kind of electronics intelligent fault monitoring method and device based on JTAG technologies, is related to electronics and sets
Standby self-test and fault diagnosis field, it is specifically to be related to jtag test and maintenance technology and artificial intelligence technology.
Background technology
Hyundai electronicses equip becoming increasingly complex of composition, and the complexity of the integrated and electronic system of electronic circuit is increasingly
Improve, which greatly enhances the fault detection and diagnosis positioning difficulty of equipment.
The content of the invention
The purpose of the present invention is to propose to a set of electronics intelligent fault monitoring method and device based on JTAG technologies, profit
Equipment Self-testability energy is improved with JTAG technologies.
The present invention is achieved through the following technical solutions：
A kind of electronics intelligent fault monitoring method based on JTAG technologies, comprises the following steps：
（1）Electronics are configured using JTAG Technology designs, acquisition and recording self test data, collected as self-test data storehouse；
（2）Using the self-test data and failure situation of the analysis accumulation of artificial intelligent deep learning method, electronics are built
Fault model；
（3）Fault model, the fault model optimized are trained with the self-test data storehouse of electronics；
（4）Persistent accumulation data and fault diagnosis result, periodic iterations new model, obtain the failure prison of more preferable Continuous optimization
Survey and diagnostic model.
A kind of special purpose device of electronics intelligent fault monitoring method based on above-mentioned JTAG technologies, including jtag interface
With JTAG self test controllers, be provided with self-test master control borad in JTAG self test controllers, self-test master control borad including CPU,
JTAG main controllers, jtag interface extension, self-test data memory, self-test communication interface, wherein, one end of JTAG main controllers
Link, the link jtag interface extension of the JTAG main controllers other end, jtag interface expanding external equipment jtag interface, test oneself with CPU
Examination data storage and self-test communication interface link with CPU respectively.
Compared with the prior art, present invention design proposes a set of intelligent fault monitoring diagnostic method and special purpose device, base
Equipment Self-testability energy is improved in JTAG technologies, long term accumulation equipment self-test data, is adopted to different equipments on this basis
Fault model is built with machine learning method --- the degree of association i.e. between test data result and equipment failure, tested oneself with equipment
Big data is trained and correction model, can be in real time according to self-test data tracing trouble position, and longtime running even can be according to
Equipment failure is accurately predicted according to current test data, may out of order portion in task just being changed before equipment is turned out for work
Part.
The present invention is carried out with reference to specific embodiment explanation is explained in detail.
Brief description of the drawings
Fig. 1 --- electronic equipment internal configures the basic principle schematic of jtag test structure.
Fig. 2 --- electronic device exterior configures the basic principle schematic of jtag test structure.
Fig. 3 --- the process principle figure of electronics intelligent fault monitoring and diagnostic method of the present invention.
Fig. 4 --- the fault detection and diagnosis modular concept schematic diagram in the present invention.
Fig. 5 --- fault model structure of the invention and the principle schematic of optimization.
A kind of Fig. 6 --- line construction schematic diagram of the self-test master control borad of special purpose device of the present invention.
Embodiment
The present invention relates to jtag test and maintenance technology and artificial intelligence technology, the Self-testability of electronics can this
It is a kind of design attributes in matter, self-test function and interface is inserted during equipment Design, so that system is with higher
Testability.
In modern large scale digital circuit during, jtag interface is requisite interfaces, based on JTAG technologies
The Self-testability energy of equipment can be improved in terms of two：First, the design phase configures jtag test structure in device interior, make
Equipment has a higher self-test fault coverage, framework is as shown in Figure 1；Second, in device external structure JTAG master control tests
And interface, the jtag interface that equipment is drawn is linked into, the testability of equipment can be improved, Technical Architecture is as shown in Figure 2.
Based on above-mentioned, the present invention proposes a kind of electronics intelligent fault monitoring based on JTAG technologies and diagnosis side
Method, comprise the following steps（It is shown in Figure 3）：
（1）Electronics are configured using JTAG Technology designs, improve the Self-testability energy of existing electronics, while gather note
Self test data is recorded, is collected as self-test data storehouse；
（2）Use artificial intelligent deep learning method（Deep Mind）Analyze the self-test data and failure situation of accumulation, structure
The fault model of electronics；
（3）Fault model, the fault model optimized are trained with the self-test data storehouse of electronics；
（4）Persistent accumulation data and fault diagnosis result, periodic iterations new model, obtain the failure prison of more preferable Continuous optimization
Survey and diagnostic model.
The self-test data storehouse of structuring is formed after the self-test data long term accumulation of electronics, Database field is main
Including time, self-test project, test data, equipment fault code etc..Equipment fault code is defined on equipment design process
In determined by priori, characterize the function of equipment and the missing of index or reduction, partial fault can directly be covered by self-test
Lid, some failure need to draw by analysis.The fault detection and diagnosis model of specific electron equipment is by this two parts
Form, the method for machine learning can be used to obtain a unified model, failure code is obtained according to test data.
Shown in Figure 4, fault detection and diagnosis model is substantially each of fault type code and self-test data
Relativity measurement between variable,, wherein, Y is failure generation
Code, X are self-test data, correlations of the r between failure code and self-test data, and fault diagnosis is then each correlation
Thresholding.
Fault detection and diagnosis model construction process based on artificial intelligence machine study is to determine correlation ri, j mistake
Journey, partial correlation values can be by priori direct constructions, and partial correlation values need to train by substantial amounts of data analysis
Arrive.As shown in figure 5, its step is summarized as follows：
（1）The fault threshold of one group of correlation and correlation is fixed tentatively by priori；
（2）The data point reuse correlation obtained according to self-test, optimize fault model；
（3）Utilize new test data testing model and the correlation of adjustment more new model.
In addition, in two kinds of above-mentioned electronics JTAG self-test frameworks, the present invention also design proposes a kind of special dress
Put, including jtag interface and JTAG self test controllers, JTAG self test controllers are interior to be provided with self-test master control borad, its circuit knot
Structure principle is as shown in fig. 6, self-test master control borad is mainly extended by CPU, JTAG main controller SN74LVT8980A, jtag interface
LVT8986, self-test data memory, self-test communication interface etc. form.
SN74LVT8980A is the embedded testing bus control unit with 8 universal host machine interfaces of TI companies
IEEE STD 1149.1 (JTAG), a jtag interface is externally provided, control interface is typical address data control bus
Interface.
JTAG main controllers are controlled by CPU, produce jtag test sequential, there is provided TCK, TMS, TDI, TDO, TRST signal arrive
In jtag test chain.
SN74LVT8986 is that the 3V of TI companies links addressable scanning port, multiple spot addressable IEEE standards
1149.1 (JTAG) TAP transceivers, SN74LVT8986 A9-A0 and P2-P0 is by toggle switch option and installment, two panels
It can be cascaded between SN74LVT8986 by CTDI and CTDO signals.
Self-test master control borad extends jtag interface quantity by scanning bridge piece, can form star with multiple test objects and open up
Flutter structure.During self-test, self-test master control borad generation JTAG chain test vectors, control test process, read test result,
Judge measurand failure whether and abort situation, outside can be transmitted test data to, while self test results are stored
In band self-test data memory.
Claims (2)
1. a kind of electronics intelligent fault monitoring method based on JTAG technologies, comprises the following steps：
（1）Electronics are configured using JTAG Technology designs, acquisition and recording self test data, collected as self-test data storehouse；
（2）Using the self-test data and failure situation of the analysis accumulation of artificial intelligent deep learning method, electronics are built
Fault model；
（3）Fault model, the fault model optimized are trained with the self-test data storehouse of electronics；
（4）Persistent accumulation data and fault diagnosis result, periodic iterations new model, obtain the failure prison of more preferable Continuous optimization
Survey and diagnostic model.
2. a kind of device of the electronics intelligent fault monitoring method based on JTAG technologies according to claim 1, including
Jtag interface and JTAG self test controllers, JTAG self test controllers are interior to be provided with self-test master control borad, self-test master control borad bag
CPU, JTAG main controller, jtag interface extension, self-test data memory, self-test communication interface are included, wherein, JTAG main controllers
One end linked with CPU, the link jtag interface extension of the JTAG main controllers other end, jtag interface expanding external equipment JTAG connects
Mouthful, self-test data memory and self-test communication interface link with CPU respectively.
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| CN201710288755.XA CN107505512A (en) | 2017-04-27 | 2017-04-27 | Electronics intelligent fault monitoring method and device based on JTAG technologies |
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| CN109884499A (en) * | 2019-02-01 | 2019-06-14 | 京微齐力(北京)科技有限公司 | A kind of method and system chip of artificial intelligence module on test macro chip |
| CN109919322A (en) * | 2019-02-01 | 2019-06-21 | 京微齐力(北京)科技有限公司 | A kind of method and system chip of artificial intelligence module on test macro chip |
| CN116955045A (en) * | 2023-09-20 | 2023-10-27 | 江苏嘉擎信息技术有限公司 | Remote JTAG multiplexing test method and system |
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| CN109884499A (en) * | 2019-02-01 | 2019-06-14 | 京微齐力(北京)科技有限公司 | A kind of method and system chip of artificial intelligence module on test macro chip |
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Application publication date: 20171222 |