CN108155892A - A kind of RS trigger architectures for eliminating nondeterministic statement - Google Patents
A kind of RS trigger architectures for eliminating nondeterministic statement Download PDFInfo
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- CN108155892A CN108155892A CN201711430846.9A CN201711430846A CN108155892A CN 108155892 A CN108155892 A CN 108155892A CN 201711430846 A CN201711430846 A CN 201711430846A CN 108155892 A CN108155892 A CN 108155892A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/013—Modifications of generator to prevent operation by noise or interference
Abstract
A kind of RS trigger architectures for eliminating nondeterministic statement, belong to technical field of integrated circuits.Including the first nor gate and the second nor gate, the first input end of first nor gate and the second nor gate connects the first input end of RS trigger architectures, second input terminal of the first nor gate and the second nor gate connects the second input terminal of RS trigger architectures, first output terminal of the output terminal of first nor gate as RS trigger architectures, second output terminal of the output terminal of second nor gate as RS trigger architectures, the rest-set flip-flop available for NAND gate structure.The first phase inverter and the second phase inverter are further included in some embodiments, first phase inverter is connected between the first input end of RS trigger architectures and the first input end of the first nor gate, second phase inverter is connected between the second input terminal of RS trigger architectures and the second input terminal of the second nor gate, the rest-set flip-flop available for nor gate structure.The present invention reduces production cost while noise cancellation effect is improved.
Description
Technical field
The present invention relates to technical field of integrated circuits more particularly to a kind of RS trigger architectures for eliminating nondeterministic statement.
Background technology
Nowadays, rest-set flip-flop is widely used in each adhesive integrated circuit, and IGBT drive circuit is since it is with voltage-type
Driving, driving power is small, switching speed is high, saturation pressure reduces and can be in a series of applications such as high voltage withstanding, high current the advantages of,
Good comprehensive performance is shown, so as to be used widely.However in IGBT drive circuit, because after LDMOS pipes
Clutter can be brought into makes waveform become very poor, so needing to be filtered planarization into filter circuit.Again due to pulse signal without
Method driving power MOSFET element, in the filter circuit of IGBT drive circuit, last rising edge pulse and failing edge pulse
Narrow pulse signal is reduced into square-wave signal to high-end floating ground VS by signal by rest-set flip-flop, but in its course of work
Certain noise can be generated, influences the normal work of electronic equipment.
At present, the rest-set flip-flop structure being made of nor gate, when two input terminals are all invalid, it may appear that uncertain shape
State；The rest-set flip-flop structure being made of NAND gate, when two input terminals are all effective, it may appear that nondeterministic statement.Therefore, it is necessary to
A kind of RS trigger architectures for the stabilization that can achieve the effect that eliminate noise and production cost very well.
Invention content
Part against the above deficiency, the present invention provide a kind of RS trigger architectures for eliminating nondeterministic statement, are improving noise
Production cost is reduced while eradicating efficacy.
The technical scheme is that：
A kind of RS trigger architectures for eliminating nondeterministic statement, including two input terminals and two output terminals, the RS triggerings
Structure first including the first nor gate NOR1 and the second nor gate NOR2, the first nor gate NOR1 and the second nor gate NOR2 is defeated
Enter the second input terminal of the first input end that end connects the RS trigger architectures, the first nor gate NOR1 and the second nor gate NOR2
Connect the second input terminal of the RS trigger architectures, the output terminal of the first nor gate NOR1 as the RS trigger architectures first
Output terminal, the second output terminal of the output terminal of the second nor gate NOR2 as the RS trigger architectures.
Specifically, further including the first phase inverter INV1 and the second phase inverter INV2, the first phase inverter INV1 is connected on the RS
Between the first input end of the first input end of trigger architecture and the first nor gate NOR1, the second phase inverter INV2 is connected on the RS
Between the second input terminal of second input terminal of trigger architecture and the second nor gate NOR2.
Specifically, the first nor gate NOR1 includes the second NMOS tube MN2, third NMOS tube MN3, the second PMOS tube
The grid of MP2 and third PMOS tube MP3, the second PMOS tube MP2 connect the grid of the second NMOS tube MN2 and as described first or
The second input terminal of NOT gate NOR1, the source electrode of drain electrode connection third PMOS tube MP3, source electrode connection supply voltage VDD；Third
The grid of the grid connection third PMOS tube MP3 of NMOS tube MN3 and as the first input end of the first nor gate NOR1,
The source electrode ground connection of the drain electrode of drain electrode connection the second NMOS tube MN2 and third PMOS tube MP3, source electrode and the second NMOS tube MN2
GND；
The second nor gate NOR2 includes the 5th NMOS tube MN5, the 6th NMOS tube MN6, the 5th PMOS tube MP5 and the 6th
The grid of PMOS tube MP6, the 5th PMOS tube MP5 connect the grid of the 6th NMOS tube MN6 and are used as the second nor gate NOR2
First input end, the source electrode of the 6th PMOS tube MP6 of drain electrode connection, source electrode connection supply voltage VDD；6th NMOS tube
The grid of MN6 connects the grid of the 6th PMOS tube MP6 and as the second input terminal of the second nor gate NOR2, and drain electrode connects
Meet the source electrode ground connection GND of the drain electrode of the 5th NMOS tube MN5 and the 6th PMOS tube MP6, source electrode and the 5th NMOS tube MN5.
Specifically, the first phase inverter INV1 includes the first NMOS tube MN1 and the first PMOS tube MP1, the first NMOS tube
The grid of MN1 connects the grid of the first PMOS tube MP1 and the input terminal as the first phase inverter INV1 connects the RS and touches
The first input end of structure is sent out, drain electrode connects the drain electrode of the first NMOS tube MN1 and as the defeated of the first phase inverter INV1
Outlet connects the first input end of the first nor gate NOR1, and source electrode connects supply voltage VDD, the first NMOS tube MN1's
Source electrode is grounded GND；
The second phase inverter INV2 includes the 4th NMOS tube MN4 and the 4th PMOS tube MP4, the grid of the 4th NMOS tube MN4
Pole connects the grid of the 4th PMOS tube MP4 and the input terminal as the second phase inverter INV2 connects the RS trigger architectures
Second input terminal, the drain electrode of the 4th NMOS tube MN4 of drain electrode connection and the output terminal as the second phase inverter INV2 connect
The second input terminal of the second nor gate NOR2, the source electrode ground connection of source electrode connection supply voltage VDD, the 4th NMOS tube MN4
GND。
Beneficial effects of the present invention are：A kind of RS trigger architectures for eliminating nondeterministic statement provided by the invention, it is applicable
In rest-set flip-flop, rest-set flip-flop can be avoided to generate uncertain state, while simple in structure, with existing elimination nondeterministic statement
Structure compared to reducing production cost.
Description of the drawings
Fig. 1 is the schematic diagram of rest-set flip-flop being made of nor gate.
Fig. 2 is the truth table of rest-set flip-flop being made of nor gate.
Fig. 3 is the oscillogram of rest-set flip-flop input signal being made of nor gate.
Fig. 4 is that the present invention is used for the RS trigger architectures of a kind of elimination nondeterministic statement of rest-set flip-flop being made of NAND gate
Schematic diagram.
Fig. 5 is that the present invention is used for the RS trigger architectures of a kind of elimination nondeterministic statement of rest-set flip-flop being made of nor gate
Schematic diagram.
Fig. 6 is that the RS of a kind of elimination nondeterministic statement of rest-set flip-flop for being used to be made of nor gate in embodiment triggers knot
The schematic diagram of structure.
Fig. 7 is that the RS of a kind of elimination nondeterministic statement of rest-set flip-flop for being used to be made of nor gate in embodiment triggers knot
The truth table of structure；
Fig. 8 is that the RS of a kind of elimination nondeterministic statement of rest-set flip-flop for being used to be made of nor gate in embodiment triggers knot
The eradicating efficacy oscillogram of structure.
Specific embodiment
The detailed description present invention in the following with reference to the drawings and specific embodiments.
A kind of RS trigger architectures for eliminating nondeterministic statement proposed by the present invention can be used in rest-set flip-flop, such as Fig. 4 institutes
The nondeterministic statement that the present invention is used to eliminate two input terminals of the rest-set flip-flop of NAND gate structure while occurs when being low is shown as,
Including two input terminals and two output terminals, RS trigger architectures are connected on before the input terminal of rest-set flip-flop, and first input end connects
Connect the signal of the S input terminals connection of former rest-set flip-flop, the letter of the R input connection of the former rest-set flip-flop of the second input terminal connection
Number, the first output terminal connects the S input terminals of rest-set flip-flop, and second output terminal connects the R input of rest-set flip-flop；RS is triggered
Structure first including the first nor gate NOR1 and the second nor gate NOR, the first nor gate NOR1 and the second nor gate NOR2 is defeated
Enter the first input end of end connection RS trigger architectures, the second input terminal connection of the first nor gate NOR1 and the second nor gate NOR2
Second input terminal of RS trigger architectures, the first output terminal of the output terminal of the first nor gate NOR1 as RS trigger architectures, second
Second output terminal of the output terminal of nor gate NOR2 as RS trigger architectures.
The present invention is illustrated in figure 5 to be used to eliminate two input terminals of the rest-set flip-flop of nor gate structure while when being high go out
Existing nondeterministic statement increases the first phase inverter INV1 and the second phase inverter INV2, the first phase inverter INV1 on the basis of Fig. 4
It is connected between the first input end of RS trigger architectures and the first input end of the first nor gate NOR1, the second phase inverter INV2 is connected on
Between the second input terminal of second input terminal of RS trigger architectures and the second nor gate NOR2.
Reach the technological means that predetermined purpose is taken and the technique effect actually generated for the present invention is further explained, with
Under by taking the rest-set flip-flop of nor gate structure as an example, and with reference to attached drawing to the present invention specific embodiment, structure feature and its work(
Effect, detailed description are as follows.
Fig. 1 proposes the schematic diagram for the rest-set flip-flop being made of nor gate, including transistor M1-M8, including R input, S
Input terminal, Q output and Q- output terminals.
Fig. 2 is the truth table of nor gate structure rest-set flip-flop.
Its characteristic equation is
When S input terminals and R input input high level simultaneously, trigger will appear nondeterministic statement.
Fig. 3 is the sequential logic oscillogram of nor gate structure rest-set flip-flop.
Fig. 5 proposes a kind of RS trigger architectures for eliminating nondeterministic statement, is touched with the RS for solving existing nor gate structure
Send out the nondeterministic statement of device input terminal.
Fig. 6 show the RS triggering knots of the elimination nondeterministic statement for the rest-set flip-flop of nor gate structure in the present embodiment
Structure,
The grid that first NMOS tube MN1 and the first PMOS tube MP1 forms the first phase inverter INV1, the first NMOS tube MN1 connects
The first input end of the grid of the first PMOS tube MP1 and the input terminal connection RS trigger architectures as the first phase inverter INV1 is connect,
Its drain electrode connects the drain electrode of the first NMOS tube MN1 and the output terminal as the first phase inverter INV1 connects the first nor gate NOR1's
First input end, the source electrode ground connection GND of source electrode connection supply voltage VDD, the first NMOS tube MN1；4th NMOS tube MN4 and
Four PMOS tube MP4 form the grid and work of the 4th PMOS tube MP4 of grid connection of the second phase inverter INV2, the 4th NMOS tube MN4
Input terminal for the second phase inverter INV2 connects the second input terminal of RS trigger architectures, the 4th NMOS tube MN4's of drain electrode connection
It drains and the output terminal of the second phase inverter INV2 is used as to connect the second input terminal of the second nor gate NOR2, source electrode connection power supply
The source electrode ground connection GND of voltage VDD, the 4th NMOS tube MN4.
Second NMOS tube MN2, third NMOS tube MN3, the second PMOS tube MP2 and third PMOS tube MP3 form first or non-
Door NOR1, the grid of the second PMOS tube MP2 connect the grid of the second NMOS tube MN2 and second defeated as the first nor gate NOR1
Enter end, the source electrode of drain electrode connection third PMOS tube MP3, source electrode connection supply voltage VDD；The grid of third NMOS tube MN3
Connect the grid of third PMOS tube MP3 and as the first input end of the first nor gate NOR1, drain electrode the second NMOS tube of connection
The source electrode ground connection GND of the drain electrode of MN2 and third PMOS tube MP3, source electrode and the second NMOS tube MN2；5th NMOS tube MN5,
Six NMOS tube MN6, the 5th PMOS tube MP5 and the 6th PMOS tube MP6 form the second nor gate NOR2, the grid of the 5th PMOS tube MP5
Pole connects the grid of the 6th NMOS tube MN6 and as the first input end of the second nor gate NOR2, the 6th PMOS of drain electrode connection
The source electrode of pipe MP6, source electrode connection supply voltage VDD；The grid of 6th NMOS tube MN6 connects the grid of the 6th PMOS tube MP6
And as the second input terminal of the second nor gate NOR2, the leakage of drain electrode connection the 5th NMOS tube MN5 and the 6th PMOS tube MP6
The source electrode ground connection GND of pole, source electrode and the 5th NMOS tube MN5.
The signal of the input terminal connection original rest-set flip-flop S input terminal connections of first phase inverter INV1, the second phase inverter INV2
The former rest-set flip-flop R input connection of input terminal connection signal, the output terminal connection nor gate structure of the first nor gate NOR1
Rest-set flip-flop S input terminals, the second nor gate NOR2 output terminal connection nor gate structure rest-set flip-flop R input.
In Fig. 6, the first phase inverter INV1 connects with the first input end of the first nor gate NOR1, and input terminal connects second or non-simultaneously
The first input end of door NOR2；Second phase inverter INV2 connects with the second input terminal of the second nor gate NOR2, and input terminal is same
When connect the second input terminal of the first nor gate NOR1, form the structure being mutually coupled.
Fig. 7 is applied for the present invention in the rest-set flip-flop of nor gate structure, and the truth table of rest-set flip-flop is led when there is noise
Two input terminals of rest-set flip-flop is caused the situation of high level set simultaneously occur, elimination nondeterministic statement proposed by the present invention
The first output terminal S ' and second output terminal R ' the then reset again of RS trigger architectures ensure the normal work of rest-set flip-flop.
Fig. 8 is applied for the present invention in the rest-set flip-flop of nor gate structure, the input waveform figure of rest-set flip-flop.
In summary it can be seen, it is provided by the invention it is a kind of eliminate nondeterministic statement RS trigger architectures, can be used for it is non-
The rest-set flip-flop of door and the rest-set flip-flop of nor gate structure can not only avoid what two input terminals of rest-set flip-flop inputted
Uncertain noise, so as to which rest-set flip-flop be avoided to generate uncertain state；It is also possible to effectively improve circuit open state
Stability.
It should be noted that RS trigger architectures provided by the invention can also be applied to occur not in other integrated circuits
Determine that state is eliminated.
Those of ordinary skill in the art can make various do not depart from originally according to these technical inspirations disclosed by the invention
The other various specific deformations and combination of essence are invented, these deformations and combination are still within the scope of the present invention.
Claims (4)
1. a kind of RS trigger architectures for eliminating nondeterministic statement, which is characterized in that including two input terminals and two output terminals, institute
It states RS trigger architectures and includes the first nor gate (NOR1) and the second nor gate (NOR2), the first nor gate (NOR1) and second or non-
The first input end of door (NOR2) connects the first input end of the RS trigger architectures, the first nor gate (NOR1) and second or non-
Second input terminal of door (NOR2) connects the second input terminal of the RS trigger architectures, and the output terminal of the first nor gate (NOR1) is made
For the first output terminal of the RS trigger architectures, the output terminal of the second nor gate (NOR2) as the RS trigger architectures second
Output terminal.
2. the RS trigger architectures according to claim 1 for eliminating nondeterministic statement, which is characterized in that further include the first reverse phase
Device (INV1) and the second phase inverter (INV2), the first phase inverter (INV1) are connected on the first input end and of the RS trigger architectures
Between the first input end of one nor gate (NOR1), the second phase inverter (INV2) is connected on the second input terminal of the RS trigger architectures
And second nor gate (NOR2) the second input terminal between.
3. the RS trigger architectures according to claim 1 or 2 for eliminating nondeterministic statement, which is characterized in that
First nor gate (NOR1) including the second NMOS tube (MN2), third NMOS tube (MN3), the second PMOS tube (MP2) and
Third PMOS tube (MP3), the grid of the second PMOS tube (MP2) connect the grid of the second NMOS tube (MN2) and as described first
Second input terminal of nor gate (NOR1), the source electrode of drain electrode connection third PMOS tube (MP3), source electrode connection supply voltage
(VDD)；The grid of the grid connection third PMOS tube (MP3) of third NMOS tube (MN3) is simultaneously used as first nor gate
(NOR1) first input end, drain electrode connection the second NMOS tube (MN2) and third PMOS tube (MP3) drain electrode, source electrode with
The source electrode ground connection (GND) of second NMOS tube (MN2)；
Second nor gate (NOR2) including the 5th NMOS tube (MN5), the 6th NMOS tube (MN6), the 5th PMOS tube (MP5) and
6th PMOS tube (MP6), the grid of the 5th PMOS tube (MP5) connect the grid of the 6th NMOS tube (MN6) and as described second
The first input end of nor gate (NOR2), the source electrode of drain electrode the 6th PMOS tube (MP6) of connection, source electrode connection supply voltage
(VDD)；The grid of 6th NMOS tube (MN6) connects the grid of the 6th PMOS tube (MP6) and is used as second nor gate
(NOR2) the second input terminal, drain electrode connection the 5th NMOS tube (MN5) and the 6th PMOS tube (MP6) drain electrode, source electrode with
The source electrode ground connection (GND) of 5th NMOS tube (MN5).
4. the RS trigger architectures according to claim 2 for eliminating nondeterministic statement, which is characterized in that
First phase inverter (INV1) includes the first NMOS tube (MN1) and the first PMOS tube (MP1), the first NMOS tube (MN1)
Grid connect the grid of the first PMOS tube (MP1) and the input terminal connection RS as first phase inverter (INV1) is touched
The first input end of structure is sent out, the drain electrode of drain electrode the first NMOS tube of connection (MN1) is simultaneously used as first phase inverter (INV1)
Output terminal connect the first input end of first nor gate (NOR1), source electrode connection supply voltage (VDD), the first NMOS
Manage the source electrode ground connection (GND) of (MN1)；
Second phase inverter (INV2) includes the 4th NMOS tube (MN4) and the 4th PMOS tube (MP4), the 4th NMOS tube (MN4)
Grid connect the grid of the 4th PMOS tube (MP4) and the input terminal connection RS as second phase inverter (INV2) is touched
The second input terminal of structure is sent out, the drain electrode of drain electrode the 4th NMOS tube (MN4) of connection is simultaneously used as second phase inverter (INV2)
Output terminal connect the second input terminal of second nor gate (NOR2), source electrode connection supply voltage (VDD), the 4th NMOS
Manage the source electrode ground connection (GND) of (MN4).
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| CN201711430846.9A CN108155892A (en) | 2017-12-26 | 2017-12-26 | A kind of RS trigger architectures for eliminating nondeterministic statement |
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| CN201711430846.9A CN108155892A (en) | 2017-12-26 | 2017-12-26 | A kind of RS trigger architectures for eliminating nondeterministic statement |
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Cited By (2)
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| CN108880527A (en) * | 2018-08-17 | 2018-11-23 | 电子科技大学 | A kind of interface circuit being compatible with more level inputs |
| CN111030669A (en) * | 2019-12-30 | 2020-04-17 | 科世达(上海)机电有限公司 | RS latch, RS trigger and controller |
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Application publication date: 20180612 |