TWI457896B - Gate driver - Google Patents

Description

Gate driver

The present invention relates to a gate driver, and more particularly to a gate driver that can reduce input noise.

Please refer to FIG. 1 , which is a schematic diagram of a conventional liquid crystal display panel 100 . As shown in FIG. 1 , the liquid crystal display panel 100 includes a gate driver 110 and a source driver 120 , wherein the gate driver 110 is connected to the plurality of scan lines G1 , G2 , G3 , . . . The scan line is turned on to turn on a thin film transistor (TFT) on the scan line, and the source driver 120 is connected to the plurality of data lines D1, D2, ..., and is used to transmit the display data to the pixel electrode of the pixel. in. Since the operation of the liquid crystal display panel 100 shown in FIG. 1 should be well known to those of ordinary skill in the art, the details are not described herein.

When the liquid crystal display panel 100 is in operation, the data signal outputted by the source driver 120 affects the voltage level of the scan line through the coupling capacitance Cgd between the data line and the scan line, especially when the voltage level of the scan line is At low gate voltage levels, this effect transiently affects the voltage of the P-substrate in the gate driver 110, which in turn causes glitches in the internal logic signal. In addition, if the high-speed interface technology used by the source driver 120 is followed, the coupling capacitor interference problem will be more serious when the logic voltage is reduced to 1.8V.

The current solution to the above problem is to add a resistor-capacitor filter to the gate driver 110. However, the width of the required filtering noise is often due to different panel sizes, Indium-Tin Oxide (ITO) layers. The resistance value or the wafer bonding condition varies, which causes design troubles.

Accordingly, it is an object of the present invention to provide a gate driver that utilizes a logic circuit to automatically determine an abnormal signal that is subject to noise interference and process it into a normal signal to solve the above problem.

According to an embodiment of the invention, a gate driver includes a receiving unit and a set/reset latch type circuit, the receiving unit is configured to receive a first signal and a second signal, wherein the first signal and the first The second signal is a complementary signal; the set/reset latch type circuit is configured to receive the first signal and the second signal, and reduce the noise of the first signal to generate a processed first signal.

Referring to FIG. 2, FIG. 2 is a schematic diagram of a gate driver 200 according to an embodiment of the present invention. As shown in FIG. 2, the gate driver 200 is coupled to a timing controller 202 and includes A receiving unit 210, a SR latching-type circuit 220, and a processing circuit 230. The gate driver 200 and the timing controller 202 are formed on a liquid crystal display panel, and the gate driver 200 receives a clock signal CPV and its complementary signal CPVB and other control signals (not shown) from the timing controller 202 to sequentially generate more The gate control signal V _{G is} to the scan line on the liquid crystal display panel.

In operation of the gate driver 200, first, the receiving unit 210 receives the clock signal CPV and its complementary signal CPVB from the timing controller 202. Then, the set/reset latch type circuit 220 receives the clock signal CPV and its complementary signal CPVB, and reduces the noise of the clock signal CPV to generate a processed clock signal CPVI. Finally, the processing circuit 230 receives the processed clock signal CPVI and other control signals (not shown) from the timing controller 202 to sequentially generate a plurality of gate control signals V _G to the scan lines on the liquid crystal display panel.

In detail, referring to the schematic diagram of the set/reset latch type circuit 220 shown in FIG. 3, the set/reset latch type circuit 220 includes a first logic circuit 310, a latch circuit 320, and a second. The logic circuit 330, wherein the first logic circuit 310 includes two inverters 312, 314 and two NAND gates 316, 318, and the latch circuit 320 is a set/reset reverse gate latch ( SR NAND latch, and includes two mutually coupled anti-gates 322, 324, and the second logic circuit 330 includes a reverse gate 332 and an inverter 334. In addition, when the gate driver is activated, the input signal V _{P of the} reverse gate is directly set to "1".

In the operation of setting/resetting the latch type circuit 220, first, the inverter 312 receives the complementary signal CPVB to generate a reverse post-complement signal, and then the gate 316 receives The clock signal CPV and the reverse post-complement signal generate a set signal SETB; at the same time, the inverter 314 receives the clock signal CPV to generate a reverse post-clock signal, and then the gate 318 receives the complementary signal CPVB and the reverse direction. The pulse signal generates a reset signal RSTB. Then, the latch circuit 320 receives the set signal SETB and the reset signal RSTB, and generates an output signal Q, wherein the output signal Q can be regarded as a clock signal after the noise processing. Finally, the output signal Q is processed by the inverse gate 332 and the inverter 334 to generate a processed clock signal CPVI.

Please refer to FIG. 4, which is a timing diagram of the clock signal CPV, the complementary signal CPVB, and the processed clock signal CPVI. As shown in Figure 4, when the pulse signal CPV and the complementary signal CPVB are (1, 0) respectively, the setting signal SETB is "0", and the processed clock signal CPVI is "1"; and the pulse signal CPV is complementary. When the signal CPVB is (0, 1), the reset signal RSTB is “0”, and the clock signal CPVI is “0” after processing. That is, the set/reset latch type circuit 220 automatically processes the error state when the clock signal CPV and the complementary signal CPVB are (1, 1) or respectively (0, 0) (ie, 4th) The glitch 402, 404) shown in the figure.

In addition, the set/reset latch type circuit 220 shown in FIG. 3 is merely illustrative and not a limitation of the present invention. In other embodiments of the present invention, the latch circuit 320 may be replaced with other forms. The latch circuit, and the first logic circuit 310 can also adopt other circuit architectures to generate the setting signal SETB and the reset signal RSTB. In addition, the architecture of the second logic circuit 330 is also merely an example, which may be replaced with other forms of logic circuits, or directly removed to cause the latch circuit 320 to lose. Output Q is directly used as the output of the set/reset latch type circuit 220. Variations in the above design are all within the scope of the present invention.

In addition, the set/reset latch type circuit 220 of the present invention is not limited to processing the clock signal CPV and the complementary signal CPVB from the timing controller, but can be used to process other complementary signals to eliminate similar surges. Noise interference.

Briefly summarized, the gate driver of the present invention includes a set/reset latch type circuit that can be used to receive the first signal and the second signal complementary thereto, and to reduce the noise of the first signal. A first signal after processing is generated. Compared with the prior art, the gate driver of the present invention having a set/reset latch type circuit can be widely applied to various panels, has a simple structure, and can reliably reduce noise interference to solve the conventional technology. problem.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100‧‧‧LCD panel

110, 200‧‧ ‧ gate driver

120‧‧‧Source Driver

202‧‧‧Sequence Controller

210‧‧‧ Receiving unit

220‧‧‧Set/Reset Latch Type Circuit

230‧‧‧Processing Circuit

310‧‧‧First logic circuit

312, 314, 334‧‧‧ reverser

316, 318, 322, 324, 332‧‧ ‧ anti-gate

320‧‧‧Latch circuit

330‧‧‧Second logic circuit

Cgd‧‧‧Coupling Capacitor

TFT‧‧‧thin film transistor

G1~G3‧‧‧ scan line

D1~D2‧‧‧ data line

FIG. 1 is a schematic view of a conventional liquid crystal display panel 100.

2 is a schematic diagram of a gate driver 200 in accordance with an embodiment of the present invention.

Figure 3 is a schematic diagram of the set/reset latch type circuit shown in Figure 2.

Figure 4 is a timing diagram of the clock signal CPV, the complementary signal CPVB, and the processed clock signal CPVI shown in Figure 3.

200‧‧ ‧ gate driver

202‧‧‧Sequence Controller

210‧‧‧ Receiving unit

220‧‧‧Set/Reset Latch Type Circuit

230‧‧‧Processing Circuit

Claims (7)

A gate driver includes: a receiving unit configured to receive a first signal and a second signal, wherein the first signal and the second signal are complementary signals; and a set/reset latch type circuit ( The SR latching-type circuit is configured to receive the first signal and the second signal, and reduce the noise of the first signal to generate a processed first signal, where the set/reset latch type circuit includes a first logic circuit for receiving the first signal and the second signal, and generating a set signal and a reset signal; and a latch circuit coupled to the first logic circuit for The set signal and the reset signal are used to generate an output signal. The gate driver of claim 1, wherein the output signal is the first signal after the processing. The gate driver of claim 1, wherein the set/reset latch type circuit further includes: a second logic circuit coupled to the latch circuit for receiving the output signal to generate The first signal after the processing. The gate driver of claim 1, wherein the first logic circuit comprises: a first inverter for receiving the second signal to generate a reverse second signal; a second inverter for receiving the first signal to generate a reverse first signal; a first reverse gate coupled to the first inverter to generate the setting signal; and a second And the gate is coupled to the second inverter to generate the reset signal. The gate driver of claim 4, wherein the latch circuit is a reset/reset latch and a SR NAND latch. The gate driver of claim 1, wherein the first signal and the second signal are from a timing controller on a display panel, and the first signal is a clock signal. The gate driver of claim 6, wherein the display panel is a liquid crystal display panel.