CN106027000B - A kind of hysteresis comparator - Google Patents
A kind of hysteresis comparator Download PDFInfo
- Publication number
- CN106027000B CN106027000B CN201610321791.7A CN201610321791A CN106027000B CN 106027000 B CN106027000 B CN 106027000B CN 201610321791 A CN201610321791 A CN 201610321791A CN 106027000 B CN106027000 B CN 106027000B
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- Prior art keywords
- tube
- pmos tube
- nmos tube
- pmos
- drain electrode
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
Abstract
The invention belongs to Analogous Integrated Electronic Circuits technical fields, are related to a kind of hysteresis comparator.The present invention is compared with traditional hysteresis comparator, mainly by increasing by one and the relevant dynamic current of X point current potentials, when X point voltages increase, the pull-down capability of X points enhances, therefore relative to traditional hysteresis comparator, that above-mentioned situation is improved, the stability of comparator is dynamically enhanced；In addition, the dynamic current can't influence the amount of hysteresis requirement of comparator.Beneficial effects of the present invention are to enhance hysteresis comparator framework by the dynamic of proposition, both ensure that the amount of hysteresis needed for comparator, and also improved the reliability of hysteresis comparator simultaneously.The dynamic enhancing hysteresis comparator is simple for structure, it is easy to accomplish, there is practical value.
Description
Technical field
The invention belongs to Analogous Integrated Electronic Circuits technical fields, are related to a kind of hysteresis comparator.
Background technology
In analogue layout field, hysteresis comparator is extremely important and common module, under normal circumstances
The amount of hysteresis of hysteresis comparator is a definite value, however, when high frequency components occurs in the input signal of hysteresis comparator, it is easy to
Make output false triggering, the ability of anti-dV/dt is limited, and reliability is not strong.
Invention content
It is to be solved by this invention, aiming at the above problem, proposes a kind of dynamic stability enhancing hysteresis comparator, both protected
The amount of hysteresis requirement for having demonstrate,proved comparator, also enhances the Ability of Resisting Disturbance of comparator.
The technical scheme is that：As shown in figure 3, a kind of hysteresis comparator, including the first PMOS tube MP1, second
PMOS tube MP2, third PMOS tube MP3, the 4th PMOS tube MP4, the 5th PMOS tube MP5, the first NMOS tube MN1, the second NMOS tube
MN2, third NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the first phase inverter INV1, the second phase inverter INV2,
Capacitance and current source；The source electrode of first PMOS tube MP1 connects power supply, grid and drain interconnection；The source electrode of second PMOS tube MP2 connects
Power supply, grid connect the drain electrode of the first PMOS tube MP1；The source electrode of third PMOS tube MP3 connects power supply, and grid connects the first PMOS tube
The drain electrode of MP1；The drain electrode of one the first PMOS tube MP1 of termination of current source, other end ground connection；The source electrode of 4th PMOS tube MP4 connects
The drain electrode of second PMOS tube MP2, the grid of the 4th PMOS tube MP4 connect the first input signal；The source electrode of 5th PMOS tube MP5 connects
The drain electrode of two PMOS tube MP2, the grid of the 5th PMOS tube MP5 connect the second input signal；The drain and gate of first NMOS tube MN1
Connect the drain electrode of the 4th PMOS tube MP4, the source electrode ground connection of the first NMOS tube MN1；The source electrode of second NMOS tube MN2 connects the 5th PMOS tube
The drain electrode of MP5, the drain electrode of the 4th PMOS tube MP4 of grounded-grid of the second NMOS tube MN2, the source electrode ground connection of the second NMOS tube MN2；
The drain electrode of third NMOS tube MN3 meets the drain electrode of the 5th PMOS tube MP5, the 4th PMOS tube MP4 of grounded-grid of third NMOS tube MN3
Drain electrode；The drain electrode of 4th NMOS tube MN4 connects the source electrode of third NMOS tube MN3, the source electrode ground connection of the 4th NMOS tube MN4；5th
The drain electrode of NMOS tube MN5 connects the drain electrode of third PMOS tube MP3, and the grid of the 5th NMOS tube MN5 connects the leakage of the 5th PMOS tube MP5
Pole, the source electrode ground connection of the 5th NMOS tube MN5；5th PMOS tube MP5 grids are followed by the 5th PMOS tube MP5 drain electrode, the by capacitance
The tie point of two NMOS tube MN2 drain electrodes, third NMOS tube MN3 drain electrode and the 5th NMOS tube MN5 grids；The MP3 leakages of third PMOS tube
The tie point of pole and the 5th NMOS tube MN5 drain electrodes connects the input terminal of the first phase inverter INV1, the output end of the first phase inverter INV1
Connect the input terminal of the second phase inverter INV2, the grid of the 4th NMOS tube MN4 of output termination of the second phase inverter INV2；Second reverse phase
The tie point of device INV2 output ends and the 4th NMOS tube MN4 grids is output end.
Beneficial effects of the present invention are to enhance hysteresis comparator framework by the dynamic of proposition, both ensure that comparator institute
The amount of hysteresis needed also improves the reliability of hysteresis comparator simultaneously.The dynamic enhancing hysteresis comparator is simple for structure, is easy to real
It is existing, there is practical value.
Description of the drawings
Fig. 1 is traditional hysteresis comparator block diagram；
Fig. 2 is the physical circuit figure of traditional hysteresis comparator；
Fig. 3 is the physical circuit figure of hysteresis comparator of the present invention.
Specific implementation mode
Below in conjunction with the accompanying drawings, detailed description of the present invention technical solution：
When high dither occurs for comparator input signal, it is easy to be coupled in circuit by the parasitic capacitance of input pipe
So as to cause the false triggering of output, the phenomenon to be more easy to happen when disturbing signal dV/dt is bigger.The purpose of the present invention
It exactly prevents from inputting because high dither causes the false triggering of output, enhances the reliability of comparator.Further, since the sluggish ratio of tradition
Amount of hysteresis is built by the method for introducing constant current difference compared with device, the amount of hysteresis of comparator is caused to require to deposit with performance of noiseproof
In mutual restricting relation.Dynamic proposed by the present invention enhances hysteresis comparator, can be moved under the premise of ensureing that amount of hysteresis requires
State realizes the enhancing of comparator performance of noiseproof.
In traditional hysteresis comparator, as shown in Figure 1, when input signal A voltages are less than voltage B, X point voltages are drawn
Low, INV1 overturnings export C high jumps, and transistor MN1 is opened, and increase the drop-down speed of X point voltages by constant current source I, and
At this time if when A voltages have small size shake, because introducing amount of hysteresis, output will not false triggering.However, when input signal exists
When the noise jamming of high frequency, disturbance larger especially dV/dt can be coupled the interference signal by the parasitic capacitance of input pipe
To X points.For example, when disturbing signal there are one rise dV/dt when, if this fixed pull-down capability cannot rapidly by
X points drag down, it is possible to output be made to generate the false triggering signal of high potential.The present invention is relevant with X point current potentials by increasing by one
Dynamic current, when X point voltages increase, the pull-down capability of X points enhances, therefore relative to traditional hysteresis comparator, improves
That above-mentioned situation, dynamically enhances the stability of comparator；In addition, the dynamic current can't influence the sluggishness of comparator
Amount requires.
The physical circuit figure of traditional hysteresis comparator is as shown in Figure 2：
General hysteresis comparator function description：Under normal working point, when the voltage value of input signal B is less than input signal
When A, the electric current of transistor MP4 is less than the electric current of transistor MP5, therefore the electric current of MN2 is less than MP5, and transistor MP5 enters linear
Area, X point voltage highs, output C are low level, and switching tube MN4 is closed.When the voltage value of input signal B is more than input signal A
When, the electric current of transistor MN2 is more than the electric current of MP5, and transistor MN2 enters linear zone, and X point voltage pull-downs export C high jumps, brilliant
Body pipe MN4 is opened, at this time, it may be necessary to which the sum of electric current of the electric current of transistor MP5 more than transistor MN2 and electric current I3 can just make X points
Current potential is drawn high, so input voltage B must drop to an A point voltages amount of hysteresis below, it is thus eliminated that believing in output
The mistake output generated when input signal B shakes near voltage A after number C high jumps.Traditional hysteresis comparator problem description：Tradition
Although hysteresis comparator eliminates false triggering problem caused by the input signal B after exporting C high jumps shakes near voltage A,
But if after output signal C high jumps, if there is the high voltage noise of high frequency in input signal B voltages at this time, the height
Voltage can be coupled to X points by the gate leakage capacitance of input pipe MP5, and in traditional hysteresis comparator, amount of hysteresis often uses constant current source
It is arranged, therefore the pull-down capability of X points is fixed, if the pull-down capability is less than X point rates of voltage rise, therefore common source pipe
MN5 output jumps are low, and output signal C jumps are low, generate and accidentally export.
Traditional hysteresis comparator amount of hysteresis calculates
When B voltages are more than A voltages, after X point voltage pull-downs, C high jumps are exported, switching tube MN4 is opened, when X point voltages
When drawing high again, there is I2=I1+I3(size of transistor MN1 and MN2 is identical)
Wherein I3<ISS, not so X points voltage can not possibly draw high.
I again1+I2=ISS
It releases：
Amount of hysteresis is：
Wherein
Occur high-frequency high-voltage noise coupling in signal B to calculate to tradition hysteresis comparator pull-down capability when X points
Input signal B generates high voltage noise, and tail current ISS all flows through input pipe MP4, at this time if
When, X point voltages can be raised, and generated and accidentally exported.Here the drop-down energy of the circuit at this time is defined
Power (i.e. anti-dV/dt abilities) is
Hysteresis comparator of the present invention is as shown in figure 3, change the constant current source in traditional hysteresis comparator into transistor
MN3, the wherein image ratio of transistor MN1 and MN3 are 1/m.
The calculating of amount of hysteresis of the present invention
I2=I1+mI1
ISS=I1+I2
It releases：
Amount of hysteresis is：
Hysteresis comparator pull-down capability calculating of the present invention when occurring high-frequency high-voltage noise coupling in signal B to X points
Pull-down capability is at this time：
Pass through comparing calculation, it is known that whenWhen, VT1=VT2, but pull-down capability is significantly different at this time, passes
In system hysteresis comparator,And in the hysteresis comparator of the present invention,
M is adjusted here by the image ratio of setting transistor MN3 and MN1, so as to adjust pull-down capability, when m is larger, pulls down energy
Power much enhances.
It, can be not influence DC slow it can be seen that the present invention's is a hysteresis comparator with dynamic stability enhancing
While the design of stagnant amount, and by dynamic pull-down capability limitization so that the hysteresis comparator reliability increases, and relative to
It is sluggish relatively to eliminate the tradition of the output false triggering because caused by being shaken B point voltage high frequencies that following stage makees a delay circuit
Device, the invention circuit structure is simple, and shared chip area is small.
Claims (1)
1. a kind of hysteresis comparator, including the first PMOS tube MP1, the second PMOS tube MP2, third PMOS tube MP3, the 4th PMOS tube
MP4, the 5th PMOS tube MP5, the first NMOS tube MN1, the second NMOS tube MN2, third NMOS tube MN3, the 4th NMOS tube MN4,
Five NMOS tube MN5, the first phase inverter INV1, the second phase inverter INV2, capacitance and current source；The source electrode of first PMOS tube MP1 connects
Power supply, grid and drain interconnection；The source electrode of second PMOS tube MP2 connects power supply, and grid connects the drain electrode of the first PMOS tube MP1；
The source electrode of third PMOS tube MP3 connects power supply, and grid connects the drain electrode of the first PMOS tube MP1；One the first PMOS of termination of current source
The drain electrode of pipe MP1, other end ground connection；The source electrode of 4th PMOS tube MP4 meets the drain electrode of the second PMOS tube MP2, the 4th PMOS tube MP4
Grid connect the first input signal；The source electrode of 5th PMOS tube MP5 connects the drain electrode of the second PMOS tube MP2, the 5th PMOS tube MP5's
Grid connects the second input signal；The drain and gate of first NMOS tube MN1 connects the drain electrode of the 4th PMOS tube MP4, the first NMOS tube
The source electrode of MN1 is grounded；The source electrode of second NMOS tube MN2 connects the drain electrode of the 5th PMOS tube MP5, and the grid of the second NMOS tube MN2 connects
The drain electrode of the 4th PMOS tube MP4 of ground, the source electrode ground connection of the second NMOS tube MN2；The drain electrode of third NMOS tube MN3 connects the 5th PMOS tube
The drain electrode of MP5, the drain electrode of the 4th PMOS tube MP4 of grounded-grid of third NMOS tube MN3；The drain electrode of 4th NMOS tube MN4 connects
The source electrode of three NMOS tube MN3, the source electrode ground connection of the 4th NMOS tube MN4；The drain electrode of 5th NMOS tube MN5 meets third PMOS tube MP3
Drain electrode, the grid of the 5th NMOS tube MN5 connects the drain electrode of the 5th PMOS tube MP5, the source electrode ground connection of the 5th NMOS tube MN5；5th
PMOS tube MP5 grids are followed by the 5th PMOS tube MP5 drain electrodes, the second NMOS tube MN2 drain electrodes, the MN3 leakages of third NMOS tube by capacitance
The tie point of pole and the 5th NMOS tube MN5 grids；Third PMOS tube MP3 drain electrodes and the tie point of the 5th NMOS tube MN5 drain electrodes connect
The input terminal of first phase inverter INV1, the input terminal of the second phase inverter INV2 of output termination of the first phase inverter INV1, second is anti-
The grid of the 4th NMOS tube MN4 of output termination of phase device INV2；Second phase inverter INV2 output ends and the 4th NMOS tube MN4 grids
Tie point be output end；Wherein, the image ratio of the first transistor MN1 and third transistor MN3 are 1/m, and m is third transistor
The mirror image ratio of MN3 and the first transistor MN1, specially：M is bigger, to the 5th PMOS tube MP5 drain electrodes and the second NMOS tube MN2
The pull-down capability of voltage is stronger at drain junction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610321791.7A CN106027000B (en) | 2016-05-16 | 2016-05-16 | A kind of hysteresis comparator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610321791.7A CN106027000B (en) | 2016-05-16 | 2016-05-16 | A kind of hysteresis comparator |
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| Publication Number | Publication Date |
|---|---|
| CN106027000A CN106027000A (en) | 2016-10-12 |
| CN106027000B true CN106027000B (en) | 2018-08-10 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201610321791.7A Expired - Fee Related CN106027000B (en) | 2016-05-16 | 2016-05-16 | A kind of hysteresis comparator |
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Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106533402B (en) * | 2016-12-29 | 2023-03-24 | 厦门亿芯源半导体科技有限公司 | Current comparator with hysteresis function |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6137368A (en) * | 1998-06-23 | 2000-10-24 | Samsung Electronics Co., Ltd. | Frequency synthesizer with constant loop characteristics |
| JP2004135306A (en) * | 2002-07-22 | 2004-04-30 | Texas Instr Deutschland Gmbh | Comparator having hysteresis |
| CN102025352A (en) * | 2010-11-08 | 2011-04-20 | 中国兵器工业集团第二一四研究所苏州研发中心 | Hysteresis voltage comparator |
| CN102594308A (en) * | 2010-11-22 | 2012-07-18 | 快捷半导体(苏州)有限公司 | Reduced temperature dependent hysteretic comparator |
| CN105227161A (en) * | 2014-06-23 | 2016-01-06 | 瑞鼎科技股份有限公司 | Comparator control circuit |
-
2016
- 2016-05-16 CN CN201610321791.7A patent/CN106027000B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6137368A (en) * | 1998-06-23 | 2000-10-24 | Samsung Electronics Co., Ltd. | Frequency synthesizer with constant loop characteristics |
| JP2004135306A (en) * | 2002-07-22 | 2004-04-30 | Texas Instr Deutschland Gmbh | Comparator having hysteresis |
| CN102025352A (en) * | 2010-11-08 | 2011-04-20 | 中国兵器工业集团第二一四研究所苏州研发中心 | Hysteresis voltage comparator |
| CN102594308A (en) * | 2010-11-22 | 2012-07-18 | 快捷半导体(苏州)有限公司 | Reduced temperature dependent hysteretic comparator |
| CN105227161A (en) * | 2014-06-23 | 2016-01-06 | 瑞鼎科技股份有限公司 | Comparator control circuit |
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| CN106027000A (en) | 2016-10-12 |
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