CN208241644U - A kind of transmission gate circuit that high input voltage is isolated - Google Patents
A kind of transmission gate circuit that high input voltage is isolated Download PDFInfo
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- CN208241644U CN208241644U CN201820786372.5U CN201820786372U CN208241644U CN 208241644 U CN208241644 U CN 208241644U CN 201820786372 U CN201820786372 U CN 201820786372U CN 208241644 U CN208241644 U CN 208241644U
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- pmos tube
- transmission gate
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Abstract
The utility model provides a kind of transmission gate circuit of simple, high reliablity the isolation high input voltage of structure, belongs to electronic circuit technology field.Transmission gate circuit includes PMOS tube M3, NMOS tube M4 and pull-up circuit, the input VIN connection of the drain/source and transmission gate circuit of NMOS tube M4；The drain electrode of PMOS tube M3 is connect with the source/drain of NMOS tube M4, while being connect with the output VOUT of transmission gate circuit, the opposite in phase of the grid control signal of PMOS tube M3 and NMOS tube M4；Pull-up circuit is connected in series between input VIN and the source electrode of PMOS tube M3, for when transmission gate circuit is in an off state, making the source voltage of PMOS tube M3 identical as voltage VDD.The utility model joined pull-up circuit, can be with normal turn-off when being in an off state transmission gate circuit, and the high voltage inputted on VIN will not influence the voltage signal on output VOUT by transmission gate.
Description
Technical field
The utility model relates to a kind of transmission gate circuit, in particular to a kind of transmission gate circuit that high input voltage is isolated belongs to
In electronic circuit technology field.
Background technique
In traditional circuit, PMOS tube and NMOS tube can form transmission gate together, as shown in Figure 1.In figure CLK andFor the opposite signal of voltage, i.e., when CLK is high voltage,For low-voltage, vice versa.When CLK is low-voltage, pass
Defeated door conducting；When CLK is high voltage, transmission gate is disconnected.The high voltage of CLK is generally equivalent to the supply voltage of chip, such as
5V。
In actual application, often there is the phenomenon that input VIN high pressure, such as 8V, transmission gate traditional at this time can not
Realize break function.Because being disconnected after the voltage inputted on VIN is higher than PMOS tube voltage threshold voltage even if transmission gate is in
State, but PMOS tube therein is closed constantly, and VIN still can influence the value of output VOUT by transmission gate.Transmission gate at this time
Just lose the effect of the pass as switch.
In view of the above technical problems, the solution of prior art routine be the voltage threshold of PMOS tube is increased so that
The voltage value inputted on VIN is not higher than the voltage of PMOS tube voltage threshold.In this way when transmission gate is in an off state, transmission gate
Can be with normal turn-off, the high voltage inputted on VIN will not influence the voltage signal on output VOUT by transmission gate.But it should
There are still limitations for method: the voltage threshold for raising PMOS tube can make the complexity of circuit increase, not only will increase circuit at
This, and the reliability for also resulting in circuit reduces.
Utility model content
In view of the above problems, the utility model provides a kind of transmission gate circuit that high input voltage can be isolated.
A kind of transmission gate circuit of isolation high input voltage of the utility model, the transmission gate circuit include PMOS tube M3
With NMOS tube M4, the input VIN connection of the drain/source and transmission gate circuit of NMOS tube M4；The drain electrode of PMOS tube M3 and NMOS
The source/drain of pipe M4 connects, while connecting with the output VOUT of transmission gate circuit, the grid control of PMOS tube M3 and NMOS tube M4
Signal phase processed is opposite；
The transmission gate circuit further includes pull-up circuit, and the pull-up circuit is connected in series in input VIN and PMOS tube M3
Source electrode between, for when transmission gate circuit is in an off state, making the source voltage of PMOS tube M3 identical as voltage VDD.
Preferably, the pull-up circuit includes PMOS tube M1 and PMOS tube M2；
The source electrode of PMOS tube M1 connects voltage VDD, drain electrode and the source electrode of PMOS tube M2, the source of PMOS tube M3 of PMOS tube M1
Pole connects simultaneously, the drain electrode of PMOS tube M2 and the input VIN connection of transmission gate circuit, the grid of the PMOS tube M1 and NMOS tube M4
The phase that pole controls signal is identical, and the PMOS tube M2 is identical as the phase of the grid control signal of PMOS tube M3.
Preferably, a1/a2> 2.5, a1Indicate the channel width of PMOS tube M1 and the ratio of length, a2Indicate PMOS tube
The channel width of M2 and the ratio of length.
Preferably, the input VIN voltage is less than 10V, it is further preferred that the input VIN voltage is 5-8V.
The beneficial effects of the utility model are that the utility model joined pull-up circuit, make the transmission of the utility model
When gate circuit is in an off state, transmission gate circuit can be with normal turn-off, and the high voltage inputted on VIN will not pass through transmission gate shadow
It rings to the voltage signal on output VOUT, so the improved transmission gate circuit of the utility model is pressed with well the height of input
Barrier properties, reliability increases, and the utility model structure is simple, at low cost.
Detailed description of the invention
Fig. 1 is the electronic schematic diagram of existing transmission gate circuit；
Fig. 2 is the electronic schematic diagram of the transmission gate circuit of specific embodiment of the present invention；
Fig. 3 is the equivalent circuit of Fig. 2；
Fig. 4 is that high input voltage VIN emulation experiment is isolated in existing transmission gate circuit；
Fig. 5 is that high input voltage VIN emulation experiment is isolated in the transmission gate circuit of the utility model.
Specific embodiment
The following will be combined with the drawings in the embodiments of the present invention, carries out the technical scheme in the embodiment of the utility model
Clearly and completely describe, it is clear that the described embodiments are only a part of the embodiments of the utility model, rather than whole
Embodiment.Based on the embodiments of the present invention, those of ordinary skill in the art are in the premise for not making creative work
Under every other embodiment obtained, fall within the protection scope of the utility model.
It should be noted that in the absence of conflict, the feature in the embodiments of the present invention and embodiment can
To be combined with each other.
The utility model is described in further detail in the following with reference to the drawings and specific embodiments, but not as the utility model
It limits.
The transmission gate circuit of the isolation high input voltage of present embodiment, as shown in Fig. 2, including PMOS tube M3, NMOS tube M4
And pull-up circuit, the input VIN connection of the drain/source and transmission gate circuit of NMOS tube M4；The drain electrode of PMOS tube M3 and NMOS
The source/drain of pipe M4 connects, while connecting with the output VOUT of transmission gate circuit, the grid control of PMOS tube M3 and NMOS tube M4
Signal phase processed is opposite；
Pull-up circuit is connected in series between input VIN and the source electrode of PMOS tube M3, and effect is: even if input VIN is
Voltage higher than VDD, for when transmission gate circuit is in an off state, making the source voltage and voltage VDD phase of PMOS tube M3
Together.Present embodiment is pressed with good barrier properties to the height of input, and reliability increases；
In preferred embodiment, the pull-up circuit of present embodiment includes PMOS tube M1 and PMOS tube M2；
The source electrode of PMOS tube M1 meets voltage VDD, and the drain electrode of PMOS tube M1 is connect simultaneously with the source electrode of PMOS tube M2, M3, institute
State that PMOS tube M1 is identical as the phase of the grid control signal of NMOS tube M4, the grid of the PMOS tube M2 and PMOS tube M3 control
The phase of signal is identical.
The working principle of present embodiment are as follows: all PMOS tube work in vdd voltage threshold, for example VDD is 5V, works as transmission
When gate circuit is in an off state, the PMOS tube M1 in pull-up circuit is connected, and has very strong pull-up ability, remaining metal-oxide-semiconductor is equal
It is in close state.When input VIN is high voltage, such as 8V, when being more than vdd voltage, the PMOS tube M2 in pull-up circuit is in
Weak on state, PMOS tube M1 and PMOS tube M2 work together, so that A point current potential is close to VDD, then M3 is equivalent to closing at this time
State, influence very little of the A point to VOUT, and then influence very little of the VIN to VOUT is inputted, it can be ignored.
In order to make PMOS tube M1 have very strong pull-up ability and A point current potential close to VDD, the ruler of PMOS tube M1 is designed at this time
Very little W/L is very big, has very strong pull-up ability, and the driving capability of PMOS tube M2 is weaker, in preferred embodiment, when VDD is 5V,
A can be enabled1/a2> 2.5, a1Indicate the channel width of PMOS tube M1 and the ratio of length, a2Indicate the channel width of PMOS tube M2
With the ratio of length.
Principle at this time can be with equivalent as shown in Figure 3.PMOS tube M1 and PMOS tube M2 are equivalent to resistance R1 and resistance respectively
R2, then the voltage of A point beBecause the driving capability of PMOS tube M1 is much larger than
PMOS tube M2 is equivalent to resistance R2 much larger than resistance R1, then VA is approximately equal to VDD, so PMOS tube M3 at this time is in A point and defeated
Disconnection is equivalent between VOUT out, A point does not almost influence output VOUT.
In the following, further describing the performance of the transmission gate circuit of the isolation high input voltage of the present embodiment.
Simulated experiment is carried out using the transmission gate circuit of the isolation high input voltage of the utility model, in the defeated of transmission gate circuit
VOUT terminates the voltage of very weak 2.5V or so out, is highly susceptible to interfere and change, and test input voltage VIN is 5-
When 8V, VDD are 5V, output voltage after transmission gate disconnection by input voltage interfere as a result, as shown in Figure 4 and Figure 5, in figure
Abscissa is the voltage that transmission gate inputs VIN, and ordinate is the voltage that transmission gate circuit exports VOUT.The voltage of cmos circuit
Threshold value is 5V, it can be seen that the improved transmission gate circuit of present embodiment is pressed with very well the height of input from Fig. 4 and Fig. 5
Barrier properties, achieved the purpose that circuits improvement.
Although describing the utility model herein with reference to specific embodiment, it should be understood that, this
A little embodiments are only the example of the principles of the present invention and application.It should therefore be understood that can be to illustrative reality
It applies example and carries out many modifications, and can be designed that other arrangements, without departing from this reality as defined in the appended claims
With novel spirit and scope.It should be understood that can be combined by being different from mode described in original claim
Different dependent claims and feature described herein.It will also be appreciated that combining spy described in separate embodiments
Sign can be used in other embodiments.
Claims (4)
1. a kind of transmission gate circuit that high input voltage is isolated, the transmission gate circuit includes PMOS tube M3 and NMOS tube M4, NMOS
The input VIN connection of the drain/source and transmission gate circuit of pipe M4；The drain electrode of PMOS tube M3 and the source/drain of NMOS tube M4
Connection, while being connect with the output VOUT of transmission gate circuit, the phase phase of the grid control signal of PMOS tube M3 and NMOS tube M4
Instead；
It is characterized in that, the transmission gate circuit further includes pull-up circuit, the pull-up circuit be connected in series in input VIN with
Between the source electrode of PMOS tube M3, for when transmission gate circuit is in an off state, making the source voltage and voltage of PMOS tube M3
VDD is identical.
2. the transmission gate circuit of isolation high input voltage according to claim 1, which is characterized in that the pull-up circuit includes
PMOS tube M1 and PMOS tube M2；
The source electrode of PMOS tube M1 meets voltage VDD, the source electrode of the drain electrode of PMOS tube M1 and PMOS tube M2, PMOS tube M3 source electrode simultaneously
The grid of connection, the drain electrode of PMOS tube M2 and the input VIN connection of transmission gate circuit, the PMOS tube M1 and NMOS tube M4 control
The phase of signal is identical, and the PMOS tube M2 is identical as the phase of the grid control signal of PMOS tube M3.
3. the transmission gate circuit of isolation high input voltage according to claim 2, which is characterized in that a1/a2> 2.5, a1It indicates
The channel width of PMOS tube M1 and the ratio of length, a2Indicate the channel width of PMOS tube M2 and the ratio of length.
4. the transmission gate circuit of isolation high input voltage according to claim 3, which is characterized in that the input VIN voltage
Less than 10V.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820786372.5U CN208241644U (en) | 2018-05-24 | 2018-05-24 | A kind of transmission gate circuit that high input voltage is isolated |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820786372.5U CN208241644U (en) | 2018-05-24 | 2018-05-24 | A kind of transmission gate circuit that high input voltage is isolated |
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| Publication Number | Publication Date |
|---|---|
| CN208241644U true CN208241644U (en) | 2018-12-14 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201820786372.5U Active CN208241644U (en) | 2018-05-24 | 2018-05-24 | A kind of transmission gate circuit that high input voltage is isolated |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108809285A (en) * | 2018-05-24 | 2018-11-13 | 上海芯圣电子股份有限公司 | A kind of transmission gate circuit of isolation high input voltage |
-
2018
- 2018-05-24 CN CN201820786372.5U patent/CN208241644U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108809285A (en) * | 2018-05-24 | 2018-11-13 | 上海芯圣电子股份有限公司 | A kind of transmission gate circuit of isolation high input voltage |
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