CN105515560A - Voltage conversion circuit - Google Patents
Voltage conversion circuit Download PDFInfo
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- CN105515560A CN105515560A CN201610056353.2A CN201610056353A CN105515560A CN 105515560 A CN105515560 A CN 105515560A CN 201610056353 A CN201610056353 A CN 201610056353A CN 105515560 A CN105515560 A CN 105515560A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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Abstract
The invention provides a voltage conversion circuit. The voltage conversion circuit comprises a voltage converter and a latch circuit. The voltage converter comprises a first inverter, a second inverter, a first metal oxide semiconductor (MOS) pipe, a second MOS pipe, a third MOS pipe and a fourth MOS pipe. The conversion of signals from a first voltage domain to a second voltage domain can be achieved by the voltage converter, a first interface of the latch circuit is connected with a first output node, and a second interface of the latch circuit is connected with a second output node. When a first voltage source is switched off, the voltage of the first output node and the voltage of the second output node are latched by the latch circuit at the voltage value before the first voltage source is switched off. Compared with the prior art, the latch circuit is added on the basis of the existing voltage converter, when the voltage source of the first voltage domain is closed, the voltage of the output node is latched by the latch circuit at the voltage value before the first voltage domain is closed, and thus the goal of avoiding circuit electric leakage of the second voltage domain and determining the output signals is achieved.
Description
[technical field]
The present invention relates to technical field of circuit design, particularly the anti-creeping voltage conversion circuit of one.
[background technology]
Integrated circuit comprises the circuit of two runnings at different voltage domain sometimes; such as; the voltage domain VDDL of core (core) part when operating of integrated circuit usually can lower than the voltage domain VDDH of I/O (I/O) circuit; to reduce power consumption; and therefore can use less transistor, thus reduce the area of whole chips.Therefore, integrated circuit often utilizes electric pressure converter to adjust the voltage thresholding of input signal, and output signal is normally worked in another higher or lower voltage domain circuit.
Please refer to shown in Fig. 1, it is the circuit diagram of traditional a kind of electric pressure converter, electric pressure converter shown in Fig. 1 comprises PMOS transistor MP1 and MP2, nmos pass transistor MN1 and MN2, inverter INV1 and INV2, wherein, INV1 is the inverter of VDDL voltage domain, and INV2 is the inverter of VDDH voltage domain.When after the input signal IN that circuit receives from core, a signal INB reverse with input signal IN can be produced by inverter INV1, then signal IN and signal INB is input to respectively the grid of nmos pass transistor MN2 and MN1.As input signal IN=VDDL, the signal INB=0 obtained by inverter INV1, thus make nmos pass transistor MN2 conducting, MN1 ends, as long as the conducting resistance of nmos pass transistor MN2 is less than the conducting resistance of PMOS transistor MP2 to a certain degree, just the voltage of OUTB node can be pulled down to enough low, make PMOS transistor MP1 conducting, PMOS transistor MP1 can move the voltage of OUTBB node to again and equal VDDH, thus PMOS transistor MP2 is ended, the voltage of OUTB node will be moved to ground by nmos pass transistor MN2, and be the output signal OUT of VDDH by output voltage after inverter INV2.
Like this, the electric pressure converter shown in Fig. 1 just achieves the conversion of signal IN from low-voltage threshold VDDL to high voltage threshold VDDH.We are in order to reach the object of power saving, and often the power vd DL of core part can be turned off, the power vd DH of I/O part retains, but, after power vd DL is switched off, there will be the circuit electric leakage of VDDH territory and the uncertain problem of output signal OUT.
Therefore, be necessary to provide a kind of technical scheme of improvement to solve the problems referred to above.
[summary of the invention]
The object of the present invention is to provide a kind of voltage conversion circuit, it not only can realize signal from the first voltage domain to the conversion of the second voltage domain, and when the voltage source of the first voltage domain is closed, the second voltage domain circuit electric leakage can be avoided, and output signal can be determined.
In order to solve the problem, the invention provides a kind of voltage conversion circuit, it comprises electric pressure converter and latch cicuit.Described electric pressure converter comprises the first inverter, the second inverter, the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, wherein, the input of the first inverter is connected with the input of electric pressure converter, the output of the first inverter is connected with the grid of the 3rd metal-oxide-semiconductor, and the power end of the first inverter is connected with the first voltage source; The source ground of the 3rd metal-oxide-semiconductor, its drain electrode is connected with the drain electrode of the first metal-oxide-semiconductor, and the source electrode of the first metal-oxide-semiconductor is connected with the second voltage source; The source electrode of the second metal-oxide-semiconductor is connected with the second voltage source, and its drain electrode is connected with the drain electrode of the 4th metal-oxide-semiconductor, the source ground of the 4th metal-oxide-semiconductor, and the grid of the 4th metal-oxide-semiconductor is connected with the input of electric pressure converter; Connected node between first metal-oxide-semiconductor and the 3rd metal-oxide-semiconductor is the first output node, and the connected node between the second metal-oxide-semiconductor and the 4th metal-oxide-semiconductor is the second output node; The grid of the first metal-oxide-semiconductor is connected with the second output node, and the grid of the second metal-oxide-semiconductor is connected with the first output node; The input of the second inverter is connected with the second output node, and the output of the second inverter is connected with the output of electric pressure converter, and the power end of the second inverter is connected with the second voltage source.The first interface of described latch cicuit is connected with the first output node, its second interface is connected with the second output node, when the first voltage source is closed, described latch cicuit is respectively by the magnitude of voltage of the voltage latch of the first output node and the second output node before the first voltage source is closed.
Further, described latch cicuit comprises the 5th metal-oxide-semiconductor and the 6th metal-oxide-semiconductor, and the first link of the 5th metal-oxide-semiconductor is connected with the first interface of described latch cicuit, and its control end is connected with the second interface of described latch cicuit, its second link ground connection; First link of the 6th metal-oxide-semiconductor is connected with the second interface of described latch cicuit, and its control end is connected with the first interface of described latch cicuit, its second link ground connection.
Further, described 5th metal-oxide-semiconductor and the 6th metal-oxide-semiconductor are nmos pass transistor, and the first link of the 5th metal-oxide-semiconductor, control end and the second link are respectively drain electrode, grid and source electrode; First link of the 6th metal-oxide-semiconductor, control end and the second link are respectively drain electrode, grid and source electrode.
Further, all power-up state is at stage 1: the first voltage source and the second voltage source, as the signal IN=VDDL that the input of electric pressure converter receives, 4th metal-oxide-semiconductor conducting, the 3rd metal-oxide-semiconductor cut-off, the first metal-oxide-semiconductor conducting, the second metal-oxide-semiconductor cut-off, the output signal OUT=VDDH of the output of electric pressure converter, and the 6th metal-oxide-semiconductor conducting, the 5th metal-oxide-semiconductor cut-off; Electricity under stage 2: the first voltage source, the second voltage source maintains power-up state, under the first voltage source after electricity, 3rd metal-oxide-semiconductor cut-off, the 4th metal-oxide-semiconductor cut-off, now due to the 6th metal-oxide-semiconductor conducting, the 5th metal-oxide-semiconductor cut-off, first metal-oxide-semiconductor conducting, second metal-oxide-semiconductor cut-off, therefore, maintains the voltage stabilization of the first output node on VDDH current potential, the voltage stabilization of the second output node is maintained on 0 current potential, wherein, VDDL is the magnitude of voltage of the first voltage source, and VDDH is the magnitude of voltage of the second voltage source.
Further, the magnitude of voltage of described first voltage source is less than the magnitude of voltage of the second voltage source.
Further, the conducting resistance of described 4th metal-oxide-semiconductor is less than the conducting resistance of the second metal-oxide-semiconductor.
Further, the first metal-oxide-semiconductor and the second metal-oxide-semiconductor are PMOS transistor; 3rd metal-oxide-semiconductor and the 4th metal-oxide-semiconductor are nmos pass transistor.
Compared with prior art, the present invention has additional latch cicuit on the basis of existing electric pressure converter, when the voltage source of the first voltage domain closes (namely the voltage source of input signal is closed), this latch cicuit is by the magnitude of voltage of the voltage latch of output node before the first voltage domain is closed, thus reach avoid second voltage domain circuit electric leakage, determine output signal object.
[accompanying drawing explanation]
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.Wherein:
Fig. 1 its be the circuit diagram of traditional a kind of electric pressure converter;
Fig. 2 is the circuit diagram of the present invention's voltage conversion circuit in one embodiment.
[embodiment]
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, and below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
Alleged herein " embodiment " or " embodiment " refers to special characteristic, structure or the characteristic that can be contained at least one implementation of the present invention.Different local in this manual " in one embodiment " occurred not all refers to same embodiment, neither be independent or optionally mutually exclusive with other embodiments embodiment.Unless stated otherwise, connection herein, be connected, word that the expression that connects is electrically connected all represents and is directly or indirectly electrical connected.
For the technical problem that conventional voltage transducer in above-mentioned background technology exists, inventor traces it to its cause learn by going deep into spy: after the voltage source V DDL producing input signal IN closes, grid voltage IN and INB of nmos pass transistor MN1 and MN2 can be down to below the threshold voltage vt of nmos pass transistor, nmos pass transistor MN1 and MN2 is ended, now, OUTB node is in suspension joint (float) state, because only a node (OUTBB node or OUTB node) can only be pulled to VDDH by PMOS transistor MP1 and MP2, another one node is because the leakage path lacked over the ground is parked near VDDH/2, make the PMOS transistor in inverter INV2 and nmos pass transistor conducting simultaneously, thus cause the leaky of inverter INV2.In addition, because the voltage of now output OUT is uncertain, the mistake of rear class can likely be caused.
In view of above-mentioned analysis, inventor improves traditional electric pressure converter.Please refer to shown in Fig. 2, it is the circuit diagram of the present invention's voltage conversion circuit in one embodiment, and the voltage conversion circuit shown in Fig. 2 comprises electric pressure converter 210 and latches (Latch) circuit 220.
Described electric pressure converter 210 comprises the first inverter INV1, the second inverter INV2, the first metal-oxide-semiconductor MP1, the second metal-oxide-semiconductor MP2, the 3rd metal-oxide-semiconductor MN1, the 4th metal-oxide-semiconductor MN2, wherein, the input of the first inverter INV1 is connected with the input IN of electric pressure converter 210, the output of the first inverter INV1 is connected with the grid of the 3rd metal-oxide-semiconductor MN1, and the power end of the first inverter INV1 is connected with the first voltage source V DDL; The source ground of the 3rd metal-oxide-semiconductor MN1, its drain electrode is connected with the drain electrode of the first metal-oxide-semiconductor MP1, and the source electrode of the first metal-oxide-semiconductor MP1 is connected with the second voltage source V DDH; The source electrode of the second metal-oxide-semiconductor MP2 is connected with the second voltage source V DDH, and its drain electrode is connected with the drain electrode of the 4th metal-oxide-semiconductor MN2, the source ground of the 4th metal-oxide-semiconductor MN2, and the grid of the 4th metal-oxide-semiconductor MN2 is connected with the input IN of electric pressure converter 210; Connected node OUTBB between first metal-oxide-semiconductor MP1 and the 3rd metal-oxide-semiconductor MN1 is the first output node, and the connected node OUTB between the second metal-oxide-semiconductor MP2 and the 4th metal-oxide-semiconductor MN2 is the second output node; The grid of the first metal-oxide-semiconductor MP1 is connected with the second output node OUTB, and the grid of the second metal-oxide-semiconductor MP2 is connected with the first output node OUTBB; The input of the second inverter INV2 is connected with the second output node OUTB, and the output of the second inverter INV2 is connected with the output OUT of electric pressure converter, and the power end of the second inverter INV2 is connected with the second voltage source V DDH.
The first interface 1 of described latch cicuit 220 is connected with the first output node OUTBB, its second interface 2 is connected with the second output node OUTB, the effect of this latch cicuit 220 is, when the first voltage source V DDL closes, respectively by the magnitude of voltage of the voltage latch of the first output node OUTBB and the second output node OUTB before the first voltage source V DDL closes, thus reach and avoid the second voltage source V DDH circuit (or second voltage domain circuit) to leak electricity, determine the object outputing signal OUT.
In the embodiment shown in Figure 2, described latch cicuit 220 comprises the 5th metal-oxide-semiconductor MN3 and the 6th metal-oxide-semiconductor MN4, wherein, first link of the 5th metal-oxide-semiconductor MN3 is connected with the first interface 1 of described latch cicuit 220, its control end is connected with the second interface 2 of described latch cicuit 220, its second link ground connection; First link of the 6th metal-oxide-semiconductor MN4 is connected with the second interface 2 of described latch cicuit 220, and its control end is connected with the first interface 1 of described latch cicuit 220, its second link ground connection.
In the embodiment shown in Figure 2, the first metal-oxide-semiconductor MP1 and the second metal-oxide-semiconductor MP2 is PMOS transistor; 3rd metal-oxide-semiconductor MN1 and the 4th metal-oxide-semiconductor MN2 is nmos pass transistor; Described 5th metal-oxide-semiconductor MN3 and the 6th metal-oxide-semiconductor MN4 is nmos pass transistor, first link of the 5th metal-oxide-semiconductor MN3, control end and the second link are respectively drain electrode, grid and source electrode, and first link of the 6th metal-oxide-semiconductor MN4, control end and the second link are respectively drain electrode, grid and source electrode.
For the ease of understanding the present invention, the latch cicuit 220 specifically introduced below in Fig. 2 how to realize aforementioned latch function.
Stage 1: the first voltage source V DDL and the second voltage source V DDH is in power-up state.
As the signal IN=VDDL that the input of electric pressure converter 210 receives, the signal INB=0 exported by inverter INV1, thus make the 4th metal-oxide-semiconductor MN2 conducting, 3rd metal-oxide-semiconductor MN1 ends, as long as the conducting resistance of the 4th metal-oxide-semiconductor MN2 is less than the conducting resistance of the second metal-oxide-semiconductor MP2 to a certain degree, just the voltage of the second output node OUTB can be moved to an enough low voltage, make the first metal-oxide-semiconductor MP1 conducting, first metal-oxide-semiconductor MP1 can move VDDH to the voltage of the first output node OUTBB again, thus the second metal-oxide-semiconductor MP2 is ended, second output node OUTB will be moved to ground by the 4th metal-oxide-semiconductor MN2, and be the output signal OUT of VDDH by output voltage after the second inverter INV2, now, OUTBB=VDDH, OUTB=0, 6th metal-oxide-semiconductor MN4 conducting, 5th metal-oxide-semiconductor MN3 ends, wherein, OUTBB is the magnitude of voltage of the first output node OUTBB, OUTB is the magnitude of voltage of the second output node OUTB, VDDL is the magnitude of voltage (it can be described as the first voltage domain) of the first voltage source V DDL, VDDH is the magnitude of voltage (it can be described as the second voltage domain) of the second voltage source V DDH.
Electricity under stage 2: the first voltage source V DDL, the second voltage source V DDH maintains power-up state.
Under first voltage source V DDL after electricity, signal IN and signal INB will be down to below nmos pass transistor threshold voltage vt, 3rd metal-oxide-semiconductor MN1 and the 4th metal-oxide-semiconductor MN2 is all ended, now because the 6th metal-oxide-semiconductor MN4 conducting, 5th metal-oxide-semiconductor MN3 ends, first metal-oxide-semiconductor MP1 conducting, second metal-oxide-semiconductor MP2 ends, so just can the voltage stabilization of the first output node OUTBB be maintained on VDDH current potential, the value of the current potential voltage stabilization of the second output node OUTB being maintained now the first output node OUTBB and the second output node OUTB on 0 current potential just under the first voltage source V DDL before electricity, and because the first output node OUTBB and the second output node OUTB is not in float state, so also can not electric leakage be there is in the second inverter INV2, and maintain 0 current potential due to the voltage stabilization of now the second output node OUTB, therefore, output signal OUT determines on VDDH current potential.
It should be noted that, in the embodiment shown in Fig. 2, the magnitude of voltage of described first voltage source V DDL is less than the magnitude of voltage of the second voltage source V DDH,
It should be noted that, in other embodiments, also the latch cicuit of other structures of the prior art can be adopted, as long as when the first voltage source V DDL closes, it can respectively by the magnitude of voltage of the voltage latch of the first output node OUTBB and the second output node OUTB before the first voltage source V DDL closes.
In sum, the present invention sets up latch cicuit on the basis of conventional voltage transducer, when the voltage source of the first voltage domain VDDL is closed, this latch cicuit is respectively by the magnitude of voltage of the voltage latch of the first output node OUTBB and the second output node OUTB before the first voltage domain VDDL closes, thus reach avoid second voltage domain VDDH circuit electric leakage, determine output signal object.
In the present invention, " connection ", be connected, word that " companys ", the expression such as " connecing " are electrical connected, if no special instructions, then represent direct or indirect electric connection.
It is pointed out that the scope be familiar with person skilled in art and any change that the specific embodiment of the present invention is done all do not departed to claims of the present invention.Correspondingly, the scope of claim of the present invention is also not limited only to previous embodiment.
Claims (7)
1. a voltage conversion circuit, is characterized in that, it comprises electric pressure converter and latch cicuit,
Described electric pressure converter comprises the first inverter, the second inverter, the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, wherein, the input of the first inverter is connected with the input of electric pressure converter, the output of the first inverter is connected with the grid of the 3rd metal-oxide-semiconductor, and the power end of the first inverter is connected with the first voltage source; The source ground of the 3rd metal-oxide-semiconductor, its drain electrode is connected with the drain electrode of the first metal-oxide-semiconductor, and the source electrode of the first metal-oxide-semiconductor is connected with the second voltage source; The source electrode of the second metal-oxide-semiconductor is connected with the second voltage source, and its drain electrode is connected with the drain electrode of the 4th metal-oxide-semiconductor, the source ground of the 4th metal-oxide-semiconductor, and the grid of the 4th metal-oxide-semiconductor is connected with the input of electric pressure converter; Connected node between first metal-oxide-semiconductor and the 3rd metal-oxide-semiconductor is the first output node, and the connected node between the second metal-oxide-semiconductor and the 4th metal-oxide-semiconductor is the second output node; The grid of the first metal-oxide-semiconductor is connected with the second output node, and the grid of the second metal-oxide-semiconductor is connected with the first output node; The input of the second inverter is connected with the second output node, and the output of the second inverter is connected with the output of electric pressure converter, and the power end of the second inverter is connected with the second voltage source,
The first interface of described latch cicuit is connected with the first output node, its second interface is connected with the second output node, when the first voltage source is closed, described latch cicuit is respectively by the magnitude of voltage of the voltage latch of the first output node and the second output node before the first voltage source is closed.
2. voltage conversion circuit according to claim 1, it is characterized in that, described latch cicuit comprises the 5th metal-oxide-semiconductor and the 6th metal-oxide-semiconductor, first link of the 5th metal-oxide-semiconductor is connected with the first interface of described latch cicuit, its control end is connected with the second interface of described latch cicuit, its second link ground connection; First link of the 6th metal-oxide-semiconductor is connected with the second interface of described latch cicuit, and its control end is connected with the first interface of described latch cicuit, its second link ground connection.
3. voltage conversion circuit according to claim 2, is characterized in that,
Described 5th metal-oxide-semiconductor and the 6th metal-oxide-semiconductor are nmos pass transistor,
First link of the 5th metal-oxide-semiconductor, control end and the second link are respectively drain electrode, grid and source electrode; First link of the 6th metal-oxide-semiconductor, control end and the second link are respectively drain electrode, grid and source electrode.
4. voltage conversion circuit according to claim 2, is characterized in that,
All power-up state is at stage 1: the first voltage source and the second voltage source,
As the signal IN=VDDL that the input of electric pressure converter receives, 4th metal-oxide-semiconductor conducting, the 3rd metal-oxide-semiconductor cut-off, the first metal-oxide-semiconductor conducting, the second metal-oxide-semiconductor cut-off, the output signal OUT=VDDH of the output of electric pressure converter, and the 6th metal-oxide-semiconductor conducting, the 5th metal-oxide-semiconductor cut-off;
Electricity under stage 2: the first voltage source, the second voltage source maintains power-up state,
Under first voltage source after electricity, 3rd metal-oxide-semiconductor cut-off, the 4th metal-oxide-semiconductor cut-off, now due to the 6th metal-oxide-semiconductor conducting, 5th metal-oxide-semiconductor cut-off, the first metal-oxide-semiconductor conducting, the second metal-oxide-semiconductor cut-off, therefore, the voltage stabilization of the first output node is maintained on VDDH current potential, the voltage stabilization of the second output node is maintained on 0 current potential
Wherein, VDDL is the magnitude of voltage of the first voltage source, and VDDH is the magnitude of voltage of the second voltage source.
5. voltage conversion circuit according to claim 1, is characterized in that,
The magnitude of voltage of described first voltage source is less than the magnitude of voltage of the second voltage source.
6. voltage conversion circuit according to claim 1, is characterized in that,
The conducting resistance of described 4th metal-oxide-semiconductor is less than the conducting resistance of the second metal-oxide-semiconductor.
7. voltage conversion circuit according to claim 1, is characterized in that,
First metal-oxide-semiconductor and the second metal-oxide-semiconductor are PMOS transistor;
3rd metal-oxide-semiconductor and the 4th metal-oxide-semiconductor are nmos pass transistor.
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| CN201610056353.2A CN105515560A (en) | 2016-01-27 | 2016-01-27 | Voltage conversion circuit |
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| CN201610056353.2A CN105515560A (en) | 2016-01-27 | 2016-01-27 | Voltage conversion circuit |
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| CN108206689A (en) * | 2016-12-19 | 2018-06-26 | 上海安其威微电子科技有限公司 | Level conversion driving circuit |
| CN108322210A (en) * | 2017-01-16 | 2018-07-24 | 中芯国际集成电路制造(上海)有限公司 | A kind of level shifting circuit |
| CN109743055A (en) * | 2019-01-09 | 2019-05-10 | 上海艾为电子技术股份有限公司 | A kind of binary channels multiplexing level shifting circuit |
| CN110048708A (en) * | 2018-01-16 | 2019-07-23 | 中芯国际集成电路制造(北京)有限公司 | Level displacement shifter, integrated circuit and method |
| CN110581648A (en) * | 2018-06-11 | 2019-12-17 | 半导体组件工业公司 | Voltage converter circuit and system for voltage conversion |
| CN114629489A (en) * | 2022-03-29 | 2022-06-14 | 北京紫光芯能科技有限公司 | Level conversion circuit and electronic equipment with multiple voltage domains |
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| CN108206689A (en) * | 2016-12-19 | 2018-06-26 | 上海安其威微电子科技有限公司 | Level conversion driving circuit |
| CN108206689B (en) * | 2016-12-19 | 2024-02-23 | 上海安其威微电子科技有限公司 | Level shift driving circuit |
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| CN110581648B (en) * | 2018-06-11 | 2024-07-19 | 半导体组件工业公司 | Voltage converter circuit and system for voltage conversion |
| CN109743055A (en) * | 2019-01-09 | 2019-05-10 | 上海艾为电子技术股份有限公司 | A kind of binary channels multiplexing level shifting circuit |
| CN109743055B (en) * | 2019-01-09 | 2023-05-09 | 上海艾为电子技术股份有限公司 | Dual-channel multiplexing level conversion circuit |
| CN114629489A (en) * | 2022-03-29 | 2022-06-14 | 北京紫光芯能科技有限公司 | Level conversion circuit and electronic equipment with multiple voltage domains |
| CN114629489B (en) * | 2022-03-29 | 2024-05-14 | 北京紫光芯能科技有限公司 | Level conversion circuit and electronic equipment with multiple voltage domains |
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Application publication date: 20160420 |
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