CN207612250U - A kind of latch and isolation circuit - Google Patents
A kind of latch and isolation circuit Download PDFInfo
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- CN207612250U CN207612250U CN201820040682.2U CN201820040682U CN207612250U CN 207612250 U CN207612250 U CN 207612250U CN 201820040682 U CN201820040682 U CN 201820040682U CN 207612250 U CN207612250 U CN 207612250U
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Abstract
A kind of latch and isolation circuit, latch include the first order and k second level minor structure；In first order minor structure, the first and second load first ends connect first port, and the first driving circuit connects the first load second end and second port respectively, and the second driving circuit connects the second load second end and second port respectively；In i-th of second level minor structure, third load first end connects the i-th 1 second level minor structures the 4th and loads second end, third load regulation two terminates third driving circuit control terminal, the i-th 1 second level minor structure third driving circuit first ends and the 4th driving circuit first ends, 4th load first end connects the i-th 1 second level minor structure third load second ends, the 4th driving circuit control end of the 4th load regulation two termination, the i-th 1 the 4th driving circuit first ends of second level minor structure and third driving circuit first ends；1 ＜ i≤k.Latch overturning amplitude can be reduced using the above scheme.
Description
Technical field
The utility model is related to electronic circuit technology field, more particularly to a kind of latch and isolation circuit.
Background technology
Latch (Latch) is a kind of memory device to level-sensitive, and major function is the logic to input signal
Level is latched, so that it maintains certain level state (such as logical zero or logical one) and keeps stable.Latch
It is widely used in many circuits such as isolation circuit, storage circuit.
A kind of relatively conventional latch structure of latch based on double inverter structures；Wherein, two phase inverter head and the tail
It is connected, each phase inverter is by a P type metal oxide semiconductor field-effect transistor (Metal-Oxide-Semiconductor
Field-Effect Transistor, abbreviation MOSFET) and a N-type MOSFET composition.Specifically, as shown in Figure 1, being based on
The latch 100 of double inverter structures may include have the first transistor MP1, second transistor MN1, third transistor MP2 and
4th transistor MN2；Wherein, the first transistor MP1 and second transistor MN1 constitutes the first phase inverter and (is not marked in figure
Show), the third transistor MP2 and the 4th transistor MN2 constitute the second phase inverter (not indicated in figure).In practical applications,
The source electrode (and substrate) of the first transistor MP1 and third transistor MP2 can connect power supply Vdd (such as 3.3V or
1.8V), the source electrode (and substrate) of the second transistor MN1 and the 4th transistor MN2 can be grounded Vss (generally 0V).
The latch 100 is bi-stable latch, and there are two latch points for tool, specially with phase latch point A and reverse phase latch point B
(or can be interchanged), the logic level that two latch points latch are opposite.
For latch, overturning amplitude represents it by the signal identification of latch between logical zero and logical one
Amplitude difference.The overturning amplitude of latch 100 in the prior art is 0V to supply voltage Vdd.In general, overturning amplitude is
0V can meet the application demand of most of circuits to the latch 100 of supply voltage Vdd；However, with integrated circuit technique
Continuous development, the requirement to chip area and process costs is higher and higher, conventional overturning amplitude be 0V to supply voltage Vdd
Latch 100 increasingly cannot be satisfied the performance requirement of high performance integrated circuit chip.
Utility model content
The technical issues of the utility model solves is how to reduce the overturning amplitude of latch.
In order to solve the above technical problems, the utility model embodiment provides a kind of latch, the latch includes first
Grade minor structure and k second level minor structure, k are the positive integer more than or equal to 1；Wherein：The first order minor structure includes：First
Load, first end couple first port；Second load, first end couple the first port；First driving circuit, it is described
The control terminal of first driving circuit couples the second end of first load, the second end coupling second of first driving circuit
Port；Second driving circuit, the control terminal of second driving circuit couple the second end of second load, and described second drives
The second end of dynamic circuit couples the second port；The second level minor structure includes：Third load, the 4th load, third are driven
Dynamic circuit and the 4th driving circuit；In first second level minor structure, the first end coupling described second of the third load
The second end of the second end of load, the third load couples the control terminal of the third driving circuit, the first driving electricity
The first end of the first end of the first end on road and the 4th driving circuit, the 4th load couples first load
Second end, the second end of the 4th load couple the control terminal of the 4th driving circuit, second driving circuit the
The first end of one end and the third driving circuit, the second end of the third driving circuit and the 4th driving circuit
Second end couples first reference port；In i-th of second level minor structure, the first end coupling (i-1)-th of the third load
The second end of the second end of 4th load of a second level minor structure, the third load couples the control of the third driving circuit
End processed, (i-1)-th second level minor structure third driving circuit first end and the 4th driving circuit first end, institute
State the 4th load first end couple (i-1)-th second level minor structure third load second end, the of the 4th load
Two ends couple the first end of the 4th driving circuit of the control terminal of the 4th driving circuit, (i-1)-th second level minor structure with
And the first end of the third driving circuit, the second end of the second end of the third driving circuit and the 4th driving circuit
Couple i-th of reference port；Wherein, i is the positive integer more than 1 and less than or equal to k.
Optionally, one or more of first load, the second load, third load and the 4th load are resistance.
Optionally, first driving circuit includes：The first transistor, described in the control terminal of the first transistor is used as
The control terminal of first driving circuit, the first end of the first end of the first transistor as first driving circuit are described
Second end of the second end of the first transistor as first driving circuit；Second driving circuit includes：Second crystal
Pipe, the control terminal of the control terminal of the second transistor as second driving circuit, the first end of the second transistor
As the first end of second driving circuit, the second end of the second transistor as second driving circuit second
End.
Optionally, the first transistor and second transistor are N-type MOSFET；The first port is power port,
The power port is suitable for access supply voltage；The grid of the first transistor connects the second end of first load, institute
State the second end that third loads in drain electrode first second level minor structure of connection of the first transistor, the source of the first transistor
Pole connects the second port；The grid of the second transistor connects the second end of second load, second crystal
Draining for pipe connects the second end of the 4th load in first second level minor structure, described in the source electrode connection of the second transistor
Second port.
Optionally, the first transistor and second transistor are bipolar transistor；The first port is power end
Mouthful, the power port is suitable for access supply voltage；The base stage of the first transistor connects the second end of first load,
The collector of the first transistor connects the second end that third loads in first second level minor structure, the first transistor
Emitter connect the second port；The base stage of the second transistor connects the second end of second load, and described the
The collector of two-transistor connects the second end of the 4th load in first second level minor structure, the transmitting of the second transistor
Pole connects the second port.
Optionally, the output end of the second port coupling current source.
Optionally, the first transistor and second transistor are p-type MOSFET；The first port is directly or indirectly
Ground couples reference ground；The grid of the first transistor connects the second end of first load, the leakage of the first transistor
Pole connects the second end of second load, and the source electrode of the first transistor connects the second port；Second crystal
The grid of pipe connects the second end of second load, and the drain electrode of the second transistor connects the second of first load
The source electrode at end, the second transistor connects the second port.
Optionally, the output end of the second port coupling current source.
Optionally, the third driving circuit includes：Third transistor, described in the control terminal of the third transistor is used as
The control terminal of third driving circuit, the first end of the first end of the third transistor as the third driving circuit are described
Second end of the second end of third transistor as the third driving circuit；4th driving circuit includes：4th crystal
Pipe, the control terminal of the control terminal of the 4th transistor as the 4th driving circuit, the first end of the 4th transistor
As the first end of the 4th driving circuit, the second end of the 4th transistor as the 4th driving circuit second
End.
Optionally, the electrical parameter of first load and the second load is identical or different, first driving circuit and the
The electrical parameter of two driving circuits is identical or different, and the electrical parameter of third load and the 4th load is identical or different, and described the
The electrical parameter of three driving circuits and the 4th driving circuit is identical or different.
In order to solve the above technical problems, the utility model embodiment also provides a kind of isolation circuit, the isolation circuit packet
Include above-mentioned latch.
Optionally, the isolation circuit further includes：Main isolating capacitor, voltage-dividing capacitor and amplifier；Wherein, the master
The first end of isolating capacitor couples the input terminal of the isolation circuit, described point of the second end coupling of the main isolating capacitor
The control terminal of the first end of piezoelectric capsule and first driving circuit；The second end coupling ground connection of the voltage-dividing capacitor
End；The control terminal of second driving circuit couples the input terminal of the amplifier；Described in the output end coupling of the amplifier
The output end of isolation circuit.
Compared with prior art, the technical solution of the utility model embodiment has the advantages that：
The latch of the utility model embodiment may include first order minor structure and k second level minor structure, k be more than
Positive integer equal to 1；The first order minor structure includes the first load, the second load, the first driving circuit and the second driving
Circuit；The second level minor structure includes：Third load, the 4th load, third driving circuit and the 4th driving circuit.Wherein,
In i-th of second level minor structure, the first end of the third load couples the 4th load of (i-1)-th second level minor structure
Second end, the second end of third load couple the control terminal of the third driving circuit, (i-1)-th second level minor structure
The first end of the first end of third driving circuit and the 4th driving circuit, the first end coupling i-th-of the 4th load
The second end of the second end of the third load of 1 second level minor structure, the 4th load couples the 4th driving circuit
The first end of 4th driving circuit of control terminal, (i-1)-th second level minor structure and the first end of the third driving circuit,
The second end of the third driving circuit and the second end of the 4th driving circuit couple i-th of reference port；Wherein, i is
Positive integer more than 1 and less than or equal to k.Include first order minor structure and one in the latch based on foregoing circuit structure
When a second level minor structure, overturning amplitude can be based on first load, the second load, third load and the 4th load
Electrical parameter (such as impedance value) and first driving circuit, the second driving circuit, third driving circuit and the 4th driving circuit
Electrical parameter (size of such as output current) be determined.Furthermore, the overturning of the latch of the utility model embodiment
Amplitude is substantially dependent on the electric current of the impedance value and each driving circuit of each load.It is each negative due in specific implementation
The impedance value of load and the electric current of driving circuit can have very wide scope of design, and therefore, the overturning amplitude can be several
Millivolt arrives the arbitrary value of several volts, and the manufacturing process level of the prior art can ensure in any temperature condition and production line
The realization of the overturning amplitude.In conjunction with the development situation of nowadays integrated circuit, the overturning of the latch of the utility model embodiment
Amplitude can meet the performance requirement of high performance integrated circuit (such as isolation circuit).
Furthermore, the utility model embodiment also provides a kind of isolation circuit, may include the utility model reality
Apply the latch in example.The arbitrary of several volts is arrived since the overturning amplitude of the latch of the utility model embodiment can be several millivolts
Value, the inversion energy made it into needed for stable state can be smaller, and the main isolation capacitance of energy is used for transmission in the isolation circuit
The capacitance of device is smaller, so that the chip area of the isolation circuit is smaller, consuming cost is low, in addition, drive the master every
The circuit of circuit and processing common mode inhibition electric current from capacitance is simplified, and is conducive to the system architecture design of the isolation circuit
With optimization.
Description of the drawings
Fig. 1 is a kind of circuit diagram of latch in the prior art.
Fig. 2 is the circuit diagram of another latch in the prior art.
Fig. 3 is a kind of schematic block diagram of latch of the utility model embodiment.
Fig. 4 is the circuit diagram of the first latch of the utility model embodiment.
Fig. 5 is the circuit diagram of second of latch of the utility model embodiment.
Fig. 6 is the circuit diagram of the third latch of the utility model embodiment.
Fig. 7 is the circuit diagram of the 4th kind of latch of the utility model embodiment.
Fig. 8 is a kind of circuit diagram of isolation circuit of the utility model embodiment.
Specific implementation mode
As described in the background section, the overturning amplitude of the latch in the prior art based on double inverter structures be 0V extremely
In general supply voltage can meet the application demand of most of circuits.However, continuous with integrated circuit technique
Development, the requirement to chip area and process costs is higher and higher, and conventional overturning amplitude is latch of the 0V to supply voltage
It increasingly cannot be satisfied the performance requirement of high performance integrated circuit chip.
In order to reduce the overturning amplitude of latch 100 shown in figure 1, occurs another latch in the prior art.
Present inventor analyzes the latch.As shown in Fig. 2, latch 200 may include the first phase inverter I1, second
Phase inverter I2 and resistance R；Wherein, the first phase inverter I1 and the second phase inverter I2 join end to end, and the resistance R is connected to
Between the output end of the first phase inverter I1 and the output end of the second phase inverter I2；The first phase inverter I1 and second
Phase inverter I2 is by P type metal oxide semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-
Effect Transistor, abbreviation MOSFET) and N-type MOSFET structures (it is not shown, Fig. 1 is specifically referred to, is no longer opened up herein
Open introduction).
To put it more simply, assume that the electrical parameter of the first phase inverter I1 and the second phase inverter I2 is identical, and described first is anti-
Mutual conductance when p-type MOSFET and N-type MOSFET in phase device I1 work in saturation region is equal.
Furthermore, the operating condition of the latch 200 is gm× R ＞ 2；Wherein, gmFor the first phase inverter I1
Mutual conductance when p-type MOSFET (or N-type MOSFET) works in saturation region in (or second phase inverter I2), R are the resistance of the resistance R
Anti- value.If VA and VB are respectively the voltage amplitude of two latch points A and B in the latch 200, VT is first phase inverter
The threshold voltage of p-type MOSFET (or N-type MOSFET) in I1 (or second phase inverter I2), Rds are the p-type MOSFET (or N-types
MOSFET) in the resistance value of linear zone.Since as VA-VB ＞ VT, the p-type MOSFET (or N-type MOSFET) leaves saturation region
And entering linear zone, then the operating condition of the latch 200 becomes g at this timem× (Rds//R)≤2, wherein gm≈ 2/Rds,
" Rds//R " indicates that Rds is in parallel with R, namely is equal to (Rds × R)/(Rds+R)；Therefore, VT is the overturning width of the latch
Degree.
For existing integrated circuit technology, VT is generally 0.7V or 0.3V.However, existing integrated circuit technology
In, VT is typically unfixed so that the overturning amplitude of the latch 200 is not different to different chips.In general,
Only control VT stablizes the circuit application requirement that could meet the latch 200 near 50mV.
Further for analysis, since overturning amplitude is smaller, latch enters that the inversion energy needed for stable state is smaller (to post
Under the premise of raw capacitance is also small) for example, when latch is applied in isolation circuit, the energy of isolation circuit is by inside it
Main isolation capacitance be transmitted, it is bigger that latch enters the inversion energy consumed when stable state, it is meant that the main isolation electricity
The capacitance of appearance is bigger, and then means that the chip area for carrying the isolation circuit is bigger, and consuming cost is higher, in addition, driving
The circuit of the circuit and processing common mode inhibition electric current that move the main isolation capacitance is more complicated.At the same time, due in isolation circuit
In, the signal after being isolated generally has the decaying of preset multiple (such as 30 times), and when the overturning amplitude of latch is excessive,
It differs larger between overturning amplitude and the overturning amplitude after decaying, is unfavorable for system design, however, by default times of decaying
Number, which reduces, can make system design more complicated and chip area increase, and therefore, the overturning amplitude for reducing latch is to realize preferably
The best mode of isolation circuit framework.
Based on the above development situation analyzed and combine nowadays integrated circuit, the overturning width of previously described two kinds of latch
Degree is excessive, cannot be satisfied the performance requirement of high performance integrated circuit (such as isolation circuit).
For techniques discussed above problem, the utility model embodiment proposes a kind of latch, in the work of the prior art
Skill processing procedure is horizontal, can accomplish that the overturning amplitude of latch is several millivolts and arrives the arbitrary of several volts in any temperature and production line
Value, can meet the performance requirement of high performance integrated circuit (such as isolation circuit).
It is understandable to enable the above-mentioned purpose, feature and advantageous effect of the utility model to become apparent, below in conjunction with the accompanying drawings
Specific embodiment of the utility model is described in detail.
Fig. 3 is a kind of schematic block diagram of latch of the utility model embodiment.
As shown in figure 3, the utility model embodiment provides a kind of latch 300, the latch 300 may include first
Grade minor structure (not indicated in figure) and k second level minor structure (not indicated in figure), k are the positive integer more than or equal to 1.For letter
Change, only shows that the latch 300 includes that there are one the second level minor structures in Fig. 3.
Specifically, the first order minor structure may include that the first load 101, second loads the 201, first driving circuit
102 and second driving circuit 202；The second level minor structure may include the 301, the 4th load 401 of third load, third drive
302 and the 4th driving circuit 402 of dynamic circuit.
Wherein, the first end coupling first port Port1 of first load 101；The first end of second load 201
Couple the first port Port1；The control terminal A of first driving circuit 102 couples the second of first load 101
End, the second end coupling second port Port2 of first driving circuit 102；The control terminal B of second driving circuit 202
The second end of second load 201 is coupled, the second end of second driving circuit 202 couples the second port Port2.
Furthermore, the control terminal B of the control terminal A of first driving circuit 102 and the second driving circuit 202 can be used as described
Two latch points of latch 300.
In first second level minor structure, the first end of third load 301 couples the of second load 201
The second end at two ends, the third load 302 couples the control terminal of the third driving circuit 302, first driving circuit
The first end of 102 first end and the 4th driving circuit 402, the first end coupling described the of the 4th load 401
The second end of the second end of one load 101, the 4th load 401 couples the control terminal, described of the 4th driving circuit 402
The first end of the first end of second driving circuit 202 and the third driving circuit 302, the third driving circuit 302
Second end and the second end of the 4th driving circuit 402 couple first reference port Port3.
In second second level minor structure (not shown), the first end of the third load (not shown) couples first
The second end of the second end of 4th load 401 of second level minor structure, the third load couples the third driving circuit (figure
Do not show) control terminal, first second level minor structure third driving circuit 302 first end and the 4th driving circuit
The first end of (not shown), the first end of the 4th load couple the of the third load 301 of first second level minor structure
Two ends, the second end of the 4th load couple the control terminal of the 4th driving circuit, first second level minor structure the
The first end of the first end of four driving circuits 402 and the third driving circuit, the second end of the third driving circuit and
The second end of 4th driving circuit couples second reference port (not shown)；Third second level minor structure or even more
The circuit connecting relation of a second level minor structure and so on, it no longer repeats one by one herein.
In conclusion having such as i-th (i is the positive integer more than 1 and less than or equal to the k) a second level minor structure
Lower rule：In i-th of second level minor structure, the first end of third load couples the of (i-1)-th second level minor structure
The second end of the second end of four loads, the third load couples the control terminal of the third driving circuit, (i-1)-th second level
The first end of the first end of the third driving circuit of minor structure and the 4th driving circuit, the first end of the 4th load
The second end of the second end of the third load of (i-1)-th second level minor structure of coupling, the 4th load couples the 4 wheel driven
The first end of 4th driving circuit of the control terminal of dynamic circuit, (i-1)-th second level minor structure and the third driving circuit
First end, the second end of the second end of the third driving circuit and the 4th driving circuit couples i-th of reference port
(not shown).
Further, 101, second load 201 of the first load, third load 301 and the 4th load 401 are two ends
Mouthpart part；First driving circuit 102, the second driving circuit 202, third driving circuit 302 and the 4th driving circuit 402
For three port devices namely first driving circuit 102, the second driving circuit 202, third driving circuit 302 and the 4th
The driving capability of driving circuit 402 is controllable by the input parameter of its control terminal.
It should be noted that the utility model embodiment is to the first port Port1, second port Port2 and i-th
For the concrete form of a reference port without particular determination, they can be any suitable port；For example, the first port
Port1, second port Port2 and i-th reference port can be selected from power port, ground terminal, other functional circuits it is defeated
Enter/output port, or can also be that potential value is other ports etc. of non-zero V.
In specific implementation, 101, second load 201 of the first load, third load 301 and the 4th load 401 can
To be the arbitrary device with electric current rejection ability, for example, 101, second load 201 of the first load, third load 301 with
And the 4th load 401 in one or more can be resistance, but not limited to this, for example, they can also be reactance, capacitance
Or combination thereof etc..
In specific implementation, first driving circuit 102, the second driving circuit 202, third driving circuit 302 and
4th driving circuit 402 can be the device for arbitrarily having current driving ability, such as various transistors appropriate or phase inverter
Deng.Wherein, the transistor can be unipolar transistor (also referred to as field-effect tube, such as N-type MOSFET or p-type MOSFET) or double
Bipolar transistor, full name are bipolar junction-type transistor (Bipolar Junction Transistor, abbreviation BJT).It is described
First driving circuit 102, the second driving circuit 202, third driving circuit 302 and the electric current of the 4th driving circuit 402 output
The signal (such as voltage, electric current) applied by its each port determines.
To put it more simply, the utility model embodiment loads the 101, second load 201, third load 301 with described first
And the 4th load 401 be resistance, first driving circuit 102, the second driving circuit 202, third driving circuit 302 and
4th driving circuit 402 be transistor for illustrate.
Specifically, first driving circuit 102 may include the first transistor (not shown), the first transistor
Control terminal of the control terminal as first driving circuit 102, the first end of the first transistor drives as described first
The first end of dynamic circuit 102, the second end of the second end of the first transistor as first driving circuit 102；It is described
Second driving circuit 202 may include second transistor (not shown), and the control terminal of the second transistor is as described second
The control terminal of driving circuit 202, the first end of the first end of the second transistor as second driving circuit 202, institute
State second end of the second end of second transistor as second driving circuit 202.
More specifically, the third driving circuit 302 may include third transistor (not shown), the third
Control terminal of the control terminal of transistor as the third driving circuit 302, described in the first end of the third transistor is used as
The first end of third driving circuit 302, the second end of the third transistor as the third driving circuit 302 second
End；4th driving circuit 402 may include the 4th transistor (not shown), and the control terminal of the 4th transistor is as institute
State the control terminal of the 4th driving circuit 402, the first end of the 4th transistor as the 4th driving circuit 402 first
End, the second end of the second end of the 4th transistor as the 4th driving circuit 402.
It is understood to one skilled in the art that transistor is three port devices.For unipolar transistor, control terminal one
As be grid, first end and second end can be respectively its drain electrode and source electrode, or exchange；When for bipolar transistor,
Its control terminal is generally base stage, and first end and second end can be respectively its collector and emitter, or exchanges.
In specific implementation, the electrical parameter of first load, 101 and second load 201 can be identical or different, described
The electrical parameter of first driving circuit 102 and the second driving circuit 202 can also be identical or different, third load 301 and the
The electrical parameter of four loads 401 can be identical or different, the electrical parameter of 302 and the 4th driving circuit 402 of the third driving circuit
It can be identical or different.
Preferably, first load 101 is identical with the electrical parameter of the second load 201,102 He of the first driving circuit
The electrical parameter of second driving circuit 202 is also identical, and the electrical parameter of 301 and the 4th load 401 of the third load is also identical, described
The electrical parameter of third driving circuit 302 and the 4th driving circuit 402 is also identical；Namely preferably, the circuit of the latch 300
Structure and electrical parameter are full symmetric.
In the circuit structure and/or electrical parameter non complete symmetry of the latch 300, first driving circuit 102
Control terminal A and the second driving circuit 202 control terminal B (namely two latch points of the latch 300) latch logic
There will be gain coefficient between level, the gain coefficient depends on described first and loads the 101, second load 201, third load
301 and the 4th load 401 electrical parameter (such as impedance value) and first driving circuit 102, the second driving circuit 202,
The electrical parameter (size of such as output current) of third driving circuit 302 and the 4th driving circuit 402.
Include first order minor structure and a second level minor structure in the latch 300 based on foregoing circuit structure
When, the overturning amplitude of the latch 300 can be based on described first and load the 101, second load 201, third load 301 and the
The electrical parameter (such as impedance value) and first driving circuit 102 of four loads 401, the second driving circuit 202, third driving
The electrical parameter (size of such as output current) of circuit 302 and the 4th driving circuit 402 is determined.To put it more simply, can with institute
The impedance value for stating the first load 101 and second load 201 is equal and be R1, the resistance of third load 301 and the 4th load 401
Anti- value is equal and is R2, the output current of first driving circuit, 102 and second driving circuit 202 equal in magnitude and is
I1, the output current of 302 and the 4th driving circuit 402 of the third driving circuit equal in magnitude and illustrates for I2.
Furthermore, the overturning amplitude of the latch 300 of the utility model embodiment can be according to impedance value R1 and electricity
The size for flowing I2 determines.Since in specific implementation, R1 and I2 can have very wide scope of design, therefore, the overturning width
Degree V can be several millivolts of arbitrary values for arriving several volts, and the manufacturing process level of the prior art can in any temperature condition and
Ensure the realization of the overturning amplitude V on production line.In conjunction with the development situation of nowadays integrated circuit, the latch 300 turns over
The amplitude V of turning can meet the performance requirement of high performance integrated circuit (such as isolation circuit).
It should be noted that when the latch 300 includes first order minor structure and multiple second level minor structures, institute
Stating the specific calculation of the overturning amplitude V of latch 300 can suitably be adjusted, but still can be according to corresponding driving
The wider scope of design of the output current of circuit and realize the flexible design to the overturning amplitude V.
Fig. 4 is the circuit diagram of the first latch of the utility model embodiment.
The circuit structure and operation principle basic one for the latch 300 that latch 400 illustrated in fig. 4 goes out as shown in figure 3
It causes, the main distinction is, in the latch 400, first load (not indicated in figure), the second load are (in figure not
Mark), third load (not indicated in figure) and the 4th load (not indicated in figure) can be resistance, and respectively use R1, R2, R3
And R4 is indicated, the first transistor, second transistor, third transistor and the 4th transistor can be N-type
MOSFET, and indicated respectively with MN1, MN2, MN3 and MN4.
Specifically, the first port (not indicated in figure) can be power port (not indicated in figure) described power port
Suitable for accessing supply voltage Vdd.
The grid A of the first transistor MN1 connects the second end of the first load R1, the first transistor MN1
Drain electrode connection first second level minor structure in third load R3 second end, the first transistor MN1 source electrode connection
The second port Port2；The grid B of the second transistor MN2 connect it is described second load R2 second end, described second
The second end of 4th load R4 in drain electrode first second level minor structure of connection of transistor MN2, the second transistor MN2's
Source electrode connects the second port Port2.Wherein, the second port Port2 can be any suitable port, such as it can
To be the input/output end port of other functional circuits, or it can also be that potential value is other ports of appropriate value.
In first second level minor structure, the grid of the third transistor MN3 connects the first transistor MN1's
Drain electrode, the drain electrode of the second end of third load R3 and the 4th transistor MN4, the source electrode of the third transistor MN3 connect
Meet first reference port Port3；The grid of the 4th transistor MN4 connects the drain electrode of the second transistor MN2, the 4th
Load the drain electrode of the second end and the third transistor of R4, described first of the source electrode connection of the 4th transistor MN4
Reference port Port3.Wherein, first reference port Port3 can be any suitable port, such as it can be other work(
The input/output end port of energy circuit, or can also be that potential value is other ports of appropriate value.
Include herein the physical circuit connection structure of more second level minor structures without one to the latch 400
One repeats, and for details, reference can be made to previously described more information.Wherein, before the more information about the latch 400 refers to
Text is to the associated description of latch 300 illustrated in fig. 3, and it will not go into details herein.
Fig. 5 is the circuit diagram of second of latch of the utility model embodiment.
The circuit structure and operation principle basic one of latch 500 and latch 400 illustrated in fig. 4 illustrated in fig. 5
It causes, the main distinction is, in the latch 500, the second port (not indicated in figure) can couple the first electric current
The output end of source Iref1.Wherein, the input terminal of the first current source Iref1 can couple ground terminal Vss.Furthermore,
The first current source Iref1 can provide pull-down current for the first transistor MN1 and second transistor MN2, and (figure is not
Show), when the second port couples the first current source Iref1, previously described I1 is first current source
The output current of Iref1.
Similarly, first reference port (not indicated in figure) can couple the output end of the second current source Iref2,
In, the input terminal of the second current source Iref2 can also couple ground terminal Vss.Furthermore, second current source
Iref2 can in first second level minor structure third transistor MN3 and the 4th transistor MN4 pull-down current is provided
(not shown), when first reference port couples the second current source Iref2, previously described I2 is described the
The output current of two current source Iref2.
It should be noted that the utility model embodiment is to the first current source Iref1's and the second current source Iref2
Circuit structure can be any form of reference current source without specifically limited, as long as it is capable of providing the drop-down electricity
Stream.
Wherein, the more information about the latch 500 refers to above to the phase of latch 400 illustrated in fig. 4
Description is closed, it will not go into details herein.
Fig. 6 is the circuit diagram of the third latch of the utility model embodiment.
The circuit structure and operation principle basic one of latch 600 and latch 500 illustrated in fig. 5 illustrated in fig. 6
Cause, the main distinction is, in the latch 600, the first transistor, second transistor, third transistor and
4th transistor can be p-type MOSFET, and be indicated respectively with MP1, MP2, MP3 and MP4.
Specifically, the first port (not indicated in figure) can directly or indirectly couple reference ground Vss (in Fig. 6
It is illustrated by taking its directly coupling reference ground Vss as an example).The second port (not indicated in figure) can couple the first current source
The input terminal of the output end of Iref1, the first current source Iref1 can couple power port (not indicated in figure), the electricity
Source port is suitable for access supply voltage Vdd.First reference port (not indicated in figure) can couple the second current source
The input terminal of the output end of Iref2, the second current source Iref2 can couple the power port.First second level
In minor structure, the first end of the first end of the third load R3 and the 4th load R4 can be coupled directly or indirectly
Reference ground Vss (Fig. 6 is illustrated by taking its directly coupling reference ground Vss as an example).
The grid A of the first transistor MP1 connects the second end of the first load R1, the first transistor MP1
Drain electrode connection first second level minor structure in third load R3 second end, the first transistor MP1 source electrode connection
The second port；The grid B of the second transistor MP2 connects the second end of the second load R2, second crystal
The second end of 4th load R4, the source electrode of the second transistor MP2 in drain electrode first second level minor structure of connection of pipe MP2
Connect the second port.
In first second level minor structure, the grid of the third transistor MP3 connects the first transistor MP1's
Drain electrode, the drain electrode of the second end of third load R3 and the 4th transistor MP4, the source electrode of the third transistor MP3 connect
Connect first reference port；The grid of the 4th transistor MP4 connects the drain electrode of the second transistor MP2, the 4th load
The drain electrode of the second end of R4 and the third transistor, source electrode connection first reference of the 4th transistor MP4
Port.
Include herein the physical circuit connection structure of more second level minor structures without one to the latch 600
One repeats, and for details, reference can be made to previously described more information.Wherein, before the more information about the latch 600 refers to
Text is to the associated description of latch 500 illustrated in fig. 5, and it will not go into details herein.
Fig. 7 is the circuit diagram of the 4th kind of latch of the utility model embodiment.
The circuit structure and operation principle basic one of latch 700 and latch 500 illustrated in fig. 5 illustrated in fig. 7
Cause, the main distinction is, in the latch 700, the first transistor, second transistor, third transistor and
4th transistor can be bipolar transistor, and be indicated respectively with Q1, Q2, Q3 and Q4.
Specifically, the first port (not indicated in figure) can be power port (not indicated in figure) described power port
Suitable for accessing supply voltage Vdd.
The base stage A of the first transistor Q1 connects the second end of the first load R1, the first transistor Q1's
Collector connects the second end of third load R3 in first second level minor structure, the emitter connection of the first transistor Q1
The second port (not indicated in figure, Fig. 7 is shown so that it couples the output end of the first current source Iref1 as an example)；
The base stage B of the second transistor Q2 connects the second end of the second load R2, and the collector of the second transistor Q2 connects
Connect the second end of the 4th load R4 in first second level minor structure, the emitter connection described second of the second transistor Q2
Port.
In first second level minor structure, the base stage of the third transistor Q3 connects the collection of the first transistor Q1
The collector of electrode, the second end of third load R3 and the 4th transistor Q4, the emitter of the third transistor Q3
First reference port of connection (does not indicate, Fig. 7 is carried out so that it couples the output end of the second current source Iref2 as an example in figure
It shows)；The base stage of the 4th transistor Q4 connect the collector of the second transistor Q2, the 4th load R4 second end with
And the collector of the third transistor, the emitter of the 4th transistor Q4 connect first reference port.
Include herein the physical circuit connection structure of more second level minor structures without one to the latch 700
One repeats, and for details, reference can be made to previously described more information.Wherein, before the more information about the latch 700 refers to
Text is to the associated description of latch 400 illustrated in fig. 4 and latch illustrated in fig. 5 500, and it will not go into details herein.
Fig. 8 is a kind of circuit diagram of isolation circuit of the utility model embodiment.
As shown in figure 8, the utility model embodiment also discloses a kind of isolation circuit 800, the isolation circuit 800 can be with
Include latch of the Fig. 3 in the utility model embodiment to Fig. 7 shown by any one.Due to the lock of the utility model embodiment
The overturning amplitude of storage can be several millivolts of arbitrary values for arriving several volts, and the inversion energy made it into needed for stable state can be smaller,
The capacitance that the main isolating capacitor C1 of energy is used for transmission in the isolation circuit 800 is smaller, so that the isolation circuit
800 chip area is smaller, and consuming cost is low.In addition, the circuit (not shown) of the driving main isolation capacitance C1 and processing are altogether
Mould inhibits the circuit (not shown) of electric current to be simplified, and is conducive to the system architecture design and optimization of the isolation circuit 800.
As a unrestricted example, the isolation circuit 800 may include main isolating capacitor C1, derided capacitors
Device C2, latch L1 (namely the latch of Fig. 3 to Fig. 7 shown by any one) and amplifier AMP1.
Wherein, the first end of the main isolating capacitor C1 couples the input terminal IN of the isolation circuit 800, the master every
Second end from capacitor C1 couples the control terminal A of the first end and first driving circuit 102 of the voltage-dividing capacitor C2
(referring to Fig. 3)；The second end coupling ground terminal Vss of the voltage-dividing capacitor C2；The control terminal B of second driving circuit 202
The input terminal of (referring to Fig. 3) coupling amplifier AMP1；The output end of the amplifier AMP1 couples the isolation circuit 800
Output end OUT.
It should be noted that in order to improve the interference free performance of circuit, the isolation circuit 800 can also use difference knot
Structure (not shown) namely its can be with access differential signal.Correspondingly, the master that quantity is 2 may be used in the isolation circuit 800
Isolating capacitor C1, voltage-dividing capacitor C2 and latch L1.To put it more simply, not expansion is introduced herein.
It should also be noted that, " coupling " in the utility model embodiment refers to directly or indirectly connecting,
It can directly be attached, can also be indirectly attached by other electrical parts.
Although the utility model discloses as above, the utility model is not limited to this.Any those skilled in the art,
It does not depart from the spirit and scope of the utility model, can make various changes or modifications, therefore the scope of protection of the utility model
It should be subject to claim limited range.
Claims (12)
1. a kind of latch, which is characterized in that including first order minor structure and k second level minor structure, k is more than or equal to 1
Positive integer；Wherein：
The first order minor structure includes：
First load, first end couple first port；
Second load, first end couple the first port；
First driving circuit, the control terminal of first driving circuit couple the second end of first load, and described first drives
The second end of dynamic circuit couples second port；
Second driving circuit, the control terminal of second driving circuit couple the second end of second load, and described second drives
The second end of dynamic circuit couples the second port；
The second level minor structure includes：Third load, the 4th load, third driving circuit and the 4th driving circuit；
In first second level minor structure, the first end of the third load couples the second end of second load, described
The second end of third load couples the control terminal of the third driving circuit, the first end of first driving circuit and described
The first end of 4th driving circuit, the first end of the 4th load couple the second end of first load, and the described 4th is negative
The second end of load couples the control terminal of the 4th driving circuit, the first end of second driving circuit and the third and drives
The second end of the first end of dynamic circuit, the second end of the third driving circuit and the 4th driving circuit couples first ginseng
Examine port；
In i-th of second level minor structure, the 4th of first end (i-1)-th second level minor structure of coupling of the third load is negative
The second end of the second end of load, the third load couples the control terminal of the third driving circuit, (i-1)-th second level sub- knot
The first end of the first end of the third driving circuit of structure and the 4th driving circuit, the first end coupling of the 4th load
The second end of the third load of (i-1)-th second level minor structure, second end coupling the 4th driving electricity of the 4th load
The first end of 4th driving circuit of the control terminal on road, (i-1)-th second level minor structure and the of the third driving circuit
The second end of one end, the second end of the third driving circuit and the 4th driving circuit couples i-th of reference port；
Wherein, i is the positive integer more than 1 and less than or equal to k.
2. latch according to claim 1, which is characterized in that first load, the second load, third load and the
One or more of four loads are resistance.
3. latch according to claim 1, which is characterized in that first driving circuit includes：The first transistor, institute
Control terminal of the control terminal of the first transistor as first driving circuit is stated, the first end of the first transistor is as institute
State the first end of the first driving circuit, the second end of the second end of the first transistor as first driving circuit；
Second driving circuit includes：Second transistor, the control terminal of the second transistor is as the second driving electricity
The control terminal on road, the first end of the first end of the second transistor as second driving circuit, the second transistor
Second end of the second end as second driving circuit.
4. latch according to claim 3, which is characterized in that the first transistor and second transistor are N-type
MOSFET；
The first port is power port, and the power port is suitable for access supply voltage；
The grid of the first transistor connects the second end of first load, the drain electrode connection first of the first transistor
The source electrode of the second end that third loads in a second level minor structure, the first transistor connects the second port；
The grid of the second transistor connects the second end of second load, the drain electrode connection first of the second transistor
The second end of 4th load in a second level minor structure, the source electrode of the second transistor connect the second port.
5. latch according to claim 3, which is characterized in that the first transistor and second transistor are bipolarity
Transistor；
The first port is power port, and the power port is suitable for access supply voltage；
The base stage of the first transistor connects the second end of first load, the collector connection the of the first transistor
The emitter of the second end that third loads in one second level minor structure, the first transistor connects the second port；
The base stage of the second transistor connects the second end of second load, the collector connection the of the second transistor
The second end of 4th load in one second level minor structure, the emitter of the second transistor connect the second port.
6. latch according to claim 4 or 5, which is characterized in that the output end of the second port coupling current source.
7. latch according to claim 3, which is characterized in that the first transistor and second transistor are p-type
MOSFET；
The first port directly or indirectly couples reference ground；
The grid of the first transistor connect it is described first load second end, the first transistor drain electrode connection described in
The source electrode of the second end of second load, the first transistor connects the second port；
The grid of the second transistor connect it is described second load second end, the second transistor drain electrode connection described in
The source electrode of the second end of first load, the second transistor connects the second port.
8. latch according to claim 7, which is characterized in that the output end of the second port coupling current source.
9. latch according to claim 1, which is characterized in that the third driving circuit includes：Third transistor, institute
Control terminal of the control terminal of third transistor as the third driving circuit is stated, the first end of the third transistor is as institute
State the first end of third driving circuit, the second end of the second end of the third transistor as the third driving circuit；
4th driving circuit includes：4th transistor, the control terminal of the 4th transistor is as the 4th driving electricity
The control terminal on road, the first end of the first end of the 4th transistor as the 4th driving circuit, the 4th transistor
Second end of the second end as the 4th driving circuit.
10. the latch according to any one of claim 1 to 5,7 to 9, which is characterized in that first load and the
The electrical parameter of two loads is identical or different, and the electrical parameter of first driving circuit and the second driving circuit is identical or different, institute
The electrical parameter for stating third load and the 4th load is identical or different, the electrical parameter of the third driving circuit and the 4th driving circuit
It is identical or different.
11. a kind of isolation circuit, which is characterized in that including claims 1 to 10 any one of them latch.
12. isolation circuit according to claim 11, which is characterized in that further include：Main isolating capacitor, voltage-dividing capacitor
And amplifier；Wherein,
The first end of the main isolating capacitor couples the input terminal of the isolation circuit, the second end of the main isolating capacitor
Couple the first end of the voltage-dividing capacitor and the control terminal of first driving circuit；
The second end of the voltage-dividing capacitor couples ground terminal；
The control terminal of second driving circuit couples the input terminal of the amplifier；
The output end of the amplifier couples the output end of the isolation circuit.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820040682.2U CN207612250U (en) | 2018-01-10 | 2018-01-10 | A kind of latch and isolation circuit |
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| CN201820040682.2U CN207612250U (en) | 2018-01-10 | 2018-01-10 | A kind of latch and isolation circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110022138A (en) * | 2018-01-10 | 2019-07-16 | 荣湃半导体（上海）有限公司 | A kind of latch and isolation circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110022138A (en) * | 2018-01-10 | 2019-07-16 | 荣湃半导体（上海）有限公司 | A kind of latch and isolation circuit |
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