CN206450765U - Line under-voltage spike detects circuit - Google Patents
Line under-voltage spike detects circuit Download PDFInfo
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- CN206450765U CN206450765U CN201621143979.9U CN201621143979U CN206450765U CN 206450765 U CN206450765 U CN 206450765U CN 201621143979 U CN201621143979 U CN 201621143979U CN 206450765 U CN206450765 U CN 206450765U
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Abstract
Circuit is detected the utility model discloses a kind of line under-voltage spike, sub-circuit, static state are obtained including voltage change and sets low sub-circuit, low power consumption control sub-circuit and comparator, and the voltage change obtains the second FET that circuit includes the first FET, is connected with the first FET, the 3rd FET, the first electric capacity and the second electric capacity that are connected with the second FET；The low power consumption control sub-circuit includes the 4th FET, the 5th FET being connected with the 4th FET, the 6th FET being connected with the 5th FET, the 7th FET being connected with the 6th FET, the 8th FET, the 3rd electric capacity and the resistance being connected with the 7th FET；The static state, which sets low sub-circuit, includes the 9th FET, the tenth FET being connected with the 9th FET and the 11st FET being connected with the tenth FET.The utility model is simple in construction, realizes the detection of ultra low quiescent power consumption line under-voltage spike.
Description
Technical field
The utility model is related to integrated circuit fields, the line under-voltage spike inspection of more particularly to a kind of super low-power consumption
Slowdown monitoring circuit.
Background technology
With continuing to develop for electronic equipment, electromagnetic interference phenomenon is more and more obvious.Many accurate electronic equipments, can be even
The situation that you error code, deadlock occur, even burnt, most of the time, it is all due to line under-voltage spike arteries and veins above-mentioned situation occur
Caused by punching interference.
In order to timely be tackled to the spike occurred on power supply, it is necessary to the electricity of a detection spike
Road.Spike detection circuit is typically to be made up of voltage change acquisition circuit and voltage comparator.The work of voltage comparator
A bias current is needed, in order to timely respond to, voltage comparator must be constantly in working condition.Therefore can exist than larger
Quiescent dissipation, in order to reduce quiescent dissipation, it is possible to reduce the working time of voltage comparator, but thus exist can not be timely
The risk for spike that power source-responsive is under-voltage.
Utility model content
The purpose of this utility model is to overcome the deficiencies in the prior art that there is provided a kind of line under-voltage spike of super low-power consumption
Pulse-detecting circuit.
The purpose of this utility model is achieved through the following technical solutions：A kind of line under-voltage spike detection electricity
Road, including voltage change obtain sub-circuit, static state and set low sub-circuit, the low power consumption control that sub-circuit is connected is set low with the static state
Sub-circuit and set low the comparator that sub-circuit and the low power consumption control sub-circuit are connected, the voltage change with the static state
The change that sub-circuit obtains supply voltage is obtained, the static state sets low sub-circuit control when being inputted without spike, the electricity
The output end output low level signal of spike that source is under-voltage detection circuit, the low power consumption control sub-circuit control is having spike
Bias current is provided for the comparator during pulse input, the voltage change, which obtains circuit, includes the first FET and institute
The 3rd FET, the first electricity for state the second connected FET of the first FET, being connected with second FET
The second electric capacity for holding and being connected with first electric capacity；The low power consumption control sub-circuit include the 4th FET, with it is described
The 5th connected FET of 4th FET, the 6th FET being connected with the 5th FET and described the
The 7th connected FET of six FETs, the 8th FET and the described 4th being connected with the 7th FET
FET connected the 3rd electric capacity and resistance；The static state, which sets low sub-circuit, includes the 9th FET and described 9th
The tenth connected FET of effect pipe and the 11st FET being connected with the tenth FET.
The grid of first FET and drain electrode are connected with the source electrode of second FET, second effect
Should pipe grid and drain electrode, the source electrode of the 3rd FET, one end of first electric capacity, the one of second electric capacity
The one end at end, the grid of the 4th FET and the resistance connects an input of the comparator jointly.
The source electrode of 4th FET is connected one end of the 3rd electric capacity, institute with the other end of the resistance jointly
State the draining of the 4th FET, the grid of the 5th FET and drain electrode, it is the grid of the 6th FET, described
The grid of 9th FET and the tenth FET are connected jointly, the drain electrode and the described 7th of the 6th FET
The grid of FET is connected with the grid of drain electrode and the 8th FET, the drain electrode of the 8th FET with it is described
The bias current inputs of comparator are connected.
The drain electrode of 9th FET and the drain electrode of the tenth FET and the 11st FET
Grid is connected, and the drain electrode of the 11st FET is connected with the output end of the comparator.
The source electrode of first FET, the other end of first electric capacity, the source electrode of the 7th FET, institute
The source electrode of the source electrode and the 9th FET of stating the 8th FET connects power end jointly, the 3rd FET
Grid and drain electrode, the other end of second electric capacity, the other end of the 3rd electric capacity, the source electrode of the 5th FET,
The source electrode of 6th FET, the source electrode of the tenth FET, the source electrode of the 11st FET and described
Another input and earth terminal common ground of comparator.
First FET, second FET, the 3rd FET, the 4th FET,
7th FET, the 8th FET, the 9th FET are p-type FET, the 5th effect
Ying Guan, the 6th FET, the tenth FET, the 11st FET are N-type FET.
First FET, second FET and the 3rd FET are replaced by a resistance respectively
Change.
The beneficial effects of the utility model are：Circuit structure is simple, and can just be held when line under-voltage spike arrives
The bias current of comparator is opened, the detection of the line under-voltage spike of ultra low quiescent power consumption is realized.
Brief description of the drawings
Fig. 1 is the particular circuit configurations figure that the spike of the utility model line under-voltage detects circuit；
Fig. 2 is the time diagram that the spike of the utility model line under-voltage detects circuit.
Embodiment
The technical solution of the utility model, but protection domain of the present utility model are described in further detail below in conjunction with the accompanying drawings
It is not limited to as described below.
As shown in figure 1, the utility model line under-voltage spike detection circuit includes voltage change and obtains sub-circuit, quiet
State sets low sub-circuit, sets low low power consumption control sub-circuit that sub-circuit is connected with static and set low sub-circuit and low work(with static state
The connected comparator COM of consumption control sub-circuit.
Wherein, voltage change obtains the change that sub-circuit is used to obtain supply voltage, and static state, which sets low sub-circuit, to be used to control
When being inputted without spike, output end output low level signal, low power consumption control sub-circuit is used to control having spike
During input bias current is provided for comparator COM.
In the utility model, voltage change obtain circuit include the first FET M1, with the first FET M1 phases
The second FET M2 even, the 3rd FET M3 being connected with the second FET M2, the first electric capacity C1 and with it is first electric
Hold the second connected electric capacity C2 of C1；Low power consumption control sub-circuit includes the 4th FET M4, is connected with the 4th FET M4
The 5th FET M5, be connected with the 5th FET M5 the 6th FET M6, be connected with the 6th FET M6
7th FET M7, the 8th FET M8 being connected with the 7th FET M7, be connected with the 4th FET M4
Three electric capacity C3 and resistance R1；Static state sets low the tenth that sub-circuit includes the 9th FET M9, is connected with the 9th FET M9
FET M10 and the 11st FET M11 being connected with the tenth FET M10；Comparator COM includes two inputs
Vip, Vin, bias current inputs ibias, earth terminal and output end Spur_dn.
The physical circuit annexation of the utility model line under-voltage spike detection circuit is as follows：First FET
M1 grid and drain electrode are connected with the second FET M2 source electrode, the second FET M2 grid and drain electrode, the 3rd effect
Should pipe M3 source electrode, the first electric capacity C1 one end, the second electric capacity C2 one end, the 4th FET M4 grid and resistance R1
One end connect comparator COM input Vin jointly；4th FET M4 source electrode connects jointly with the resistance R1 other end
The 3rd electric capacity C3 one end is connect, the voltage end at its tie point is Ps, the 4th FET M4 drain electrode, the 5th FET M5
Grid and drain electrode, the 6th FET M6 grid, the 9th FET M9 grid and the tenth common phases of FET M10
Even, the 6th FET M6 drain electrode and the grid phase of the 7th FET M7 grid and drain electrode and the 8th FET M8
Even, the 8th FET M8 drain electrode is connected with comparator COM bias current inputs ibias；9th FET M9's
Drain electrode is connected with the tenth FET M10 drain electrode and the 11st FET M11 grid, the 11st FET M11's
Drain electrode is connected with comparator COM output end Spur_dn；First FET M1 source electrode, the first electric capacity C1 other end,
Seven FET M7 source electrode, the 8th FET M8 source electrode and the 9th FET M9 source electrode connects power end jointly
VDD, the 3rd FET M3 grid and drain electrode, the second electric capacity C2 other end, the 3rd electric capacity C3 other end, the 5th effect
Should pipe M5 source electrode, the 6th FET M6 source electrode, the tenth FET M10 source electrode, the 11st FET M11 source
Pole and comparator COM input Vip and earth terminal common ground.
Wherein, in the present embodiment, the first FET M1, the second FET M2, the 3rd FET M3, the 4th
Effect pipe M4, the 7th FET M7, the 8th FET M8, the 9th FET M9 are p-type FET, the 5th field-effect
Pipe M5, the 6th FET M6, the tenth FET M10, the 11st FET M11 are N-type FET, in other implementations
In example, above-mentioned FET can realize the component of identical function for other structures, however it is not limited to this.
In other embodiments, voltage change obtains the first FET M1, the second FET M2 in circuit and the
Three FET M3 can be replaced by a resistance respectively.
The operation principle of the utility model line under-voltage spike detection circuit is as follows：
It is no power supply spike under normal circumstances, the input Vin of comparator has quiet when circuit static works
The voltage of state, input Vin is identical with voltage end Ps voltage, and the 4th FET M4 is closed；Comparator COM does not have biased electrical
Stream, does not work.Static state sets low sub-circuit so that comparator COM output end Spur_dn is low level.Now there was only first effect
Should pipe M1, the second FET M2 and the 3rd FET M3 have electric current and flow through, as long as the first FET M1, second
Effect pipe M2 and the 3rd FET M3 breadth length ratio W/L are sufficiently small, and quiescent current can be accomplished very small.
During circuit dynamic duty, a part of component Δ V of peak voltage is obtained by the first electric capacity C1 and the second electric capacity C2,
And be applied on input Vin, when input Vin voltage declines, voltage end Ps voltage will not follow decline at once, this
Sample just can be with the of short duration FET M4 of connection the 4th, and closes static state and set low sub-circuit, makes output end Spur_dn not by by force
Drag down；If the 4th FET M4 has electric current to flow through, comparator COM bias current can be provided, if input Vin
Voltage causes output end Spur_dn to be high level less than ground, then comparator COM.
Please refer to Fig. 2, Fig. 2 is the time diagram that the spike of the utility model line under-voltage detects circuit.By
It can be seen from the figure that, when spike occurs, and peak voltage is when decreaseing beyond the scope Vlevel of setting, can cause output
The signal for holding Spur_dn outputs is high level signal, wherein, supply voltage when VDD_v is quiescent operation.
In the utility model, the detection range Vlevel of peak voltage computational methods are as follows：
When the voltage built using FET obtains sub-circuit, for ratio precisely, the first FET M1, second
FET M2 and the 3rd FET M3 is typically model identical, sets voltages of the Vspur (t) as spike, then real
Border voltage is VDD_v-Vspur (t).The input Vin and voltage phase difference VDD_v/3 on ground, spike component during quiescent operation
Voltage Δ V=Vspur (t) * C1/ (C1+C2), as long as therefore Δ V be more than input Vin voltage, so that it may so that output end
Spur_dn voltage is uprised.
It can thus be concluded that：Vspur(t)>(VDD_v/3)*[(C1+C2)/C1]；
Vlevel=(VDD_v/3) * [(C1+C2)/C1]；
Similarly, it is assumed that build voltage using resistance and obtain sub-circuit, can draw：
Vlevel=[VDD_v*R3/ (R2+R3)] * [(C1+C2)/C1]；
Wherein, C1, C2 represent the first electric capacity C1 and the second electric capacity C2 capacitance respectively, and R1, R2, R3 are equivalent to respectively
Resistance value at one FET M1, the second FET M2 and the 3rd FET M3.
The spike of the utility model line under-voltage detects that circuit sets low sub- electricity by low power consumption control sub-circuit and static state
Road only can just open the bias current of comparator when under-voltage spike arrives, and under normal circumstances, than
Do not worked compared with device, realize the detection of the line under-voltage spike of ultra low quiescent power consumption.
In summary, the utility model line under-voltage spike detection circuit structure is simple, and in line under-voltage spike
Pulse can just open the bias current of comparator when arriving, and realize the inspection of the line under-voltage spike of ultra low quiescent power consumption
Survey.
Claims (7)
1. a kind of line under-voltage spike detects circuit, it is characterised in that：The line under-voltage spike detects circuit bag
Include voltage change obtain sub-circuit, it is static set low sub-circuit, the low power consumption control that sub-circuit is set low with the static state is connected it is sub electric
Road and set low the comparator that sub-circuit and the low power consumption control sub-circuit are connected with the static state, the voltage change is obtained
Sub-circuit obtains the change of supply voltage, and the static state sets low sub-circuit control when being inputted without spike, and the power supply is owed
The output end output low level signal of pointing peak pulse-detecting circuit, the low power consumption control sub-circuit control is having spike
Bias current is provided for the comparator, the voltage change, which obtains circuit, includes the first FET, with described the during input
The second connected FET of one FET, the 3rd FET being connected with second FET, the first electric capacity and
The second electric capacity being connected with first electric capacity；The low power consumption control sub-circuit includes the 4th FET and the described 4th
The 5th connected FET of FET, the 6th FET being connected with the 5th FET and described 6th
The 7th connected FET of effect pipe, the 8th FET being connected with the 7th FET and described 4th effect
Connected the 3rd electric capacity and resistance should be managed；The static state, which sets low sub-circuit, includes the 9th FET and the 9th field-effect
The tenth connected FET of pipe and the 11st FET being connected with the tenth FET.
2. line under-voltage spike according to claim 1 detects circuit, it is characterised in that：First FET
Grid and drain electrode be connected with the source electrode of second FET, the grid of second FET and drain electrode, described
The source electrode of three FETs, one end of first electric capacity, one end of second electric capacity, the grid of the 4th FET
And one end of the resistance connects an input of the comparator jointly.
3. line under-voltage spike according to claim 2 detects circuit, it is characterised in that：4th FET
Source electrode be connected one end of the 3rd electric capacity, the drain electrode of the 4th FET, institute jointly with the other end of the resistance
State grid and drain electrode, the grid of the 6th FET, the grid of the 9th FET and the institute of the 5th FET
The tenth FET is stated jointly to be connected, the drain electrode of the 6th FET and the grid of the 7th FET and drain and
The grid of 8th FET is connected, the drain electrode of the 8th FET and the bias current inputs of the comparator
It is connected.
4. line under-voltage spike according to claim 3 detects circuit, it is characterised in that：9th FET
Drain electrode be connected with the drain electrode of the tenth FET and the grid of the 11st FET, the 11st field-effect
The drain electrode of pipe is connected with the output end of the comparator.
5. line under-voltage spike according to claim 4 detects circuit, it is characterised in that：First FET
Source electrode, the other end of first electric capacity, the source electrode of the 7th FET, the source electrode of the 8th FET and institute
The source electrode for stating the 9th FET connects power end, the grid of the 3rd FET and drain electrode, second electric capacity jointly
The other end, the other end of the 3rd electric capacity, the source electrode of the 5th FET, the source electrode of the 6th FET,
The source electrode of tenth FET, the source electrode of the 11st FET and another input of the comparator and ground connection
Hold common ground.
6. line under-voltage spike according to claim 1 detects circuit, it is characterised in that：First field-effect
Pipe, second FET, the 3rd FET, the 4th FET, the 7th FET, described
Eight FETs, the 9th FET are p-type FET, the 5th FET, the 6th FET, institute
The tenth FET, the 11st FET are stated for N-type FET.
7. line under-voltage spike according to claim 1 detects circuit, it is characterised in that：First field-effect
Pipe, second FET and the 3rd FET are replaced by a resistance respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621143979.9U CN206450765U (en) | 2016-10-21 | 2016-10-21 | Line under-voltage spike detects circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621143979.9U CN206450765U (en) | 2016-10-21 | 2016-10-21 | Line under-voltage spike detects circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206450765U true CN206450765U (en) | 2017-08-29 |
Family
ID=59662760
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201621143979.9U Expired - Fee Related CN206450765U (en) | 2016-10-21 | 2016-10-21 | Line under-voltage spike detects circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206450765U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107966604A (en) * | 2017-11-21 | 2018-04-27 | 广电计量检测（西安）有限公司 | Peak voltage triggering catches circuit and system |
| CN107976584A (en) * | 2016-10-21 | 2018-05-01 | 成都锐成芯微科技股份有限公司 | Line under-voltage spike detection circuit |
| CN112485654A (en) * | 2020-11-16 | 2021-03-12 | 上海唯捷创芯电子技术有限公司 | Chip port state detection circuit, chip and communication terminal |
-
2016
- 2016-10-21 CN CN201621143979.9U patent/CN206450765U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107976584A (en) * | 2016-10-21 | 2018-05-01 | 成都锐成芯微科技股份有限公司 | Line under-voltage spike detection circuit |
| CN107966604A (en) * | 2017-11-21 | 2018-04-27 | 广电计量检测（西安）有限公司 | Peak voltage triggering catches circuit and system |
| CN107966604B (en) * | 2017-11-21 | 2020-05-19 | 广电计量检测（西安）有限公司 | Peak voltage trigger capture circuit and system |
| CN112485654A (en) * | 2020-11-16 | 2021-03-12 | 上海唯捷创芯电子技术有限公司 | Chip port state detection circuit, chip and communication terminal |
| WO2022100756A1 (en) * | 2020-11-16 | 2022-05-19 | 上海唯捷创芯电子技术有限公司 | Chip port state detection circuit, chip, and communication terminal |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170829 Termination date: 20201021 |