CN205566254U - A boostrap circuit for channel selection switch - Google Patents
A boostrap circuit for channel selection switch Download PDFInfo
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- CN205566254U CN205566254U CN201620133054.XU CN201620133054U CN205566254U CN 205566254 U CN205566254 U CN 205566254U CN 201620133054 U CN201620133054 U CN 201620133054U CN 205566254 U CN205566254 U CN 205566254U
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Abstract
The utility model discloses a boostrap circuit for channel selection switch, including be used for receiving incoming signal's incoming signal end, clock signal input, the sub circuit that steps up, control sub circuit, with the gating signal end and the output signal terminal that are used for receiving outside gating signal, clock signal input controls the normal work of the sub circuit that steps up, the voltage of the sub - circuit control output signal terminal that steps up output is the input voltage and the mains voltage sum of incoming signal end, control sub - circuit control when the signal of gating signal end input is effective, the voltage of output signal terminal output is not less than mains voltage. The utility model discloses make the signal of sending into sample hold circuit keep in succession, can follow incoming signal's change and change to reduce the setting -up time of sampling next time, improve the sample rate, be fit for being used for the multichannel selection circuit of high -speed analog front end.
Description
Technical field
This utility model relates to integrated circuit fields, particularly relates to a kind of AFE (analog front end) boostrap circuit for channel selection switch.
Background technology
In the design of integrated circuit, in order to ensure signal bandwidth and the linearity, the multi-channel switch of AFE (analog front end) would generally
Use boostrap circuit.
Existing boostrap circuit, is often applied in sampling hold circuit, and in sampling period, boostrap circuit provides to sampling switch
Grid voltage be: supply voltage VDD and input voltage VIN sum, now, the linearity of sampling switch conduction impedance is good；?
During holding, the grid voltage that boostrap circuit provides to sampling switch is: ground voltage GND, now, sampling switch is turned off.Existing
The waveform diagram of the boostrap circuit for sampling hold circuit having is as shown in Figure 1.
And in the multi-channel switch of AFE (analog front end), signal path is connected with the sampling switch of rear end, if kept
Period, channel selection switch also can be turned off, and now, then can increase sampling next time sets up the time.
Utility model content
The purpose of this utility model is to overcome the deficiencies in the prior art, it is provided that a kind of AFE (analog front end) is used for oneself of channel selection switch
Lift circuit so that the signal sending into sampling hold circuit keeps continuously, it is possible to follows the change of input signal and changes, thus subtracts
Setting up the time of little sampling next time, improves sample rate.
The purpose of this utility model is achieved through the following technical solutions: a kind of boostrap circuit for channel selection switch,
Including for receiving the input signal end of input signal, clock signal input terminal and input signal end and clock signal input terminal phase
Boosting electronic circuit even, be connected with boosting electronic circuit control electronic circuit, with control electronic circuit and be connected for receiving outside gating
The gating signal end of signal and with boosting electronic circuit and control the output signal end that electronic circuit is connected, described clock signal input terminal control
Making the normal work of described boosting electronic circuit, it is described input that described boosting electronic circuit controls the voltage of described output signal end output
The input voltage of signal end and supply voltage sum, described control electronic circuit controls when the signal of described gating signal end input is effective
Time, the voltage of described output signal end output is not less than described supply voltage.
Described clock signal input terminal includes two inputs, and the frequency signal that the input of said two input is orthogonal, described liter
Pressure electronic circuit includes the first field effect transistor being connected with described clock signal input terminal, be connected with described clock signal input terminal the
Two field effect transistor, the 3rd field effect transistor being connected with described clock signal input terminal, be connected with described first field effect transistor the 4th
Field effect transistor, the 5th field effect transistor being connected with described 4th field effect transistor, the 6th effect being connected with described 5th field effect transistor
Ying Guan, the 7th field effect transistor being connected with described 5th field effect transistor and described 6th field effect transistor and described 7th field effect transistor
Be connected the 8th field effect transistor, the 9th field effect transistor being connected with described 8th field effect transistor, be connected with described 9th field effect transistor
The tenth field effect transistor, the 11st field effect transistor being connected with described tenth field effect transistor and be connected with described 4th field effect transistor
Electric capacity.
Described control electronic circuit include the 12nd field effect transistor, the 13rd field effect transistor being connected with described 12nd field effect transistor,
The 14th field effect transistor being connected with described 13rd field effect transistor, the 15th field effect being connected with described 14th field effect transistor
Pipe and the 16th field effect transistor being connected with described 15th field effect transistor.
Described first field effect transistor, described 4th field effect transistor, described 5th field effect transistor, described 6th field effect transistor, described
Tenth field effect transistor, described 12nd field effect transistor, described 13rd field effect transistor and described 15th field effect transistor are p-type field
Effect pipe, described second field effect transistor, described 3rd field effect transistor, described 7th field effect transistor, described 8th field effect transistor,
Described 9th field effect transistor, described 11st field effect transistor, described 14th field effect transistor and described 16th field effect transistor are N
Type field effect transistor.
The grid of the grid of described first field effect transistor and described second field effect transistor and wherein one end of described clock signal input terminal
It is connected, drain electrode and the drain electrode of described second field effect transistor, the grid of described 5th field effect transistor, the institute of described first field effect transistor
The drain electrode of the grid and described 7th field effect transistor of stating the 6th field effect transistor is connected；The source class of described second field effect transistor and described the
The drain electrode of three field effect transistor, one end of described electric capacity, the source class of described 7th field effect transistor and the drain electrode of described 8th field effect transistor
It is connected；The grid of the grid of described 3rd field effect transistor, the grid of described tenth field effect transistor and described 11st field effect transistor is altogether
It is connected with the other end with described clock signal input terminal.
The grid of described 4th field effect transistor and the drain electrode of described 5th field effect transistor, the source class of described 6th field effect transistor, described
The grid of the 7th field effect transistor, the grid of described 8th field effect transistor, the source class of described 9th field effect transistor and described 13rd
The grid of effect pipe is connected, another of the source class of described 4th field effect transistor and the source class of described 5th field effect transistor and described electric capacity
End is connected；Drain electrode and the source class of described 13rd field effect transistor, the source of described 14th field effect transistor of described 6th field effect transistor
Level is common connects described output signal end；The source class of described 8th field effect transistor is connected with described input signal end；Described 9th
The drain electrode of effect pipe is connected with the drain electrode of described tenth field effect transistor and the drain electrode of described 11st field effect transistor.
The grid of described 12nd field effect transistor and the grid of described 15th field effect transistor and the grid of described 16th field effect transistor
The described gating signal end of common connection, the drain electrode of described 12nd field effect transistor is connected with the drain electrode of described 13rd field effect transistor；
The drain electrode of described 14th field effect transistor and the drain electrode of described 15th field effect transistor and the drain electrode phase of described 16th field effect transistor
Even.
The source class of described first field effect transistor, the drain electrode of described 4th field effect transistor, the grid of described 9th field effect transistor, described
The grid of the source class of the tenth field effect transistor, the source class of described 12nd field effect transistor and described 14th field effect transistor connects electricity jointly
Source voltage, the source class of described 3rd field effect transistor, the source class of described 11st field effect transistor and the source of described 16th field effect transistor
Level common ground.
The beneficial effects of the utility model are: make the signal sending into sampling hold circuit keep continuously, it is possible to follow input signal
Change and change, thus reduce next time sampling time of setting up, improve sample rate, be highly suitable for High Speed Analog front end
Multichannel selection circuit.
Accompanying drawing explanation
Fig. 1 is the waveform diagram of the existing boostrap circuit for sampling hold circuit；
Fig. 2 is to use this utility model for the Organization Chart of the channel selectivity circuit of the boostrap circuit of channel selection switch；
Fig. 3 is this utility model circuit framework figure for the boostrap circuit of channel selection switch；
Fig. 4 is this utility model particular circuit configurations figure for the boostrap circuit of channel selection switch；
Fig. 5 is this utility model waveform diagram for the boostrap circuit of channel selection switch.
Detailed description of the invention
The technical solution of the utility model is described in further detail below in conjunction with the accompanying drawings, but protection domain of the present utility model does not limits to
In the following stated.
As in figure 2 it is shown, Fig. 2 is to use this utility model for the frame of the channel selectivity circuit of the boostrap circuit of channel selection switch
Composition, one end of boostrap circuit is used for receiving input signal, and other end output grid voltage controls signal to one end of channel selection switch,
The other end of channel selection switch outputs signal to the sampling hold circuit of rear end for exporting channel selection switch.
As it is shown on figure 3, for the boostrap circuit of channel selection switch, this utility model includes that input signal end, clock signal input
End, be connected with input signal end and clock signal input terminal boosting electronic circuit, with boost electronic circuit be connected control electronic circuit,
The gating signal end being connected with control electronic circuit and the output signal end being connected with boosting electronic circuit and control electronic circuit.Input letter
Number end is used for receiving input signal, and clock signal input terminal is for the normal work of the electronic circuit that controls to boost, and boosting electronic circuit is used for
The voltage controlling output signal end output is input voltage and supply voltage sum, and gating signal end is for receiving the gating letter of outside
Number, controlling electronic circuit for control when the signal of gating signal end input is effective, the voltage of output signal end output is not less than electricity
Source voltage.
As shown in Figure 4, Fig. 4 is this utility model particular circuit configurations figure for the boostrap circuit of channel selection switch.Wherein,
Input signal end is IN end, clock signal input terminal be SP end andEnd, gating signal end isEnd, output signal end
For OUT terminal；Boosting electronic circuit include the first field effect transistor M1, the second field effect transistor M2, the 3rd field effect transistor M3, the 4th
Field effect transistor M4, the 5th field effect transistor M5, the 6th field effect transistor M6, the 7th field effect transistor M7, the 8th field effect transistor M8,
9th field effect transistor M9, the tenth field effect transistor M10, the 11st field effect transistor M11 and electric capacity C；Control electronic circuit and include the
12 field effect transistor M12, the 13rd field effect transistor M13, the 14th field effect transistor M14, the 15th field effect transistor M15 and
16th field effect transistor M16.
Wherein, in the present embodiment, the first field effect transistor M1, the 4th field effect transistor M4, the 5th field effect transistor M5, the 6th
Field effect transistor M6, the tenth field effect transistor M10, the 12nd field effect transistor M12, the 13rd field effect transistor M13 and the 15th
Effect pipe M15 is p-type field effect transistor, the second field effect transistor M2, the 3rd field effect transistor M3, the 7th field effect transistor M7,
Eight field effect transistor M8, the 9th field effect transistor M9, the 11st field effect transistor M11, the 14th field effect transistor M14 and the 16th
Field effect transistor M16 is N-type field effect transistor；In other embodiments, above-mentioned field effect transistor can be that other structures can realize phase
The components and parts of congenerous, however it is not limited to this.
The grid of the first field effect transistor M1 and the grid of the second field effect transistor M2 are connected with clock signal input terminal SP, first
Drain electrode and the drain electrode of the second field effect transistor M2, the grid of the 5th field effect transistor M5, the 6th field effect transistor M6 of effect pipe M1
Grid and the 7th field effect transistor M7 drain electrode be connected；The source class of the second field effect transistor M2 and the leakage of the 3rd field effect transistor M3
The drain electrode of pole, one end of electric capacity C, the source class of the 7th field effect transistor M7 and the 8th field effect transistor M8 is connected；3rd field effect
The grid of the grid of pipe M3, the grid of the tenth field effect transistor M10 and the 11st field effect transistor M11 is common and clock signal inputs
EndIt is connected；The grid of the 4th field effect transistor M4 and the drain electrode of the 5th field effect transistor M5, the source class of the 6th field effect transistor M6,
The grid of the 7th field effect transistor M7, the grid of the 8th field effect transistor M8, the source class of the 9th field effect transistor M9 and the 13rd
The grid of effect pipe M13 is connected, and the source class of the 4th field effect transistor M4 and the source class of the 5th field effect transistor M5 and electric capacity C's is another
One end is connected；Drain electrode and the source class of the 13rd field effect transistor M13, the 14th field effect transistor M14 of the 6th field effect transistor M6
Source class jointly connect output signal end OUT；The source class of the 8th field effect transistor M8 is connected with input signal end IN；9th
The drain electrode of effect pipe M9 is connected with the drain electrode of the tenth field effect transistor M10 and the drain electrode of the 11st field effect transistor M11.
The grid of the 12nd field effect transistor M12 and the grid of the 15th field effect transistor M15 and the grid of the 16th field effect transistor M16
The most jointly connect gating signal endThe drain electrode of the 12nd field effect transistor M12 and the drain electrode phase of the 13rd field effect transistor M13
Even；The drain electrode of the 14th field effect transistor M14 and the drain electrode of the 15th field effect transistor M15 and the leakage of the 16th field effect transistor M16
The most connected.
The source class of the first field effect transistor M1, the drain electrode of the 4th field effect transistor M4, the grid of the 9th field effect transistor M9, the tenth
The grid of the source class of effect pipe M10, the source class of the 12nd field effect transistor M12 and the 14th field effect transistor M14 connects electricity jointly
Source voltage VDD, the source class of the 3rd field effect transistor M3, the source class of the 11st field effect transistor M11 and the 16th field effect transistor M16
Source class common ground.
This utility model is as follows for the operation principle of the boostrap circuit of channel selection switch:
When gating signal endDuring input low level signal, channel is strobed；Clock signal input terminal SP andInput a pair
Orthogonal frequency signal, works as clock signal input terminalInput high level signal, clock signal input terminal SP input low level is believed
Number time, the first field effect transistor M1, the 3rd field effect transistor M3 and the 11st field effect transistor M11 conducting, the second field effect transistor M2
And the tenth field effect transistor M10 cut-off, the 4th field effect transistor M4 and the 13rd field effect transistor M13 conducting, the 5th field effect transistor
M5, the 6th field effect transistor M6, the 7th field effect transistor M7 and the 8th field effect transistor M8 cut-off, the two ends of electric capacity C respectively by
Charging to supply voltage VDD and ground voltage GND, voltage difference now is VDD.
Work as clock signal input terminalInput low level signal, during clock signal input terminal SP input high level signal, first
Effect pipe M1, the 3rd field effect transistor M3 and the cut-off of the 11st field effect transistor M11, the second field effect transistor M2 and the tenth effect
Should pipe M10 conducting, the 4th field effect transistor M4 and the cut-off of the 13rd field effect transistor M13, the 5th field effect transistor M5, the 6th
Effect pipe M6, the 7th field effect transistor M7 and the conducting of the 8th field effect transistor M8, the input signal of input signal end IN is through the
Eight field effect transistor M8 are sent to one end of electric capacity C, and the voltage that now electric capacity C produces is supply voltage VDD and input voltage
VIN sum, input signal exports to output signal end OUT through the 5th field effect transistor M5 and the 6th field effect transistor M6, from
And export grid voltage and control signal to one end of channel selection switch.
As can be seen from the above analysis, as long as channel is strobed, i.e. gating signal endDuring input low level signal, time no matter
Clock signal input part SP andBeing in which phase place, the signal i.e. inputted is high level signal or low level signal, the 12nd
Field effect transistor M12 and the 15th field effect transistor M15 are both turned on, the 16th field effect transistor M16 cut-off, thus ensure that this reality
By the output grid voltage control signal of the novel boostrap circuit for channel selection switch at clock signal input terminalInput high level
Signal, during clock signal input terminal SP input low level signal, the voltage of output signal end OUT output is supply voltage VDD,
At clock signal input terminalInput low level signal, during clock signal input terminal SP input high level signal, output signal end
The voltage of OUT output is supply voltage VDD and input voltage VIN sum.Use as it is shown in figure 5, Fig. 5 is this utility model
In the waveform diagram of the boostrap circuit of channel selection switch, according to circuit structure of the present utility model, it is ensured that in sampling period
Between, the grid voltage provided for sampling switch is: supply voltage VDD and input voltage VIN sum, during keeping, for sampling
The grid voltage that switch provides is supply voltage VDD, and switch clock is held on so that the signal delivering to sampling hold circuit is continuous,
And follow the change of input signal and change, substantially reduce in sampling period, signal, carries to the time of setting up of B point from A point
High sample rate.
In sum, this utility model makes the signal sending into sampling hold circuit keep for the boostrap circuit of channel selection switch
Continuously, it is possible to follow the change of input signal and change, thus reduce the time of setting up of sampling next time, improve sample rate, non-
Often it is suitable for the multichannel selection circuit of High Speed Analog front end.
Claims (8)
1. the boostrap circuit for channel selection switch, it is characterised in that: the described boostrap circuit for channel selection switch
Including for receiving the input signal end of input signal, clock signal input terminal and input signal end and clock signal input terminal phase
Boosting electronic circuit even, be connected with boosting electronic circuit control electronic circuit, with control electronic circuit and be connected for receiving outside gating
The gating signal end of signal and with boosting electronic circuit and control the output signal end that electronic circuit is connected, described clock signal input terminal control
Making the normal work of described boosting electronic circuit, it is described input that described boosting electronic circuit controls the voltage of described output signal end output
The input voltage of signal end and supply voltage sum, described control electronic circuit controls when the signal of described gating signal end input is effective
Time, the voltage of described output signal end output is not less than described supply voltage.
Boostrap circuit for channel selection switch the most according to claim 1, it is characterised in that: described clock signal is defeated
Entering end and include two inputs, and the frequency signal that the input of said two input is orthogonal, described boosting electronic circuit includes with described
The first field effect transistor that clock signal input terminal is connected, the second field effect transistor of being connected with described clock signal input terminal are with described
The 3rd field effect transistor that clock signal input terminal is connected, the 4th field effect transistor being connected with described first field effect transistor and described the
The 5th field effect transistor, the 6th field effect transistor being connected with described 5th field effect transistor and described 5th that four field effect transistor are connected
The 7th field effect transistor that effect pipe and described 6th field effect transistor are connected, the 8th field effect transistor being connected with described 7th field effect transistor,
The 9th field effect transistor, the tenth field effect transistor being connected with described 9th field effect transistor and the institute being connected with described 8th field effect transistor
State the 11st field effect transistor that the tenth field effect transistor is connected and the electric capacity being connected with described 4th field effect transistor.
Boostrap circuit for channel selection switch the most according to claim 2, it is characterised in that: described control electronic circuit
The 13rd field effect transistor including the 12nd field effect transistor, being connected with described 12nd field effect transistor and described 13rd field effect
Pipe be connected the 14th field effect transistor, the 15th field effect transistor being connected with described 14th field effect transistor and with described 15th
The 16th field effect transistor that effect pipe is connected.
Boostrap circuit for channel selection switch the most according to claim 3, it is characterised in that: described first field effect
Pipe, described 4th field effect transistor, described 5th field effect transistor, described 6th field effect transistor, described tenth field effect transistor, described
12nd field effect transistor, described 13rd field effect transistor and described 15th field effect transistor are p-type field effect transistor, described second
Effect pipe, described 3rd field effect transistor, described 7th field effect transistor, described 8th field effect transistor, described 9th field effect transistor,
Described 11st field effect transistor, described 14th field effect transistor and described 16th field effect transistor are N-type field effect transistor.
Boostrap circuit for channel selection switch the most according to claim 4, it is characterised in that: described first field effect
The grid of pipe is connected with the grid of described second field effect transistor and wherein one end of described clock signal input terminal, described first effect
Should pipe drain electrode with the drain electrode of described second field effect transistor, the grid of described 5th field effect transistor, the grid of described 6th field effect transistor
The drain electrode of pole and described 7th field effect transistor is connected；The drain electrode of the source class of described second field effect transistor and described 3rd field effect transistor,
The drain electrode of one end of described electric capacity, the source class of described 7th field effect transistor and described 8th field effect transistor is connected；Described 3rd effect
Should the grid of pipe, the grid of described tenth field effect transistor and described 11st field effect transistor grid the most defeated with described clock signal
The other end entering end is connected.
Boostrap circuit for channel selection switch the most according to claim 5, it is characterised in that: described 4th field effect
The grid of pipe and the drain electrode of described 5th field effect transistor, the source class of described 6th field effect transistor, the grid of described 7th field effect transistor,
The grid of the grid of described 8th field effect transistor, the source class of described 9th field effect transistor and described 13rd field effect transistor is connected, institute
The source class stating the 4th field effect transistor is connected with the described source class of the 5th field effect transistor and the other end of described electric capacity；Described 6th effect
The drain electrode of pipe should jointly be connected described output letter with the source class of described 13rd field effect transistor, the source class of described 14th field effect transistor
Number end；The source class of described 8th field effect transistor is connected with described input signal end；The drain electrode of described 9th field effect transistor and described the
The drain electrode of ten field effect transistor and the drain electrode of described 11st field effect transistor are connected.
Boostrap circuit for channel selection switch the most according to claim 6, it is characterised in that: described 12nd effect
The grid of pipe should jointly be connected described gating letter with the grid of the grid of described 15th field effect transistor and described 16th field effect transistor
Number end, the drain electrode of described 12nd field effect transistor is connected with the drain electrode of described 13rd field effect transistor；Described 14th field effect transistor
Drain electrode be connected with the drain electrode of described 15th field effect transistor and the drain electrode of described 16th field effect transistor.
Boostrap circuit for channel selection switch the most according to claim 7, it is characterised in that: described first field effect
The source class of pipe, the drain electrode of described 4th field effect transistor, the grid of described 9th field effect transistor, the source class of described tenth field effect transistor,
The source class of described 12nd field effect transistor and the grid of described 14th field effect transistor connect supply voltage, described 3rd effect jointly
Should the source class of pipe, the source class of described 11st field effect transistor and the source class common ground of described 16th field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620133054.XU CN205566254U (en) | 2016-02-22 | 2016-02-22 | A boostrap circuit for channel selection switch |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620133054.XU CN205566254U (en) | 2016-02-22 | 2016-02-22 | A boostrap circuit for channel selection switch |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205566254U true CN205566254U (en) | 2016-09-07 |
Family
ID=56818334
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620133054.XU Withdrawn - After Issue CN205566254U (en) | 2016-02-22 | 2016-02-22 | A boostrap circuit for channel selection switch |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205566254U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107104663A (en) * | 2016-02-22 | 2017-08-29 | 成都锐成芯微科技股份有限公司 | Boostrap circuit for channel selection switch |
| CN108242221A (en) * | 2016-12-27 | 2018-07-03 | 无锡中微爱芯电子有限公司 | A kind of low-power consumption height driving LCD bias driving circuits being integrated in MCU |
-
2016
- 2016-02-22 CN CN201620133054.XU patent/CN205566254U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107104663A (en) * | 2016-02-22 | 2017-08-29 | 成都锐成芯微科技股份有限公司 | Boostrap circuit for channel selection switch |
| CN107104663B (en) * | 2016-02-22 | 2023-09-15 | 成都锐成芯微科技股份有限公司 | Bootstrap circuit for channel selection switch |
| CN108242221A (en) * | 2016-12-27 | 2018-07-03 | 无锡中微爱芯电子有限公司 | A kind of low-power consumption height driving LCD bias driving circuits being integrated in MCU |
| CN108242221B (en) * | 2016-12-27 | 2023-10-17 | 无锡中微爱芯电子有限公司 | Low-power consumption high-drive LCD bias driving circuit integrated in MCU |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
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| CP03 | Change of name, title or address |
Address after: 9 / F, block a, building 3, No. 200, Tianfu 5th Street, high tech Zone, Chengdu, Sichuan 610041 Patentee after: CHENGDU ANALOG CIRCUIT TECHNOLOGY Inc. Address before: 610041 room 1705, G1 building, 1800 Yizhou Road, Chengdu high tech Zone, Sichuan. Patentee before: CHENGDU RUICHENG XINWEI TECHNOLOGY Co.,Ltd. |
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| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20160907 Effective date of abandoning: 20230915 |
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| AV01 | Patent right actively abandoned |
Granted publication date: 20160907 Effective date of abandoning: 20230915 |