CN105005345A - Low-power high-speed power supply clamping circuit - Google Patents
Low-power high-speed power supply clamping circuit Download PDFInfo
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- CN105005345A CN105005345A CN201410168036.0A CN201410168036A CN105005345A CN 105005345 A CN105005345 A CN 105005345A CN 201410168036 A CN201410168036 A CN 201410168036A CN 105005345 A CN105005345 A CN 105005345A
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Abstract
The invention discloses a low-power high-speed power supply clamping circuit. The low-power high-speed power supply clamping circuit comprises an operational amplifier, a first field effect transistor and a first resistor, a second resistor, a third resistor and a fourth resistor. A drain electrode of the first field effect transistor is connected with the power supply voltage through the first resistor, a grid electrode of the first field effect transistor is connected with the output terminal of the operational amplifier and one end of the second resistor, a source electrode of the first field effect transistor is grounded, the reverse input terminal of the operational amplifier is connected with one end of the third resistor and one end of the fourth resistor, the other terminal of the fourth resistor and the other terminal of the second resistor are grounded, and the other terminal of the third resistor is connected with the drain electrode of the first field effect transistor and serves as a circuit output terminal. The low-power high-speed power supply clamping circuit is simple in structure, low in cost, easy to implement, fast in response speed, low in power consumption and high in stability.
Description
Technical field
The present invention relates to a kind of power clamp circuit, particularly a kind of low-power consumption high-speed power clamping circuit, belongs to integrated circuit fields.
Background technology
In many integrated circuit and circuit unit, power source generator is all needed to provide stable voltage for system.The voltage exported for preventing power source generator exceeds the magnitude of voltage preset, or needs the voltage by voltage generator exports to carry out step-down, and the output terminal of many voltage generators is connected with clamping circuit usually.Clamping circuit not only complex structure conventional in prior art, cost is higher, and the power attenuation produced under its duty is larger.
Summary of the invention
For the shortcoming of prior art, the object of the present invention is to provide a kind of low-power consumption high-speed power clamping circuit, its structure is simple, easy to implement.
For achieving the above object, present invention employs following technical scheme:
A kind of low-power consumption high-speed power clamping circuit, it comprises operational amplifier, first field effect transistor transistor and the first ~ tetra-resistance, described first field effect transistor drain electrode connects through the first resistance access supply voltage, grid is connected with described operational amplifier output terminal and described second resistance one end, source ground, described operational amplifier reverse input end is connected with described 3rd resistance one end and the 4th resistance one end, the described 4th resistance other end and described second resistance other end ground connection, the described 3rd resistance other end drains with described first field effect transistor and is connected, and as circuit output end.
Further, described amplifier adopts single stage operational amplifier.
Further, described single stage operational amplifier comprises the second ~ seven field effect transistor, described second field effect transistor drain electrode drains with described 4th field effect transistor and is connected, and as described single stage operational amplifier output terminal, described second field effect transistor gate and described 3rd field effect transistor gate, drain electrode and described 5th field effect transistor drain electrode connect, described 5th field effect transistor gate is connected with described 4th field effect transistor gate, and access bias current, described 5th field effect transistor source electrode drains with described 7th field effect transistor and is connected, described 4th field effect transistor source electrode drains with described 6th field effect transistor and is connected, described 7th field effect transistor gate is as described single stage operational amplifier positive input, described 6th field effect transistor gate is as described single stage operational amplifier reverse input end, described 6th field effect transistor source electrode and described 7th field effect transistor source ground, described second field effect transistor source electrode and described 3rd field effect transistor source electrode connect reference voltage.
As one of comparatively preferred embodiment, described first, fourth, five, six, seven field effect transistors adopt N-type metal-oxide-semiconductor, and second and third field effect transistor described adopts P type metal-oxide-semiconductor.
Wherein, described second resistance, as the pull down resistor of described first field effect transistor gate, effectively ensure that the stability of circuit; Single stage operational amplifier is voltage supply fast and effectively, and single stage operational amplifier power consumption is lower.
Compared with prior art, beneficial effect of the present invention comprises: not only structure is simple, and cost is low, easy to implement, and fast response time, and power attenuation is low, has reliable stability.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of low-power consumption high-speed power clamping circuit in the embodiment of the present invention 1;
Fig. 2 is the internal circuit diagram of single stage op method device in Fig. 1 embodiment.
Embodiment
In view of the defect of prior art, the present invention aims to provide a kind of low-power consumption high-speed power clamping circuit, and its structure is simple, easy to implement.
As one of viable solution of the present invention, this low-power consumption high-speed power clamping circuit comprises operational amplifier, first field effect transistor transistor and the first ~ tetra-resistance, described first field effect transistor drain electrode connects through the first resistance access supply voltage, grid is connected with described operational amplifier output terminal and described second resistance one end, source ground, described operational amplifier reverse input end is connected with described 3rd resistance one end and the 4th resistance one end, the described 4th resistance other end and described second resistance other end ground connection, the described 3rd resistance other end drains with described first field effect transistor and is connected, and as circuit output end.
Further, described amplifier adopts single stage operational amplifier.
Further, described single stage operational amplifier comprises the second ~ seven field effect transistor, described second field effect transistor drain electrode drains with described 4th field effect transistor and is connected, and as described single stage operational amplifier output terminal, described second field effect transistor gate and described 3rd field effect transistor gate, drain electrode and described 5th field effect transistor drain electrode connect, described 5th field effect transistor gate is connected with described 4th field effect transistor gate, and access bias current, described 5th field effect transistor source electrode drains with described 7th field effect transistor and is connected, described 4th field effect transistor source electrode drains with described 6th field effect transistor and is connected, described 7th field effect transistor gate is as described single stage operational amplifier positive input, described 6th field effect transistor gate is as described single stage operational amplifier reverse input end, described 6th field effect transistor source electrode and described 7th field effect transistor source ground, described second field effect transistor source electrode and described 3rd field effect transistor source electrode connect reference voltage.
As one of comparatively preferred embodiment, described first, fourth, five, six, seven field effect transistors adopt N-type metal-oxide-semiconductor, and second and third field effect transistor described adopts P type metal-oxide-semiconductor.
Below in conjunction with accompanying drawing and an embodiment, more specific detail is done to technical scheme of the present invention.
Embodiment 1 is consulted this low-power consumption high-speed power clamping circuit of Fig. 1-2 and is comprised single stage operational amplifier U, first metal-oxide-semiconductor Q1 and the first ~ tetra-resistance, first metal-oxide-semiconductor Q1 drain electrode connects and accesses supply voltage V through the first resistance R1, grid is connected with single stage operational amplifier U output terminal out and second resistance R2 one end, source ground GND, single stage operational amplifier U reverse input end is connected with the 3rd resistance R3 one end and the 4th resistance R4 one end, the 4th resistance R4 other end and the second resistance R2 other end ground connection, the 3rd resistance R3 other end drains with the first metal-oxide-semiconductor Q1 and is connected, and as circuit output end.
Wherein, single stage operational amplifier U comprises the second ~ seven metal-oxide-semiconductor, described second metal-oxide-semiconductor Q2 drain electrode drains with the 4th metal-oxide-semiconductor Q4 and is connected, and as single stage operational amplifier U output terminal out, second metal-oxide-semiconductor Q2 grid and the 3rd metal-oxide-semiconductor Q3 grid, drain electrode and the 5th metal-oxide-semiconductor Q5 drain and connect, 5th metal-oxide-semiconductor Q5 grid is connected with the 4th metal-oxide-semiconductor Q4 grid, and access bias current Ibias the 5th metal-oxide-semiconductor Q5 source electrode and drain with the 7th metal-oxide-semiconductor Q7 and be connected, 4th metal-oxide-semiconductor Q4 source electrode drains with the 6th metal-oxide-semiconductor Q6 and is connected, 7th metal-oxide-semiconductor Q7 grid is as single stage operational amplifier U positive input, 6th metal-oxide-semiconductor Q2 grid is as single stage operational amplifier U reverse input end, 6th metal-oxide-semiconductor Q6 source electrode and the 7th metal-oxide-semiconductor Q7 source ground, second metal-oxide-semiconductor Q2 source electrode and the 3rd metal-oxide-semiconductor Q3 source electrode meet reference voltage V cc.
Preferably, first, fourth, five, six, seven metal-oxide-semiconductors adopt N-type metal-oxide-semiconductor, and second and third metal-oxide-semiconductor adopts P type metal-oxide-semiconductor.
In addition to the implementation, the present invention can also have other embodiments.All employings are equal to the technical scheme of replacement or equivalent transformation formation, all drop on the protection domain of application claims.
Claims (4)
1. a low-power consumption high-speed power clamping circuit, it is characterized in that, it comprises operational amplifier, first field effect transistor transistor and the first ~ tetra-resistance, described first field effect transistor drain electrode connects through the first resistance access supply voltage, grid is connected with described operational amplifier output terminal and described second resistance one end, source ground, described operational amplifier reverse input end is connected with described 3rd resistance one end and the 4th resistance one end, the described 4th resistance other end and described second resistance other end ground connection, the described 3rd resistance other end drains with described first field effect transistor and is connected, and as circuit output end.
2. low-power consumption high-speed power clamping circuit according to claim 1, is characterized in that, described amplifier adopts single stage operational amplifier.
3. low-power consumption high-speed power clamping circuit according to claim 2, it is characterized in that, described single stage operational amplifier comprises the second ~ seven field effect transistor, described second field effect transistor drain electrode drains with described 4th field effect transistor and is connected, and as described single stage operational amplifier output terminal, described second field effect transistor gate and described 3rd field effect transistor gate, drain electrode and described 5th field effect transistor drain electrode connect, described 5th field effect transistor gate is connected with described 4th field effect transistor gate, and access bias current, described 5th field effect transistor source electrode drains with described 7th field effect transistor and is connected, described 4th field effect transistor source electrode drains with described 6th field effect transistor and is connected, described 7th field effect transistor gate is as described single stage operational amplifier positive input, described 6th field effect transistor gate is as described single stage operational amplifier reverse input end, described 6th field effect transistor source electrode and described 7th field effect transistor source ground, described second field effect transistor source electrode and described 3rd field effect transistor source electrode connect reference voltage.
4. the low-power consumption high-speed power clamping circuit according to claim 1 or 3, is characterized in that, described first, fourth, five, six, seven field effect transistors adopt N-type metal-oxide-semiconductor, and second and third field effect transistor described adopts P type metal-oxide-semiconductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410168036.0A CN105005345A (en) | 2014-04-24 | 2014-04-24 | Low-power high-speed power supply clamping circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410168036.0A CN105005345A (en) | 2014-04-24 | 2014-04-24 | Low-power high-speed power supply clamping circuit |
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| CN105005345A true CN105005345A (en) | 2015-10-28 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201410168036.0A Pending CN105005345A (en) | 2014-04-24 | 2014-04-24 | Low-power high-speed power supply clamping circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107945825A (en) * | 2017-12-13 | 2018-04-20 | 上海华虹宏力半导体制造有限公司 | A kind of low-power consumption programmed word line voltage generation circuit |
| CN114995568A (en) * | 2022-07-11 | 2022-09-02 | 上海必阳科技有限公司 | Current source with negative linear rate adjustment rate |
-
2014
- 2014-04-24 CN CN201410168036.0A patent/CN105005345A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107945825A (en) * | 2017-12-13 | 2018-04-20 | 上海华虹宏力半导体制造有限公司 | A kind of low-power consumption programmed word line voltage generation circuit |
| CN114995568A (en) * | 2022-07-11 | 2022-09-02 | 上海必阳科技有限公司 | Current source with negative linear rate adjustment rate |
| CN114995568B (en) * | 2022-07-11 | 2023-11-17 | 苏州华芯半导体科技有限公司 | Current source with negative linear rate adjustment rate |
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Application publication date: 20151028 |