CN203278212U - Card-type terminal electrostatic protection circuit - Google Patents
Card-type terminal electrostatic protection circuit Download PDFInfo
- Publication number
- CN203278212U CN203278212U CN 201320338129 CN201320338129U CN203278212U CN 203278212 U CN203278212 U CN 203278212U CN 201320338129 CN201320338129 CN 201320338129 CN 201320338129 U CN201320338129 U CN 201320338129U CN 203278212 U CN203278212 U CN 203278212U
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- CN
- China
- Prior art keywords
- protection circuit
- source electrode
- nmos
- tube
- pipe
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Abstract
The utility model discloses a card-type terminal electrostatic protection circuit which comprises a PMOS (P-channel Metal Oxide Semiconductor) tube Q1 and an NMOS (N-channel Metal Oxide Semiconductor) tube Q2. A source electrode of the PMOS tube Q1 is connected with a power line; the source electrode of the NMOS tube Q2 is connected with a ground wire; drain electrodes of the PMOS tube Q1 and the NMOS tube Q2 are connected with an IO port of a terminal; a diode D is connected between the source electrode of the PMOS tube Q1 and the source electrode of the NMOS tube Q2; a substrate capacitor C1 is connected between the drain electrode of the PMOS tube Q1 and a grid of the PMOS tube Q1; and a substrate capacitor C2 is connected between the drain electrode of the NMOS tube Q2 and the grid of the NMOS tube Q2. The beneficial effects of the utility model are that: the card-type terminal electrostatic protection circuit can provide four electrostatic leakage paths needed by the ESD protection circuit; and the card-type terminal electrostatic protection circuit has the advantages of being simple in structure and low in cost.
Description
Technical field
The utility model relates to a kind of protection circuit, particularly relates to a kind of card form terminal electrostatic discharge protection circuit.
Background technology
The ESD protection circuit of card form terminal need to provide 4 electrostatic leakage paths, and namely from the power line to the port, port is to power line, and ground wire is to port, and port is to ground wire, and existing electrostatic discharge protection circuit is too complicated, and cost is too high.
The utility model content
The purpose of this utility model is to overcome the shortcoming and defect of above-mentioned prior art, and a kind of card form terminal electrostatic discharge protection circuit is provided, and overcomes existing electrostatic discharge protection circuit complex structure, defective that cost is high.
The purpose of this utility model is achieved through the following technical solutions: card form terminal electrostatic discharge protection circuit, comprise PMOS pipe Q1 and NMOS pipe Q2, the source electrode connecting power line of described PMOS pipe Q1, the source electrode of NMOS pipe Q2 connects ground wire, the drain electrode of PMOS pipe Q1 and NMOS pipe Q2 is connected to the IO port of terminal together, be connected with a diode D between the source electrode of PMOS pipe Q1 and NMOS pipe Q2, be connected with a capacitance to substrate C1 between the drain and gate of PMOS pipe Q1, be connected with a capacitance to substrate C2 between the drain and gate of NMOS pipe Q2.
The operation principle of this circuit is: when carrying out the ESD test, if power line ground connection, the IO port adds positive ESD voltage, and the ESD electrostatic induced current directly flows away from the substrate parasitic capacitance C1 of PMOS pipe Q1; The IO port adds negative ESD voltage, and the ESD electrostatic induced current flows through NMOS pipe Q2 successively, diode D and PMOS pipe Q1.If when ground wire grounded, the IO port adds positive ESD voltage, and the ESD electrostatic induced current flows through PMOS pipe Q1 successively, diode D, and NMOS manages Q2; The IO port adds negative voltage, and the ESD electrostatic induced current flows away by the substrate parasitic capacitance C2 of NMOS.
Further; be connected with a protective resistance R1 between the grid of above-mentioned PMOS pipe Q1 and source electrode; be connected with a protective resistance R2 between the grid of described PMOS pipe Q2 and source electrode; be provided with a protective resistance R3 between the drain electrode of described PMOS pipe Q1, NMOS pipe Q2 and IO port; protective resistance R1, R2, R3 are protective action, prevent that metal-oxide-semiconductor from burning out.
The beneficial effects of the utility model are: this circuit not only can provide the ESD protection circuit needed 4 electrostatic leakage paths, also have advantages of simple in structure, cost is low.
Description of drawings
Fig. 1 is structural representation of the present utility model.
Embodiment
The utility model is described in further detail below in conjunction with embodiment, but structure of the present utility model is not limited only to following examples:
[embodiment]
As shown in Figure 1, card form terminal electrostatic discharge protection circuit, comprise PMOS pipe Q1 and NMOS pipe Q2, the source electrode connecting power line of described PMOS pipe Q1, the source electrode of NMOS pipe Q2 connects ground wire, and the drain electrode of PMOS pipe Q1 and NMOS pipe Q2 is connected to the IO port of terminal together, is connected with a diode D between the source electrode of PMOS pipe Q1 and NMOS pipe Q2, be connected with a capacitance to substrate C1 between the drain and gate of PMOS pipe Q1, be connected with a capacitance to substrate C2 between the drain and gate of NMOS pipe Q2.
The operation principle of this circuit is: when carrying out the ESD test, if power line ground connection, the IO port adds positive ESD voltage, and the ESD electrostatic induced current directly flows away from the substrate parasitic capacitance C1 of PMOS pipe Q1; The IO port adds negative ESD voltage, and the ESD electrostatic induced current flows through NMOS pipe Q2 successively, diode D and PMOS pipe Q1.If when ground wire grounded, the IO port adds positive ESD voltage, and the ESD electrostatic induced current flows through PMOS pipe Q1 successively, diode D, and NMOS manages Q2; The IO port adds negative voltage, and the ESD electrostatic induced current flows away by the substrate parasitic capacitance C2 of NMOS.
In the present embodiment; be connected with a protective resistance R1 between the grid of PMOS pipe Q1 and source electrode; be connected with a protective resistance R2 between the grid of described PMOS pipe Q2 and source electrode; be provided with a protective resistance R3 between the drain electrode of described PMOS pipe Q1, NMOS pipe Q2 and IO port; protective resistance R1, R2, R3 are protective action, prevent that metal-oxide-semiconductor from burning out.
Claims (4)
1. card form terminal electrostatic discharge protection circuit, it is characterized in that, comprise PMOS pipe Q1 and NMOS pipe Q2, the source electrode connecting power line of described PMOS pipe Q1, the source electrode of NMOS pipe Q2 connects ground wire, and the drain electrode of PMOS pipe Q1 and NMOS pipe Q2 is connected to the IO port of terminal together, is connected with a diode D between the source electrode of PMOS pipe Q1 and NMOS pipe Q2, be connected with a capacitance to substrate C1 between the drain and gate of PMOS pipe Q1, be connected with a capacitance to substrate C2 between the drain and gate of NMOS pipe Q2.
2. electrostatic discharge protection circuit according to claim 1, is characterized in that, is connected with a protective resistance R1 between the grid of described PMOS pipe Q1 and source electrode.
3. electrostatic discharge protection circuit according to claim 1, is characterized in that, is connected with a protective resistance R2 between the grid of described PMOS pipe Q2 and source electrode.
4. electrostatic discharge protection circuit according to claim 1, is characterized in that, is provided with a protective resistance R3 between the drain electrode of described PMOS pipe Q1, NMOS pipe Q2 and IO port.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320338129 CN203278212U (en) | 2013-06-14 | 2013-06-14 | Card-type terminal electrostatic protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320338129 CN203278212U (en) | 2013-06-14 | 2013-06-14 | Card-type terminal electrostatic protection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203278212U true CN203278212U (en) | 2013-11-06 |
Family
ID=49508540
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201320338129 Expired - Fee Related CN203278212U (en) | 2013-06-14 | 2013-06-14 | Card-type terminal electrostatic protection circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203278212U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103683237A (en) * | 2013-11-28 | 2014-03-26 | 成都市宏山科技有限公司 | Electrostatic protection circuit of mobile equipment |
-
2013
- 2013-06-14 CN CN 201320338129 patent/CN203278212U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103683237A (en) * | 2013-11-28 | 2014-03-26 | 成都市宏山科技有限公司 | Electrostatic protection circuit of mobile equipment |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20131106 Termination date: 20160614 |