CN205584156U - Common mode level produces circuit - Google Patents
Common mode level produces circuit Download PDFInfo
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- CN205584156U CN205584156U CN201620355047.4U CN201620355047U CN205584156U CN 205584156 U CN205584156 U CN 205584156U CN 201620355047 U CN201620355047 U CN 201620355047U CN 205584156 U CN205584156 U CN 205584156U
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- clock signal
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- electric capacity
- field effect
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Abstract
The utility model discloses a common mode level produces circuit, including the first clock signal input, with the two inphase opposition clock signal input of clock signal of first clock signal input, with field effect transistor that the 2nd clock signal input links to each other, with the first clock signal input reaches first electric capacity that field effect transistor links to each other, with field effect transistor reaches second electric capacity and common mode level output end that first electric capacity links to each other the clock signal of first clock signal input is during for low level signal, common mode level output end output common mode level. The utility model discloses the quiescent power dissipation is zero, and dynamic consumption is directly proportional with the clock frequency of system.
Description
Technical field
This utility model relates to integrated circuit fields, and the common mode electrical level particularly relating to a kind of zero quiescent dissipation produces circuit.
Background technology
In switched-capacitor circuit, often need to provide input signal or the common mode electrical level of output signal.This common mode electrical level can not
It is continuous print DC level, and only need to provide during system clock a phase place.It addition, in differential mode is applied, difference is believed
Number common mode electrical level can mutually cut, do not interfere with differential mode result, therefore common mode electrical level need not the most accurate.
Referring to Fig. 1, Fig. 1 is the circuit diagram that existing common mode electrical level produces circuit, and it includes the first resistance R1 and first electricity
The second resistance R2 and one end of electric capacity C, the first resistance R1 that resistance R1 is connected connect power end VDD, the other end and the second electricity
One end of resistance R2 and one end of electric capacity C are connected, common generation common mode electrical level VCOM, the other end of the second resistance R2 and electricity
Hold the other end common ground GND of C.
Being the oscillogram that existing common mode electrical level produces circuit please refer to Fig. 2, Fig. 2, it is defeated that existing common mode electrical level produces circuit
Go out continuous print DC level VCOM=VDD*R2/ (R1+R2), quiescent power supply current in semiconductor integrated circuit Ipower=VDD/ (R1+R2).The most permissible
Finding out, existing common mode electrical level produces circuit and there is electric current all the time, has obvious power consumption.
Utility model content
The purpose of this utility model is to overcome the deficiencies in the prior art, it is provided that a kind of quiescent dissipation is zero, dynamic power consumption and system
The common mode electrical level that clock frequency is directly proportional produces circuit.
The purpose of this utility model is achieved through the following technical solutions: a kind of common mode electrical level produces circuit, during including first
Clock signal input part and the anti-phase second clock signal input part of clock signal of described first clock signal input terminal input and
Described second clock signal input part be connected field effect transistor, be connected with described first clock signal input terminal and described field effect transistor
The first electric capacity, the second electric capacity being connected with described field effect transistor and described first electric capacity and common mode electrical level outfan, described
When the clock signal of one clock signal input terminal input is low level signal, described common mode electrical level outfan output common mode level.
Described second clock signal input part is connected with the grid of described field effect transistor, and the source class of described field effect transistor connects power end,
The drain electrode of described field effect transistor and the positive plate of described first electric capacity, the positive plate of described second electric capacity and the output of described common mode electrical level
End is connected.
The negative plate of described first electric capacity is connected with described first clock signal input terminal, the negative plate earth terminal of described second electric capacity.
Described first clock signal input terminal inputs a pair anti-phase clock signal of system with described second clock signal input part, comes
Control the discharge and recharge of described first electric capacity and described second electric capacity.
Described field effect transistor is p-type field effect transistor.
The beneficial effects of the utility model are: utilize system clock to control capacitor charge and discharge, produce common mode electricity during a phase place
Flat, quiescent dissipation is zero, and dynamic power consumption is directly proportional to system clock frequency.
Accompanying drawing explanation
Fig. 1 is the circuit diagram that existing common mode electrical level produces circuit；
Fig. 2 is the oscillogram that existing common mode electrical level produces circuit；
Fig. 3 is the circuit diagram that this utility model common mode electrical level produces circuit；
Fig. 4 is the oscillogram that this utility model common mode electrical level produces circuit.
Detailed description of the invention
The technical solution of the utility model is described in further detail below in conjunction with the accompanying drawings, but protection domain of the present utility model does not limits to
In the following stated.
As it is shown on figure 3, Fig. 3 is the circuit diagram that this utility model common mode electrical level produces circuit, it includes the first clock signal input
The second clock that the clock signal of end CLK and the input of the first clock signal input terminal is anti-phase is believedWhen entering to hold CLK and second
Zhong XinEnter to hold CLK be connected field effect transistor PM1, be connected with the first clock signal input terminal CLK and field effect transistor PM1
The first electric capacity C1, the second electric capacity C2 being connected with field effect transistor PM1 and the first electric capacity C1 and common mode electrical level outfan
VCOM。
Wherein, second clock signal input partBeing connected with the grid of field effect transistor PM1, the source class of field effect transistor PM1 is even
Meet power end VDD, the drain electrode of field effect transistor PM1 and the positive plate of the first electric capacity C1, the positive plate of the second electric capacity C2 and altogether
Mould level output end VCOM is connected；The negative plate of the first electric capacity C1 and the first clock signal input terminal CLK are connected, and second
The negative plate earth terminal GND of electric capacity C2.First clock signal input terminal CLK and second clock signal input partInput
A pair anti-phase clock signal of system, controls the first electric capacity C1 and the discharge and recharge of the second electric capacity C2, in the CLK=0 phase place phase
Between, output common mode level VCOM when the i.e. first clock signal input terminal CLK is low level.
In this utility model, field effect transistor PM1 is p-type field effect transistor, in other embodiments, field effect transistor PM1
Can be that other are capable of the switching device of identical function.
The operation principle that this utility model common mode electrical level produces circuit is as follows:
During CLK=1 phase place, when the i.e. first clock signal input terminal CLK is high level, field effect transistor PM1 turns on, the
The positive/negative plate of one electric capacity C1 meets power end VDD, and the positive plate of the second electric capacity C2 connects power end VDD, negative plate earth terminal
GND, now, between the positive/negative plate of the second electric capacity C2, pressure reduction is charged to supply voltage VDD, the second electric capacity C2 and stores electricity
Lotus is: QCLK=1=C2*VDD.
During CLK=0 phase place, when the i.e. first clock signal input terminal CLK is low level, field effect transistor PM1 is ended, the
One electric capacity C1 and the second electric capacity C2 is in parallel, the positive plate output common mode level VCOM of the first electric capacity C1 and the second electric capacity C2,
The negative plate earth terminal GND of the first electric capacity C1 and the second electric capacity C2, total electrical charge is: QCLK=0=(C1+C2) * VCOM.
Owing to total electrical charge is constant, it may be assumed that QCLK=1=QCLK=0, then: C2*VDD=(C1+C2) * VCOM.
During CLK=0 phase place, when the i.e. first clock signal input terminal CLK is low level, output common mode level VCOM is:
VCOM=VDD*C2/ (C1+C2), when taking C1=C2, VCOM=VDD/2.
It is the oscillogram that this utility model common mode electrical level produces circuit please refer to Fig. 4, Fig. 4.At this utility model common mode electricity
Show no increases in output in raw circuit, without DC channel between power supply and ground, quiescent power supply current in semiconductor integrated circuit IpowerIt is zero, utilizes system clock CLK,
Dynamic supply current IpowerIt is directly proportional to the frequency of system clock CLK.
In sum, this utility model common mode electrical level generation circuit, compared with existing common mode electrical level generation circuit, has obvious merit
Consumption advantage.
Claims (5)
1. a common mode electrical level produces circuit, it is characterised in that: described common mode electrical level produces circuit and includes the first clock signal input
End and the anti-phase second clock signal input part of clock signal of described first clock signal input terminal input and when described second
Clock signal input part be connected field effect transistor, the first electric capacity being connected with described first clock signal input terminal and described field effect transistor,
The second electric capacity being connected with described field effect transistor and described first electric capacity and common mode electrical level outfan, defeated in described first clock signal
Enter the clock signal of end input when being low level signal, described common mode electrical level outfan output common mode level.
Common mode electrical level the most according to claim 1 produce circuit, it is characterised in that: described second clock signal input part with
The grid of described field effect transistor is connected, and the source class of described field effect transistor connects power end, the drain electrode of described field effect transistor and described the
The positive plate of one electric capacity, the positive plate of described second electric capacity and described common mode electrical level outfan are connected.
Common mode electrical level the most according to claim 2 produces circuit, it is characterised in that: the negative plate of described first electric capacity and institute
State the first clock signal input terminal to be connected, the negative plate earth terminal of described second electric capacity.
Common mode electrical level the most according to claim 1 produce circuit, it is characterised in that: described first clock signal input terminal with
Described second clock signal input part inputs a pair anti-phase clock signal of system, controls described first electric capacity and described second electricity
The discharge and recharge held.
Common mode electrical level the most according to claim 1 produces circuit, it is characterised in that: described field effect transistor is p-type field effect
Pipe.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620355047.4U CN205584156U (en) | 2016-04-26 | 2016-04-26 | Common mode level produces circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620355047.4U CN205584156U (en) | 2016-04-26 | 2016-04-26 | Common mode level produces circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205584156U true CN205584156U (en) | 2016-09-14 |
Family
ID=56860128
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620355047.4U Active CN205584156U (en) | 2016-04-26 | 2016-04-26 | Common mode level produces circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205584156U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107317570A (en) * | 2016-04-26 | 2017-11-03 | 成都锐成芯微科技股份有限公司 | Common mode electrical level generation circuit |
-
2016
- 2016-04-26 CN CN201620355047.4U patent/CN205584156U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107317570A (en) * | 2016-04-26 | 2017-11-03 | 成都锐成芯微科技股份有限公司 | Common mode electrical level generation circuit |
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| GR01 | Patent grant |