CN202495918U - Square wave-to-triangle wave conversion circuit and chip - Google Patents

Abstract

The utility model is applicable to the electronic field, and provides a square wave to triangular wave circuit and a chip. The square wave to triangular wave circuit includes a first bias current source, a first P-type MOS tube, a second P-type MOS tube, The high-side current mirror formed by the third P-type MOS transistor and the fourth P-type MOS transistor is composed of a second bias current source, a first N-type MOS transistor, a second N-type MOS transistor, a third N-type MOS transistor, and a second N-type MOS transistor. The low-side current mirror composed of four N-type MOS tubes, the first switch tube, the second switch tube and the capacitor; the square wave to triangular wave circuit adopted by the utility model uses a square wave signal to control the turn-on and turn-off of the MOS transistor, through The normal working current mirror linearly charges and discharges the capacitor, so that the square wave is converted into a triangle wave with adjustable rising slope, falling slope, amplitude and period. Compared with the existing technology, the structure is simple, the required chip area is small, and the components The number is reduced by more than half, and the static power consumption is very low.

Description

A square wave to triangle wave circuit and chip

technical field

The utility model belongs to the field of electronics, in particular to a square wave to triangle wave circuit. the

Background technique

At present, the square wave to triangle wave circuit generally needs an operational amplifier, two resistors and a capacitor to form an integral operation circuit, and the square wave is integrated by the integral circuit to obtain a triangle wave. Therefore, the entire square wave to triangle wave circuit structure is relatively complicated, especially in the semiconductor integrated circuit process, resistors and capacitors require a large chip area, and the operational amplifier not only constitutes more components, but also consumes a certain amount of static power consumption. the

As the functions of consumer electronic products continue to increase and the size becomes smaller and smaller, the integration of electronic systems is required to be continuously improved, and the power consumption is getting smaller and smaller. Therefore, the circuit design is constantly developing towards low power consumption and high integration. the

Utility model content

The purpose of the utility model is to provide a square wave to triangle wave circuit, which aims to solve the problems of complex structure, large chip area and large static power consumption in the prior art. In order to solve the above-mentioned technical problems, the utility model adopts the following schemes to realize:

A square wave to triangular wave circuit is characterized in that it includes a high voltage circuit composed of a first bias current source, a first P-type MOS transistor, a second P-type MOS transistor, a third P-type MOS transistor, and a fourth P-type MOS transistor. A side current mirror, a low-side current mirror composed of a second bias current source, a first N-type MOS transistor, a second N-type MOS transistor, a third N-type MOS transistor, and a fourth N-type MOS transistor, and the first switching tube , a second switch tube and a capacitor;

The gate of the first switching transistor is controlled by an input square wave signal, the drain is connected to the gate of the fourth P-type MOS transistor, and the source is connected to the power supply;

The gate of the first P-type MOS transistor is respectively connected to the drain of the first P-type MOS transistor, the gate of the second P-type MOS transistor, and the source of the third P-type MOS transistor;

The source of the first P-type MOS transistor and the source of the second P-type MOS transistor are connected to a power supply, and the drain of the second P-type MOS transistor is connected to the source of the fourth P-type MOS transistor;

The gate of the third P-type MOS transistor is respectively connected to the drain of the third P-type MOS transistor and the gate of the fourth P-type MOS transistor, and the drain of the third P-type MOS transistor is biased by the first bias current source to ground;

The gate of the second switching transistor is controlled by an input square wave signal, the drain is connected to the gate of the second N-type MOS transistor, and the source is grounded;

The power supply is respectively connected to the drain and gate of the first N-type MOS transistor through the second bias current source, and the gate of the first N-type MOS transistor is also connected to the gate of the second N-type MOS transistor;

The gate of the third N-type MOS transistor is respectively connected to the drain of the third N-type MOS transistor and the gate of the fourth N-type MOS transistor, and the drain of the third N-type MOS transistor is connected to the first N-type MOS transistor. The source of the MOS tube is connected and the source is grounded;

The drain of the fourth N-type MOS transistor is connected to the source of the second N-type MOS transistor, and the source is grounded;

The drain of the second N-type MOS transistor and the drain of the fourth P-type MOS transistor are connected to the output node;

One end of the capacitor is connected to the output node, and the other end is respectively connected to the source of the third N-type MOS transistor and the source of the fourth N-type MOS transistor and grounded.

Further, the first switching transistor is an enhancement type P-channel MOS transistor. the

Further, the second switching transistor is an enhancement type N-channel MOS transistor. the

Another object of the present invention is to provide a chip with the above square wave to triangle wave circuit. the

The square wave to triangular wave circuit adopted by the utility model uses the square wave signal to control the turn-on and turn-off of the MOS transistor, and the capacitor is linearly charged and discharged through the normal working current mirror, so that the square wave is converted into a rising slope, a falling slope, an amplitude Compared with the prior art, the triangular wave with adjustable value and period has a simple structure, requires a small chip area, reduces the number of components by more than half, and requires only a small static power consumption. the

Description of drawings

Fig. 1 is a schematic diagram of the circuit structure of the square wave to triangle wave circuit provided by the utility model. the

Detailed ways

In order to make the purpose, technical solutions and advantages of the present utility model clearer, the utility model will be further described in detail below in conjunction with the accompanying drawings and embodiments; it should be understood that the specific embodiments described here are only used to explain the utility model, It is not used to limit the utility model. the

As shown in Figure 1, the square wave to triangle wave circuit provided by the utility model includes a first bias current source I1, a first P-type MOS transistor P1, a second P-type MOS transistor P2, and a third P-type MOS transistor P3 , The high-side current mirror formed by the fourth P-type MOS transistor P4 is composed of the second bias current source I2, the first N-type MOS transistor N1, the second N-type MOS transistor N2, the third N-type MOS transistor N3, the fourth A low-side current mirror composed of N-type MOS transistor N4, the first switch tube M1, the second switch tube M2 and the capacitor C3;

The gate of the first switching tube M1 is controlled by the input square wave signal SW, the drain is connected to the gate of the fourth P-type MOS transistor P4, and the source is connected to the power supply VDD. The first switching tube is an enhanced type P channel MOS tube;

The gate of the first P-type MOS transistor P1 is respectively connected to the drain of the first P-type MOS transistor P1, the gate of the second P-type MOS transistor P2, and the source of the third P-type MOS transistor P3;

The source of the first P-type MOS transistor P1 and the source of the second P-type MOS transistor P2 are connected to the power supply VDD, and the drain of the second P-type MOS transistor P2 is connected to the source of the fourth P-type MOS transistor P4 pole connection;

The gate of the third P-type MOS transistor P3 is respectively connected to the drain of the third P-type MOS transistor P3 and the gate of the fourth P-type MOS transistor P4, and the drain of the third P-type MOS transistor P3 passes through The first bias current source I1 is grounded;

The high-side current mirror is connected to the ground through the first bias current source I1, and mirrors the bias current I1 to form a charging current Iup.

The gate of the second switching tube M2 is controlled by the input square wave signal SW, the drain is connected to the gate of the second N-type MOS transistor N2, and the source is grounded, and the second switching tube is an enhanced N-channel MOS tube;

The power supply VDD is respectively connected to the drain and gate of the first N-type MOS transistor N1 through the second bias current source I2, and the gate of the first N-type MOS transistor N1 is also connected to the gate of the second N-type MOS transistor N2. pole connection;

The gate of the third N-type MOS transistor N3 is respectively connected to the drain of the third N-type MOS transistor N3 and the gate of the fourth N-type MOS transistor N4, and the drain of the third N-type MOS transistor N3 is connected to the gate of the fourth N-type MOS transistor N3. The source of the first N-type MOS transistor N1 is connected and the source is grounded;

The drain of the fourth N-type MOS transistor N4 is connected to the source of the second N-type MOS transistor N2, and the source is grounded;

The drain of the second N-type MOS transistor N2 and the drain of the fourth P-type MOS transistor P4 are connected to the output node Vout;

One end of the capacitor C3 is connected to the output node Vout, and the other end is respectively connected to the source of the third N-type MOS transistor N3 and the source of the fourth N-type MOS transistor N4 and grounded.

The output node Vout is the output terminal of the square wave to triangular wave circuit;

The low-side current mirror is connected to the power supply VDD through the second bias current source I2, and mirrors the bias current I2 to form a discharge current Idn.

The working principle of the square wave to triangle wave circuit is as follows:

Both the first switching tube M1 and the second switching tube M2 are controlled by the input square wave signal SW.

If the input of the square wave signal SW is at a high level, the gates of the first switching tube M1 and the second switching tube M2 are both at a high level. Since the first switching tube M1 is a P-channel MOS tube and the second switching tube M2 is an N-channel MOS transistor, the first switch M1 is turned off, the second switch M2 is turned on, and the source of the second switch M2 is grounded, that is, the gate of the first N-type MOS transistor N1, the second N-type MOS The gates of the transistor N2 are connected to the "ground", so the gates of the first N-type MOS transistor N1 and the second N-type MOS transistor N2 are both at low level, and the first N-type MOS transistor N1 and the second The N-type MOS transistors N2 are all cut off, and the circuit composed of the second bias current source I2, the first N-type MOS transistor N1, the second N-type MOS transistor N2, the third N-type MOS transistor N3, and the fourth N-type MOS transistor N4 The low-side current mirror does not work; because the first switch tube M1 is cut off, the source and drain of the first switch tube M1 are equivalent to disconnection, and the first bias current source I1, the first P-type MOS tube P1, The high-side current mirror composed of the second P-type MOS transistor P2, the third P-type MOS transistor P3, and the fourth P-type MOS transistor P4 works normally, and outputs the bias current I1 as a mirror image to form a charging current Iup, and linearizes the capacitor C3. Charge. the

If the input of the square wave signal SW is at low level, the gates of the first switching tube M1 and the second switching tube M2 are both at low level, since the first switching tube M1 is a P-channel MOS tube, and the second switching tube M2 If it is an N-channel MOS tube, the first switch tube M1 is turned on and the second switch tube M2 is turned off. Since the source of the first switch tube M1 is connected to the power supply VDD and is at a high level, the drain of the first switch tube M1 is very high. Level, that is, the gate of the third P-type MOS transistor P3 and the gate of the fourth P-type MOS transistor P4 are both high level, so the third P-type MOS transistor P3 and the fourth P-type MOS transistor P4 are all cut off , the high-side current mirror composed of the first bias current source I1, the first P-type MOS transistor P1, the second P-type MOS transistor P2, the third P-type MOS transistor P3, and the fourth P-type MOS transistor P4 does not work; Because the second switching tube M2 is cut off, the drain and the source of the second switching tube M2 are disconnected, and the second bias current source I2, the first N-type MOS transistor N1, and the second N-type MOS transistor N2 , the low-side current mirror formed by the third N-type MOS transistor N3 and the fourth N-type MOS transistor N4 works normally, mirrors and outputs the bias current I2 to form a discharge current Idn, and linearly discharges the capacitor C3. the

According to the capacitance potential difference formula: ΔV=I/C·Δt, I is the constant charge and discharge current, and C is the capacitance value, so the voltage on the capacitor C3 is a linearly changing value, that is, the voltage on the capacitor C3 changes linearly with time Vary, the node "VOUT" outputs a triangle wave with a slope of I/C. the

By adjusting the size of the capacitor C3 and the size of the first bias current source I1, the rising slope of the triangular wave can be adjusted. the

By adjusting the size of the capacitor C3 and the size of the second bias current source I2, the falling slope of the triangular wave can be adjusted. the

By adjusting the period of the input square wave, the period of the output triangle wave can be adjusted. the

By adjusting the duty ratio of the input square wave, the size of the capacitor C3, the size of the first bias current source I1, and the size of the second bias current source I2, the amplitude of the output triangle wave can be adjusted. the

The square wave to triangular wave circuit adopted by the utility model uses a square wave signal to control the on and off of the MOS transistor, and the capacitor is linearly charged and discharged through the normal working current mirror, so that the square wave is converted into a rising slope, a falling slope, an amplitude Compared with the prior art, the triangular wave with adjustable value and period has a simple structure, requires a small chip area, reduces the number of components by more than half, and requires only a small static power consumption. the

The above descriptions are only preferred embodiments of the present utility model, and are not intended to limit the present utility model. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present utility model shall be included in this utility model. within the scope of protection of utility models. the

Claims (4)

1. a square wave changes triangle wave circuit; It is characterized in that comprising the high side current mirror that constitutes by first bias current sources, a P type metal-oxide-semiconductor, the 2nd P type metal-oxide-semiconductor, the 3rd P type metal-oxide-semiconductor, the 4th P type metal-oxide-semiconductor; By the downside current mirror that second bias current sources, a N type metal-oxide-semiconductor, the 2nd N type metal-oxide-semiconductor, the 3rd N type metal-oxide-semiconductor, the 4th N type metal-oxide-semiconductor constitute, first switching tube, second switch pipe and electric capacity;

Control, drain electrode is connected with the grid of the 4th P type metal-oxide-semiconductor, source electrode is connected with power supply by square-wave signal by importing for the grid of said first switching tube;

The grid of a said P type metal-oxide-semiconductor is connected with the drain electrode of a P type metal-oxide-semiconductor, the grid of the 2nd P type metal-oxide-semiconductor and the source electrode of the 3rd P type metal-oxide-semiconductor respectively;

The source electrode of a said P type metal-oxide-semiconductor is connected with power supply with the source electrode of the 2nd P type metal-oxide-semiconductor, and the drain electrode of said the 2nd P type metal-oxide-semiconductor is connected with the source electrode of the 4th P type metal-oxide-semiconductor;

The grid of said the 3rd P type metal-oxide-semiconductor is connected with the drain electrode of the 3rd P type metal-oxide-semiconductor, the grid of the 4th P type metal-oxide-semiconductor respectively, and the drain electrode of said the 3rd P type metal-oxide-semiconductor is through the first bias current sources ground connection;

Control, drain electrode is connected with the grid of the 2nd N type metal-oxide-semiconductor, source ground by square-wave signal by importing for the grid of said second switch pipe;

Power supply is connected with the drain and gate of a N type metal-oxide-semiconductor respectively through second bias current sources, and the grid of a said N type metal-oxide-semiconductor also is connected with the grid of the 2nd N type metal-oxide-semiconductor;

The grid of said the 3rd N type metal-oxide-semiconductor is connected with the drain electrode of the 3rd N type metal-oxide-semiconductor, the grid of the 4th N type metal-oxide-semiconductor respectively, and the drain electrode of said the 3rd N type metal-oxide-semiconductor is connected with the source electrode of a N type metal-oxide-semiconductor, source ground;

The drain electrode of said the 4th N type metal-oxide-semiconductor is connected with the source electrode of the 2nd N type metal-oxide-semiconductor, source ground;

The drain electrode of said the 2nd N type metal-oxide-semiconductor links to each other with output node with the drain electrode of the 4th P type metal-oxide-semiconductor;

Said electric capacity one end is connected with output node, the other end is connected and ground connection with the source electrode of the 3rd N type metal-oxide-semiconductor, the source electrode of the 4th N type metal-oxide-semiconductor respectively.

2. square wave according to claim 1 changes triangle wave circuit, it is characterized in that first switching tube is the P channel MOS tube of enhancement mode.

3. square wave according to claim 1 changes triangle wave circuit, it is characterized in that the second switch pipe is the N-channel MOS pipe of enhancement mode.

4. a chip is characterized in that, said chip comprises that each described square wave changes triangle wave circuit among the claim 1-3.

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