CN203788266U - Circuit structure used for eliminating short-circuit currents - Google Patents
Circuit structure used for eliminating short-circuit currents Download PDFInfo
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- CN203788266U CN203788266U CN201420078904.1U CN201420078904U CN203788266U CN 203788266 U CN203788266 U CN 203788266U CN 201420078904 U CN201420078904 U CN 201420078904U CN 203788266 U CN203788266 U CN 203788266U
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Abstract
The utility model provides a circuit structure used for eliminating short-circuit currents. The circuit structure is characterized by at least comprising a first stage drive circuit and a first time delay unit. The first stage drive circuit is at least provided with a first input terminal, a first output terminal and a second output terminal; and the first time delay unit is arranged between the first output terminal and the second output terminal, and the first time delay unit comprises a first transistor and a second transistor. Through a short time delay, the moment when a switch in a complementary type circuit is switched on and off is missed, a short circuit current Is which causes unstable circuits is fundamentally eliminated, and the safety and the stability of the whole circuit are protected. At the same time, because the first output terminal and the second output terminal do not output electric signals synchronously, the moment when a switch in a subsequent cascaded complementary type circuit is switched on and off is missed, and a short circuit current which causes unstable circuits is eliminated. The circuit structure used for eliminating the short-circuit currents is advantaged by being safe, stable and energy saving, being without short circuit loss, being low in cost and the like, and can be applied to innovative improvements of standard cell libraries.
Description
Technical field
The utility model relates to standard cell circuit, is specifically related to the circuit structure for eliminating short circuit current.
Background technology
In complementary type drive circuit, the structure that particularly standard cell circuit is commonly used, it is generally made up of (with reference to accompanying drawing 1 two metal-oxide-semiconductors, include the first order circuit of transistor 11,12 compositions, the second level circuit being formed by transistor 21,22), realize subsequent conditioning circuit is exported to high or low level signal.But, whenever the level of complementary type drive circuit input is during in high and low value shear, because metal-oxide-semiconductor switch carries out opening and closing movement under synchronised clock, while having occurred being at a time worth, the situation of two metal-oxide-semiconductor switch conductings is simultaneously (with reference to accompanying drawing 3, as input voltage V
iNin the time rising moment t2 to t4 or decline moment t7 to t9, there is conducting simultaneously in metal-oxide-semiconductor), this causes between power supply and signal ground and produces short circuit, short circuit current I
smoment is poured into signal ground.Above-mentioned situation is extensively present in the middle of standard cell circuit, if logical “and” circuit is (with reference to accompanying drawing 2, comprise the first order circuit being formed by transistor 81,82,83,84, the second level circuit being formed by transistor 91,92), in the time that transistor 91 drives its folding with 92 by the level signal of synchronizeing, will produce the situation of conducting simultaneously, produce the short circuit current I from power supply to signal ground
s.Due to this short circuit current I
sexistence, the operation of logical “and” circuit will be extremely unstable because of clocking noise, increase and occur wrong at any time probability.Meanwhile, in the middle of integrated circuit, if the quantity of the standard cell circuits such as logical “and” circuit is quite huge, therefore this short circuit current I
sthe impact causing will be large by geometric grading, comprising: 1, be the most directly the consume that causes electric energy, increased power consumption and the caloric value of circuit; 2, produce a large amount of random noises at signal ground end, thereby cause sequential confusion, the computing of integrated circuit to occur Unpredictability anchor mistake, affect the stability of circuit and the delay that produces signal; 3, the inverse electromotive force of inductance in the easy detonator circuit of instantaneous surge, damages internal circuit.
For this reason, how to eliminate the short circuit current I in complementary type drive circuit
sbecome a technical barrier that needs to be captured.Existing designer wishes to drive with asynchronous signal by two metal-oxide-semiconductors to complementary type drive circuit, with avoid two metal-oxide-semiconductors in the situation of synchronization conducting (with reference to accompanying drawing 4, between input IN and metal-oxide-semiconductor S4, S5, have additional circuit element S1, S2 and the S3 for time delay, make the input voltage of metal-oxide-semiconductor S4 and metal-oxide-semiconductor S5 asynchronous).Although this mode can be eliminated short circuit current I
s, but it need increase multiple logic circuit components, and this can increase power consumption and the cost of circuit undoubtedly.And in the time having multistage complementary type circuits cascading, need before every grade of circuit, set up corresponding circuit element, and very inconvenience, in large scale integrated circuit application, the increase of power consumption and cost will be more obvious.
Utility model content
In view of this, the object of the utility model is to propose for eliminating the circuit structure of short circuit current, and this circuit has the features such as safety, stable, zero short circuit loss, energy-conservation, low cost.Its technical scheme is as follows:
For eliminating the circuit structure of short circuit current, comprising:
First order drive circuit, it is at least provided with first input end, the first output and the second output; And
The first time delay unit, it comprises the first transistor and transistor seconds, described transistor is provided with the first electrode, second electrode at its switch ways two ends and controls the third electrode of its conducting or cut-off;
The first electrode of described the first transistor is connected with the first output of described first order drive circuit, and the second electrode is connected with the second output of described first order drive circuit, and third electrode is connected with the first input end of described first order drive circuit;
The first electrode of described transistor seconds is connected with the second output of described first order drive circuit, and the second electrode is connected with the first output of described first order drive circuit, and third electrode is connected with the first input end of described first order drive circuit.
In such scheme, the first time delay unit essence is to stagger moment of switch folding in complementary type circuit by an of short duration time delay, has fundamentally eliminated and has caused the unsettled short circuit current I of circuit
s, protect the safe, stable of integrated circuit.Meanwhile, because the signal of telecommunication output of its first, second output is asynchronous, therefore the complementary type structure in subsequent conditioning circuit is played to time delay effect equally.
The technical solution of the utility model further comprises:
Described first order drive circuit comprises the 3rd transistor AND gate the 4th transistor, described the 3rd transistor, the 4th transistor are connected with the first input end of described first order drive circuit respectively, the 3rd transistor connects the first output of first order drive circuit, and the 4th transistor connects the second output of first order drive circuit.
Further, described the 3rd transistor, the 4th transistor are respectively equipped with the first electrode, second electrode at its switch ways two ends and control the third electrode of its conducting or cut-off;
Described the 3rd transistorized the first electrode is connected with power supply or higher level's circuit, and the second electrode is connected to the first output of described first order drive circuit, and third electrode is connected to the first input end of described first order drive circuit;
Described the 4th transistorized the first electrode connects signal ground, and the second electrode is connected to the second output of described first order drive circuit; Third electrode is connected to the first input end of described first order drive circuit.
Further, described first crystal, the 3rd transistor are PMOS pipe, and it comprises source electrode, drain electrode and grid, corresponding the first electrode of described source electrode, corresponding the second electrode of described drain electrode, the corresponding third electrode of described grid; Described transistor seconds, the 4th transistor are NMOS pipe, and it comprises source electrode, drain electrode and grid, corresponding the first electrode of described source electrode, corresponding the second electrode of described drain electrode, the corresponding third electrode of described grid.
Further, described circuit structure also comprises second level drive circuit, and it is provided with first input end, the second input and at least comprises the first output; The connection corresponding to the first input end of second level drive circuit of the first output of described first order drive circuit, the corresponding connection of the second input of the second output of first order drive circuit and second level drive circuit.
Further, described second level drive circuit comprises the 5th transistor AND gate the 6th transistor, and the first input end of second level drive circuit connects described in described the 5th transistor AND gate, and the second input of the 6th transistor AND gate second level drive circuit connects.
Further, described the 5th transistor, the 6th transistor are respectively equipped with the first electrode, second electrode at its switch ways two ends and control the third electrode of its conducting or cut-off;
Described the 5th transistorized the first electrode is connected with power supply or higher level's circuit, and third electrode is connected to the first input end of described second level drive circuit; Described the 6th transistorized the first electrode connects signal ground, and third electrode is connected to the second input of described second level drive circuit.
Further, described the 5th transistorized third electrode and the 6th transistorized third electrode are connected to the output of described second level drive circuit jointly; Or described the 5th transistorized third electrode is connected to the first output of the second drive circuit, the 6th transistorized third electrode is connected to the second output of the second drive circuit.
Further, described the 5th transistor is PMOS pipe, and it comprises source electrode, drain electrode and grid, corresponding the first electrode of described source electrode, corresponding the second electrode of described drain electrode, the corresponding third electrode of described grid; Described the 6th transistor is NMOS pipe, and it comprises source electrode, drain electrode and grid, corresponding the first electrode of described source electrode, corresponding the second electrode of described drain electrode, the corresponding third electrode of described grid.
Further, described circuit structure is also provided with the second time delay unit, and described first order drive circuit is provided with the second input;
Described the second time delay unit, it comprises the 7th transistor AND gate the 8th transistor, described transistor is provided with the first electrode, second electrode at its switch ways two ends and controls the third electrode of its conducting or cut-off;
Described the 7th transistorized the first electrode is connected with the first output of described first order drive circuit, and the second electrode is connected with the second output of described first order drive circuit, and third electrode is connected with the second input of described first order drive circuit;
Described the 8th transistorized the first electrode is connected with the second output of described first order drive circuit, and the second electrode is connected with the first output of described first order drive circuit, and third electrode is connected with the second input of described first order drive circuit.
Advantage of the present utility model and beneficial effect are:
1, cause the unsettled short circuit current I of circuit owing to fundamentally having eliminated
s, the power consumption of circuit and caloric value are greatly reduced, both protect the safe, stable of integrated circuit, play again obvious energy-saving effect.
2, utilize very dexterously nonsynchronous Voltage-output, in the moment of switch folding in the complementary type circuit of the subsequent cascaded that staggers, play and eliminated the effect that causes the unsettled short circuit current of circuit; Exempt simultaneously power consumption that logic circuit component causes and the increase of cost have been set.
4, circuit structure of the present utility model has been eliminated short circuit current I
simpact, the response speed of integrated circuit system signal is accelerated effectively.
5, circuit structure of the present utility model have simple in structure, volume is little, cost and low in energy consumption, improve the advantages such as standard cell circuit stability and response speed, be applicable to being widely used of large scale integrated circuit, especially show important for the innovation of standard cell lib.
Brief description of the drawings
Fig. 1 is the structural representation of complementary type drive circuit.
Fig. 2 is the structural representation of logical “and” circuit.
Fig. 3 is that the input voltage of Fig. 1 circuit structure contrasts schematic diagram with short circuit current.
Fig. 4 is the improvement structural representation of complementary type circuit.
Fig. 5 is electrical block diagram one of the present utility model.
Fig. 6 is the complementary type drive circuit schematic diagram that adopts the utility model circuit structure.
Fig. 7 is electrical block diagram two of the present utility model.
Fig. 8 is the logical “and” circuit schematic diagram that adopts the utility model circuit structure.
Fig. 9 is the input \ output voltage contrast schematic diagram of Fig. 5 circuit structure.
Embodiment
As follows by reference to the accompanying drawings, the technical solution of the utility model is described.
As shown in Figure 5, for eliminating the circuit structure of short circuit current, comprise first order drive circuit 1, second level drive circuit 2 and the first time delay unit 3;
Described first order drive circuit 1, is provided with first input end 101, the first output 103 and the second output 104;
Described second level drive circuit 2, is provided with first input end, the second input and the first output 201; The corresponding connection of first input end of the first output 101 of described first order drive circuit and second level drive circuit, the corresponding connection of the second input of the second output 103 of first order drive circuit and second level drive circuit;
Described the first time delay unit 3, comprises the first transistor 31 of pmos type and the transistor seconds 32 of nmos type.
The source electrode of described the first transistor 31 is connected with the first output 103 of described first order drive circuit 1, and drain electrode is connected with the second output 104 of described first order drive circuit 1, and grid is connected with the first input end 101 of described first order drive circuit 1;
The source electrode of described transistor seconds 32 is connected with the second output 104 of described first order drive circuit 1, and drain electrode is connected with the first output 103 of described first order drive circuit 1, and grid is connected with the first input end 101 of described first order drive circuit 1.
As shown in Figure 6, the first embodiment of the present utility model:
Described first order drive circuit 1 comprises the 3rd transistor 11 of pmos type and the 4th transistor 12 of nmos type, and the source electrode of described the 3rd transistor 11 is connected with power vd D, and drain electrode is connected to the first output 103 of described first order drive circuit 1; The source electrode of described the 4th transistor 12 meets signal ground GND, and drain electrode is connected to the second output 104 of described first order drive circuit 1; The grid of the grid of described the 3rd transistor and the 4th transistor 12 is connected to the first input end 101 of described first order drive circuit 1 jointly.
Described second level drive circuit 2 comprises the 5th transistor 21 of pmos type and the 6th transistor 22 of nmos type, the source electrode of described the 5th transistor 21 is connected with power vd D, and grid is connected to the first input end (being the first output 103 of first order drive circuit 1) of described second level drive circuit 2; The source electrode of described the 6th transistor 22 meets signal ground GND, and grid is connected to second input (being the second output 104 of first order drive circuit 1) of described second level drive circuit 2.
Described the first time delay unit 3, comprises the first transistor 31 of pmos type and the transistor seconds 32 of nmos type.
The source electrode of described the first transistor 31 is connected with the first output 103 of described first order drive circuit 1, and drain electrode is connected with the second output 104 of described first order drive circuit 1, and grid is connected with the first input end 101 of described first order drive circuit 1;
The source electrode of described transistor seconds 32 is connected with the second output 104 of described first order drive circuit 1, and drain electrode is connected with the first output 103 of described first order drive circuit 1, and grid is connected with the first input end 101 of described first order drive circuit 1.
As shown in Figure 7, on the circuit structure basis of Fig. 5, described circuit structure is also provided with the second time delay unit 4, and described first order drive circuit 1 is provided with the second input 102;
Described the second time delay unit 4, it comprises the 7th transistor 41 and the 8th transistor 42, described transistor is provided with the first electrode, second electrode at its switch ways two ends and controls the third electrode of its conducting or cut-off;
The first electrode of described the 7th transistor 41 and the first output of described first order drive circuit 1 connect 103 and connect, the second electrode is connected with the second output 104 of described first order drive circuit 1, and third electrode is connected 102 with the second input of described first order drive circuit 1;
The first electrode of described the 8th transistor 42 is connected with the second output 104 of described first order drive circuit 1, the second electrode is connected with the first output 103 of described first order drive circuit 1, and third electrode is connected with the second input 102 of described first order drive circuit 1.
As shown in Figure 8, the second embodiment of the present utility model:
Adopt the logical “and” circuit schematic diagram of the utility model circuit structure, it comprises the first order drive circuit being made up of transistor 81,82,83 and 84, the second level drive circuit being formed by transistor 91 and 92, the the first time delay unit being formed by transistor 61 and 62, and the second time delay unit being formed by transistor 71 and 72;
Described first order drive circuit is provided with first input end 101, the second input 102, the first output 103 and the second output 104; Described the first time delay unit, the second time delay unit are located between first output 103 and the second output 104 of first order drive circuit.
Described the first time delay unit, comprises the first transistor 61 of pmos type and the transistor seconds 62 of nmos type.
The source electrode of described the first transistor 61 is connected with the first output 103 of described first order drive circuit, and drain electrode is connected with the second output 104 of described first order drive circuit, and grid is connected with the first input end 101 of described first order drive circuit;
The source electrode of described transistor seconds 62 is connected with the second output 104 of described first order drive circuit, and drain electrode is connected with the first output 103 of described first order drive circuit, and grid is connected with the first input end 101 of described first order drive circuit.
Described the second time delay unit, comprises the 7th transistor 71 of pmos type and the transistor seconds 72 of nmos type.
The source electrode of described the first transistor 71 is connected with the first output 103 of described first order drive circuit, and drain electrode is connected with the second output 104 of described first order drive circuit, and grid is connected with the second input 102 of described first order drive circuit;
The source electrode of described transistor seconds 72 is connected with the second output 104 of described first order drive circuit, and drain electrode is connected with the first output 103 of described first order drive circuit, and grid is connected with the second input 102 of described first order drive circuit.
After enforcement, transistor 91 and 92 opening and closing movements are asynchronous, can not produce short circuit current.
As shown in Figure 9, due to the effect of the first time delay unit, as input voltage V
101time T1 occur when saltus step, the voltage V of the second output
104saltus step simultaneously drags down, and the voltage V of the first output
103just dragged down at moment T2; As input voltage V
101in the time there is saltus step in moment T3, the voltage V of the first output
103saltus step is simultaneously drawn high, and the voltage V of the second output
104just drawn high at moment T4.By the of short duration time delay in such scheme, make transistorized switching manipulation asynchronous, then just can there is not the situation of conducting simultaneously, fundamentally eliminate short circuit current.
Above-mentioned preferred implementation should be considered as illustrating of the utility model execution mode, and all technology deductions that duplicates, is similar to or make based on this with the utility model scheme, replacement, improvement etc., all should be considered as protection range of the present utility model.
Claims (10)
1. for eliminating a circuit structure for short circuit current, it is characterized in that: at least comprise
First order drive circuit, it is at least provided with first input end, the first output and the second output; And
The first time delay unit, it comprises the first transistor and transistor seconds, described transistor is provided with the first electrode, second electrode at its switch ways two ends and controls the third electrode of its conducting or cut-off;
The first electrode of described the first transistor is connected with the first output of described first order drive circuit, and the second electrode is connected with the second output of described first order drive circuit, and third electrode is connected with the first input end of described first order drive circuit;
The first electrode of described transistor seconds is connected with the second output of described first order drive circuit, and the second electrode is connected with the first output of described first order drive circuit, and third electrode is connected with the first input end of described first order drive circuit.
2. according to claim 1 for eliminating the circuit structure of short circuit current, it is characterized in that: described first order drive circuit comprises the 3rd transistor AND gate the 4th transistor, described the 3rd transistor, the 4th transistor are connected with the first input end of described first order drive circuit respectively, the 3rd transistor connects the first output of first order drive circuit, and the 4th transistor connects the second output of first order drive circuit.
3. according to claim 2 for eliminating the circuit structure of short circuit current, it is characterized in that: described the 3rd transistor, the 4th transistor are respectively equipped with the first electrode, second electrode at its switch ways two ends and control the third electrode of its conducting or cut-off;
Described the 3rd transistorized the first electrode is connected with power supply or higher level's circuit, and the second electrode is connected to the first output of described first order drive circuit, and third electrode is connected to the first input end of described first order drive circuit;
Described the 4th transistorized the first electrode connects signal ground, and the second electrode is connected to the second output of described first order drive circuit; Third electrode is connected to the first input end of described first order drive circuit.
4. according to claim 3 for eliminating the circuit structure of short circuit current, it is characterized in that: described first crystal, the 3rd transistor are PMOS pipe, it comprises source electrode, drain electrode and grid, corresponding the first electrode of described source electrode, corresponding the second electrode of described drain electrode, the corresponding third electrode of described grid; Described transistor seconds, the 4th transistor are NMOS pipe, and it comprises source electrode, drain electrode and grid, corresponding the first electrode of described source electrode, corresponding the second electrode of described drain electrode, the corresponding third electrode of described grid.
According to described in claim 3 or 4 for eliminating the circuit structure of short circuit current, it is characterized in that: also comprise second level drive circuit, it is provided with first input end, the second input and at least comprises the first output; The connection corresponding to the first input end of second level drive circuit of the first output of described first order drive circuit, the corresponding connection of the second input of the second output of first order drive circuit and second level drive circuit.
6. according to claim 5 for eliminating the circuit structure of short circuit current, it is characterized in that: described second level drive circuit comprises the 5th transistor AND gate the 6th transistor, described in described the 5th transistor AND gate, the first input end of second level drive circuit connects, and the second input of the 6th transistor AND gate second level drive circuit connects.
7. according to claim 6 for eliminating the circuit structure of short circuit current, it is characterized in that: described the 5th transistor, the 6th transistor are respectively equipped with the first electrode, second electrode at its switch ways two ends and control the third electrode of its conducting or cut-off;
Described the 5th transistorized the first electrode is connected with power supply or higher level's circuit, and third electrode is connected to the first input end of described second level drive circuit; Described the 6th transistorized the first electrode connects signal ground, and third electrode is connected to the second input of described second level drive circuit.
8. according to claim 7 for eliminating the circuit structure of short circuit current, it is characterized in that: described the 5th transistorized third electrode and the 6th transistorized third electrode are connected to the output of described second level drive circuit jointly; Or described the 5th transistorized third electrode is connected to the first output of the second drive circuit, the 6th transistorized third electrode is connected to the second output of the second drive circuit.
9. according to claim 8 for eliminating the circuit structure of short circuit current, it is characterized in that: described the 5th transistor is PMOS pipe, and it comprises source electrode, drain electrode and grid corresponding the first electrode of described source electrode, corresponding the second electrode of described drain electrode, the corresponding third electrode of described grid; Described the 6th transistor is NMOS pipe, and it comprises source electrode, drain electrode and grid, corresponding the first electrode of described source electrode, corresponding the second electrode of described drain electrode, the corresponding third electrode of described grid.
10. according to claim 1 for eliminating the circuit structure of short circuit current, it is characterized in that: be also provided with the second time delay unit, described first order drive circuit is provided with the second input;
Described the second time delay unit, it comprises the 7th transistor AND gate the 8th transistor, described transistor is provided with the first electrode, second electrode at its switch ways two ends and controls the third electrode of its conducting or cut-off;
Described the 7th transistorized the first electrode is connected with the first output of described first order drive circuit, and the second electrode is connected with the second output of described first order drive circuit, and third electrode is connected with the second input of described first order drive circuit;
Described the 8th transistorized the first electrode is connected with the second output of described first order drive circuit, and the second electrode is connected with the first output of described first order drive circuit, and third electrode is connected with the second input of described first order drive circuit.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420078904.1U CN203788266U (en) | 2014-02-24 | 2014-02-24 | Circuit structure used for eliminating short-circuit currents |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201420078904.1U CN203788266U (en) | 2014-02-24 | 2014-02-24 | Circuit structure used for eliminating short-circuit currents |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103795396A (en) * | 2014-02-24 | 2014-05-14 | 中山芯达电子科技有限公司 | Circuit structure for eliminating short circuit currents |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103795396A (en) * | 2014-02-24 | 2014-05-14 | 中山芯达电子科技有限公司 | Circuit structure for eliminating short circuit currents |
| CN103795396B (en) * | 2014-02-24 | 2017-01-11 | 中山芯达电子科技有限公司 | Circuit structure for eliminating short circuit currents |
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Granted publication date: 20140820 Termination date: 20170224 |
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