CN111030669B - RS latch, RS trigger and controller - Google Patents

RS latch, RS trigger and controller Download PDF

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Publication number
CN111030669B
CN111030669B CN201911398425.1A CN201911398425A CN111030669B CN 111030669 B CN111030669 B CN 111030669B CN 201911398425 A CN201911398425 A CN 201911398425A CN 111030669 B CN111030669 B CN 111030669B
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gate
signal
input
pin
input end
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CN111030669A (en
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曹珂杰
於俊
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Shanghai Kostal Huayang Automotive Electric Co Ltd
Kostal Shanghai Mechatronic Co Ltd
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Shanghai Kostal Huayang Automotive Electric Co Ltd
Kostal Shanghai Mechatronic Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/0033—Radiation hardening
    • H03K19/00338—In field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

The application discloses RS latch, trigger and controller includes: the RS latch body comprises an S input end and an R input end; and when the first signal used for being connected with the S input end and the second signal used for being connected with the R input end are both 1, the combination logic circuit converts the first signal and/or the second signal into 0 and correspondingly inputs the converted signals to the S input end and/or the R input end. According to the technical scheme, the situation that S=1 and R=1 in the RS latch body does not exist any more through the combination logic circuit connected with the RS latch body, and the S=0, R=1 or S=1, R=0 or S=0 and R=0 are converted correspondingly, so that the S=1, R=1 can be converted into the S=0 and R=0, and a certain and stable state can be output correspondingly, and the service performance of the RS latch is improved.

Description

RS latch, RS trigger and controller
Technical Field
The present disclosure relates to the field of latches, and more particularly, to an RS latch, an RS flip-flop, and a controller.
Background
An RS (Reset-Set) latch may be used to counter the jitter of the switch, which is a two-input, two-output circuit, and may be implemented in the form of a nor gate, and referring specifically to fig. 1, which illustrates an RS latch formed in the form of a nor gate as one of the prior art.
As can be seen from fig. 1, in the conventional RS latch, when the input ends are changed from s=1 and r=1 to s=0 and r=0, the two input ends S and R cannot be changed to 0 at the same time due to the asynchronous signals, so after all the two input ends S and R are changed to 0, the output ends Q and QN are in an uncertain state, that is, q=1 and qn=0 or q=0 and qn=1 cannot be determined, and the two situations can occur at the output ends randomly.
In summary, how to enable the output to be in a certain and stable state when the input is changed from s=1, r=1 to s=0, r=0 is a technical problem to be solved by those skilled in the art.
Disclosure of Invention
In view of this, it is an object of the present application to provide an RS latch, an RS flip-flop and a controller for enabling a certain and stable state of the output to occur when the input is changed from s=1, r=1 to s=0, r=0.
In order to achieve the above object, the present application provides the following technical solutions:
an RS latch comprising:
the RS latch comprises an RS latch body, a first switch and a second switch, wherein the RS latch body comprises an S input end and an R input end;
and the combination logic circuit is connected with the RS latch body, converts the first signal and/or the second signal into 0 when the first signal used for being connected with the S input end and the second signal used for being connected with the R input end are both 1, and correspondingly inputs the converted signals to the S input end and/or the R input end.
Preferably, when the combinational logic circuit is connected to the S input terminal or the R input terminal, if the first signal and the second signal are not equal to 1, the combinational logic circuit keeps the signal corresponding to the input terminal connected to the combinational logic circuit in the original state, and inputs the signal kept in the original state to the input terminal connected to the combinational logic circuit;
correspondingly, the other input end in the RS latch body directly receives a signal for accessing the RS latch body.
Preferably, when the combinational logic circuit is connected to the S input terminal and the R input terminal, if the first signal and the second signal are not equal to 1, the combinational logic circuit maintains the original states of the first signal and the second signal, and correspondingly inputs the first signal which passes through the combinational logic circuit and is maintained in the original state to the S input terminal, and correspondingly inputs the second signal which passes through the combinational logic circuit and is maintained in the original state to the R input terminal.
Preferably, the combinational logic circuit comprises a first pin for receiving the first signal, a second pin for receiving the second signal, a first NOT gate connected with the first pin, a second NOT gate connected with the second pin, a first AND gate connected with the first NOT gate and the second NOT gate, a third NOT gate connected with the output end of the first AND gate, a first gating device with a 0 pin connected with the output end of the first AND gate through the third NOT gate and a 1 pin input signal of 0, a second gating device with a 0 pin connected with the output end of the first gating device and a 1 pin input signal of 1, a second output end connected with the output end of the second gating device and a third NOT gate connected with the second pin, a second AND gate connected with the first pin and a second pin through the fourth NOT gate, a fifth gating device connected with the output end of the first pin through the third NOT gate, a fifth gating device connected with the output end of the third AND gate and a third pin connected with the output end of the third AND gate through the third pin, a third gating device connected with the output end of the third AND gate is connected with the third pin and the output end of the third gating device is 0;
the output end of the second AND gate is also connected with the control pin of the first gating device, and the output end of the third AND gate is connected with the control pin of the second gating device and the control pin of the third gating device.
Preferably, the RS latch body further includes a first nor gate having a first input terminal connected to the S input terminal, and a second nor gate having a first input terminal connected to the R input terminal;
the output end of the first nor gate is connected with the second input end of the second nor gate and the QN output end of the RS latch body, and the output end of the second nor gate is connected with the second input end of the first nor gate and the Q output end of the RS latch body.
Preferably, the RS latch body further includes a first nand gate having a first input terminal connected to the S input terminal, and a second nand gate having a first input terminal connected to the R input terminal;
the output end of the first NAND gate is connected with the second input end of the second NAND gate and the Q output end of the RS latch body, and the output end of the second NAND gate is connected with the second input end of the first NAND gate and the QN output end of the RS latch body.
An RS flip-flop comprising:
the RS trigger comprises an RS trigger body, a control circuit and a control circuit, wherein the RS trigger body comprises an S input end and an R input end;
and the combination logic circuit is connected with the RS trigger body, converts the first signal and/or the second signal into 0 when the first signal used for being connected with the S input end and the second signal used for being connected with the R input end are both 1, and correspondingly inputs the converted signals to the S input end and/or the R input end.
A controller comprising an RS latch as claimed in any one of the preceding claims or an RS flip-flop as claimed in the preceding claims.
The application provides an RS latch, an RS trigger and a controller, wherein the RS latch comprises: the RS latch body comprises an S input end and an R input end; and when the first signal used for being connected with the S input end and the second signal used for being connected with the R input end are both 1, the combination logic circuit converts the first signal and/or the second signal into 0 and correspondingly inputs the converted signals to the S input end and/or the R input end.
According to the technical scheme, the combination logic circuit connected with the RS latch body is arranged, when the first signal and the second signal are both 1, the first signal and/or the second signal are converted into 0 through the combination logic circuit, and the converted signals are correspondingly input to the S input end and/or the R input end, so that the condition that S=1 and R=1 in the RS latch body is not existed any more, and the corresponding conversion is S=0, R=1 or S=1, R=0 or S=0 and R=0, so that the S=1, R=1 and S=0 can be correspondingly output to a determined and stable state when the S=1, R=0 is converted, and the service performance of the RS latch is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings may be obtained according to the provided drawings without inventive effort to a person skilled in the art.
FIG. 1 is a diagram of an RS-latch of the prior art in the form of a NOR gate;
FIG. 2 is a schematic diagram of an RS-latch according to an embodiment of the disclosure;
FIG. 3 is a schematic diagram of a combinational logic circuit according to an embodiment of the present disclosure;
fig. 4 is a simulation result diagram corresponding to fig. 3 provided in the embodiment of the present application;
fig. 5 is a schematic structural diagram of an RS flip-flop according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
Referring to fig. 2, which is a schematic structural diagram of an RS latch provided in an embodiment of the present application, the RS latch provided in the embodiment of the present application may include:
RS latch body 1, RS latch body 1 may include an S input and an R input;
and the combination logic circuit 2 is connected with the RS latch body 1, and when the first signal used for being connected with the S input end and the second signal used for being connected with the R input end are both 1, the combination logic circuit 2 converts the first signal and/or the second signal into 0 and correspondingly inputs the converted signals to the S input end and/or the R input end.
The RS latch provided by the present application may include an RS latch body 1, and a combinational logic circuit 2 connected to the RS latch body 1, where the RS latch body 1 includes an S input end and an R input end, a Q output end and a QN output end, and the output of the RS latch body 1 is the output of the RS latch provided by the present application, that is, the output of the RS latch body 1 is used as the output of the RS latch.
The combinational logic circuit 2 comprises in particular two inputs, one of which receives a first signal for accessing the S input in the RS latch body 1 and the other of which receives a second signal for accessing the R input in the RS latch body 1, and may comprise in particular one or two outputs, which may be connected to the S input or the R input in the RS latch body 1 when it comprises one output, and may be connected to the S input and the R input in the RS latch body 1 respectively through two outputs when it comprises two outputs.
When both the first signal for accessing the S input and the second signal for accessing the R input are 1, then the combinational logic circuit 2 may convert the first signal and/or the second signal received through its own input into 0 and input the converted signal to the S input and/or the R input correspondingly, that is, only the first signal is converted into 0 and the converted first signal is input to the S input, so that the RS latch body 1 may be converted into a state of s=0 and r=1 by the state of s=1 and r=1 to be input (this case corresponds to the combinational logic circuit 2 having one output and the output being connected to the S input), or only the second signal is converted into 0 and the converted second signal is input to the R input, so that the RS latch body 1 may be converted into a state of s=1 and r=0 by the state of s=1 and r=1 to be input originally (this case corresponds to the combinational logic circuit 2 having one output and the output being connected to the output) or the combined logic circuit 2 having the other one output and the two output to the s=1 and the r=1 to the other output.
Since the RS latch body 1 outputs the signals q=0, qn=1, q=1, qn=0, or the state of holding the previous state in the three states of s=0, r=1, s=1, r=0, or s=0, r=0, the RS latch can output the determined and stable state when the input signal is about to be converted from all 1S to all 0S, and no random state is outputted any more, so that a worker can accurately learn the stable signal state outputted by the RS latch, and the usability and reliability of the RS latch can be improved.
According to the technical scheme, when the first signal and the second signal are both 1, the first signal and/or the second signal are converted into 0 through the combinational logic circuit, and the converted signals are correspondingly input to the S input end and/or the R input end, so that the condition of S=1 and R=1 in the RS latch body is not existed, but the corresponding conversion is S=0, R=1 or S=1, R=0 or S=0 and R=0, so that the state can be correspondingly output when the S=1 and R=1 are converted into S=0 and R=0, and the service performance of the RS latch is improved.
When the combinational logic circuit 2 is connected with the S input end or the R input end, if the first signal and the second signal are not equal to 1, the combinational logic circuit 2 keeps the signal corresponding to the input end connected with the combinational logic circuit 2 in the original state, and inputs the signal kept in the original state to the input end connected with the combinational logic circuit 2;
correspondingly, the other input in the RS latch body 1 directly receives a signal for accessing itself.
When the combinational logic circuit 2 is connected to the S input terminal or the R input terminal (at this time, the combinational logic circuit 2 includes only one output terminal), if the first signal and the second signal are not both 1, that is, the state of the RS latch body 1 is not to be input with all 1, but one of the other three states (that is, the first signal is 0, the second signal is 1, or the first signal is 0, or the second signal is 0) is to be input into the combinational logic circuit 2, the combinational logic circuit 2 may keep the signal corresponding to the input terminal connected thereto in the case that the first signal and the second signal are not both 1, and input the signal corresponding to the input terminal connected thereto into the combinational logic circuit 2 into the input terminal of the RS latch body 1 connected thereto, that is, if the first signal and the second signal are not both 1, the combinational logic circuit 2 may keep the original state of the signal corresponding to the input terminal connected thereto, and input the signal corresponding to the input terminal connected thereto into the combinational logic circuit 2 in the corresponding state into the input terminal connected thereto. Meanwhile, the other input end in the RS latch body 1 (i.e. the input end connected with the combinational logic circuit 2 except the input end in the RS latch body 1) directly receives the signal for accessing itself, so that the S input end and the R input end in the RS latch body 1 can correspondingly receive the first signal and the second signal which keep the original states.
Taking the example that the combinational logic circuit 2 is connected with the S input end and takes the first signal as 0 and the second signal as 1, in this state, the combinational logic circuit 2 keeps the first signal corresponding to the S input end connected with the combinational logic circuit as the original state, that is, keeps the first signal as 0, and inputs the first signal with 0 to the S input end of the RS latch body 1, meanwhile, the R input end of the RS latch body 1 can directly receive the signal for accessing itself, that is, the R input end can directly receive the second signal, so that the input end of the RS latch body 1 is in the state of s=0 and r=1.
According to the RS latch provided by the embodiment of the application, when the combination logic circuit 2 is connected with the S input end and the R input end, if the first signal and the second signal are not equal to 1, the combination logic circuit 2 keeps the original states of the first signal and the second signal, the first signal which passes through the combination logic circuit 2 and keeps the original states is correspondingly input to the S input end, and the second signal which passes through the combination logic circuit 2 and keeps the original states is correspondingly input to the R input end.
When the combinational logic circuit 2 is connected to the S input terminal and the R input terminal (at this time, the combinational logic circuit 2 includes two output terminals), if the first signal and the second signal are not equal to 1, the combinational logic circuit 2 can keep the original states of the first signal and the second signal, and the first signal which passes through the combinational logic circuit 2 and is kept in the original states is correspondingly input to the S input terminal, and the second signal which passes through the combinational logic circuit 2 and is kept in the original states is correspondingly input to the R input terminal, that is, under the condition that the first signal and the second signal are not equal to 1, the combinational logic circuit 2 does not convert the first signal to be connected to the S input terminal and the second signal to be connected to the R input terminal, so that the S input terminal and the R input terminal in the RS latch body 1 can correspondingly receive the first signal and the second signal which are kept in the original states.
Referring to fig. 3, a schematic diagram of a combination logic circuit according to an embodiment of the present application is shown. The RS latch provided IN this embodiment of the present application may include a first pin IN1 for receiving a first signal, a second pin IN2 for receiving a second signal, a first not gate 21 connected to the first pin IN1, a second not gate 22 connected to the second pin IN2, a first and a second not gate 23 connected to the first not gate 21 and the second not gate 22, a third not gate 24 connected to an output terminal of the first and gate 23, a first gate 25 with a 0 pin connected to an output terminal of the first and gate 23 through the third not gate 24 and a 1 pin input signal being 0, a second gate 26 with a 0 pin connected to an output terminal of the first gate 25 and a 1 pin input signal being 1, a second output terminal OUT2 connected to an output terminal of the second gate 26 and a R input terminal, a fourth not gate 27 connected to the second pin IN1 and a second pin IN2 through the fourth not gate 27, a second and gate 28 connected to the output terminal of the second pin IN2 through the fourth not gate 27, a fifth gate 29 connected to the first and a third gate 2, and a fifth gate 29 connected to the output terminal of the first and a third gate 2 connected to the first gate 2 and a fifth gate 29 connected to an output terminal of the first gate 2 and a third gate 2 through the third gate 29 connected to the output terminal of the first gate 2 and a third gate 21 connected to the first gate 2 and a third gate 2;
the output end of the second and gate 28 is also connected to the control pin of the first gate 25, and the output end of the third and gate 210 is connected to the control pin of the second gate 26 and the control pin of the third gate 211.
The combinational logic circuit 2 having two inputs and two outputs and capable of converting the first signal 1 and the second signal 1 into s=0, r=1 of the RS latch body 1 may include a first pin IN1, a second pin IN2, a first not gate 21, a second not gate 22, a first and gate 23, a third not gate 24, a first gate 25, a second gate 26, a second output OUT2, a fourth not gate 27, a second and gate 28, a fifth not gate 29, a third and gate 210, a third gate 211, a first output OUT1, wherein:
the first pin IN1 is used for receiving a first signal (i.e. for receiving a signal for accessing an S input end), the second pin IN2 is used for receiving a second signal (i.e. for receiving a signal for accessing an R input end), one input end of the first and gate 23 is connected with the first pin IN1 through the first not gate 21, the other input end of the first gate is connected with the second pin IN2 through the second not gate 22, the 0 pin of the first gate is connected with the first and gate 23 through the third not gate 24, the 1 pin input signal of the first gate 25 is 0, the output end of the first gate 25 is connected with the 0 pin of the second gate 26, the 1 pin input signal of the second gate 26 is 1, the output end of the second gate 26 is connected with the second output end OUT2 of the combinational logic circuit 2, the second output end OUT2 of the combinational logic circuit 2 is used for being connected with the R input end of the RS body 1, the other input end of the second and gate 28 is connected with the first pin IN1 through the fourth not gate 27, the other input end of the first gate is connected with the second pin IN2, the output end of the first gate 25 is connected with the third gate 211, the output end of the second gate 28 is connected with the third gate 2, the output end of the first gate 2 is connected with the third gate 2, the third gate 2 is directly, the output end of the first gate 2 is connected with the third gate 2 input end of the first gate 2 and the first gate 2 is connected with the third gate 2 input end of the first gate 2.
The combination logic circuit 2 not only can convert the first signal and the second signal from all 1S to 0 at the first output end OUT1 and 1 at the second output end OUT2, and output 0 output by the first output end OUT1 to the S input end of the RS latch, but also can output 1 output by the second output end OUT2 to the R input end of the RS latch, and can also keep the original states of the first signal and the second signal under the condition that the first signal and the second signal are not all 1. Referring to fig. 4, a simulation result diagram corresponding to fig. 3 is shown, where when signals received by the first pin IN1 and the second pin IN2 are not all 1, the first output terminal OUT1 and the second output terminal OUT2 are corresponding to the first pin IN1 and the second pin IN2 and keep consistent, and if signals received by the first pin IN1 and the second pin IN2 are all 1, the first output terminal OUT1 outputs 0, and the second output terminal OUT2 outputs 1.
In addition, the conversion of the first signal and the second signal from all 1 to the first output terminal OUT1 being 0 and the second output terminal OUT2 being 0 may be achieved by converting fig. 3, or the conversion of the first signal and the second signal from all 1 to the first output terminal OUT1 being 1 and the second output terminal OUT2 being 0 may be achieved by converting fig. 3, which will not be described herein, and the conversion of fig. 3 may be performed such that only one output terminal exists in the combinational logic circuit 2 to achieve the state in which the first signal and the second signal are converted from all 1 to their corresponding output terminals to output 0.
Of course, the above functions may be implemented by other combinational logic circuits 2 having similar functions, and the specific functions of this type of combinational logic circuit 2 are not limited in this application.
According to the RS latch provided by the embodiment of the application, the RS latch body 1 can further comprise a first NOR gate, a second NOR gate and a first input end, wherein the first NOR gate is connected with the S input end, and the second NOR gate is connected with the R input end;
the output end of the first nor gate is connected with the second input end of the second nor gate and the QN output end of the RS latch body 1, and the output end of the second nor gate is connected with the second input end of the first nor gate and the Q output end of the RS latch body 1.
The RS latch body 1 may further include a first nor gate, and a second nor gate, where a first input end of the first nor gate is connected to the S input end, a second input end of the first nor gate is connected to an output end of the second nor gate, and an output end of the first nor gate is further connected to a QN output end of the RS latch body 1; the first input end of the second nor gate is connected with the R input end, the second input end of the second nor gate is connected with the output end of the first nor gate, and the output end of the second nor gate is connected with the Q output end of the RS latch body 1.
That is, nor gates can be utilized as logic gates in the RS latch body 1 included in the RS latch of the present application to achieve certainty of the output signal of this type of RS latch.
According to the RS latch provided by the embodiment of the application, the RS latch body 1 can further comprise a first NAND gate with a first input end connected with the S input end and a second NAND gate with a first input end connected with the R input end;
the output end of the first NAND gate is connected with the second input end of the second NAND gate and the Q output end of the RS latch body 1, and the output end of the second NAND gate is connected with the second input end of the first NAND gate and the QN output end of the RS latch body 1.
The RS latch body 1 may further include a first nand gate and a second nand gate, where a first input end of the first nand gate is connected to an S input end, a second input end of the first nand gate is connected to an output end of the second nand gate, and an output end of the second nand gate is connected to a Q output end of the RS latch body 1; the first output end of the second NAND gate is connected with the R input end, the second input end of the second NAND gate is connected with the output end of the first NAND gate, and the output end of the second NAND gate is connected with the QN output end of the RS latch body 1.
That is, a nand gate can be used as a logic gate in the RS latch body 1 included in the RS latch of the present application to achieve the certainty of the output signal of this type of RS latch.
Of course, other types of logic gates may be utilized as logic gates in the RS latch body 1 included in the RS latch of the present application to achieve certainty of the output signals of the various types of RS latches.
Referring to fig. 5, which shows a schematic structural diagram of an RS flip-flop provided in an embodiment of the present application, the RS flip-flop provided in the embodiment of the present application may include:
the RS trigger body 3, the RS trigger body 3 comprises an S input end and an R input end;
and the combination logic circuit 4 is connected with the RS trigger body 3, and when the first signal used for being connected with the S input end and the second signal used for being connected with the R input end are both 1, the combination logic circuit 4 converts the first signal and/or the second signal into 0 and correspondingly inputs the converted signals to the S input end and/or the R input end.
In view of the fact that the RS flip-flop has a similar structure and function as the RS latch, there is likewise the problem that an undefined state occurs at the output when the input is changed from s=1, r=1 to s=0, r=0, for which purpose the present application provides a combinational logic circuit 4 connected to the RS flip-flop body 3 in the RS flip-flop, wherein the combinational logic circuit 4 mentioned here has the same function and structure as the combinational logic circuit 2 provided in the above-mentioned RS latch, so that when both the first signal for accessing the S input of the RS flip-flop body 3 and the second signal for accessing the R input of the RS flip-flop body 3 are 1, the first signal and/or the second signal are changed to 0 by the combinational logic circuit 4 connected to the RS flip-flop body 3, and the converted signals are correspondingly input to the S input and/or the R input of the RS flip-flop body 3, so that the situation of s=1, r=1 is no longer present in the RS flip-flop body 3, but the corresponding change to s=0, r=1, r=0, and r=0 are correspondingly changed to the state, and the RS flip-flop 3 is thus able to be determined.
The embodiment of the application also provides a controller which can comprise any one of the RS latches or the RS flip-flops.
Any one of the RS latches or the RS flip-flops can be applied to the controller, and the certainty of the output signal can be realized by any one of the RS latches or the RS flip-flops, so that the certainty and stability of the control signal of the controller can be improved, and the reliability of the operation of the controller can be improved.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements is inherent to. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. In addition, the parts of the above technical solutions provided in the embodiments of the present application, which are consistent with the implementation principles of the corresponding technical solutions in the prior art, are not described in detail, so that redundant descriptions are avoided.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (7)

1. An RS latch, comprising:
the RS latch comprises an RS latch body, a first switch and a second switch, wherein the RS latch body comprises an S input end and an R input end;
the combination logic circuit is connected with the RS latch body, converts the first signal and/or the second signal into 0 when the first signal used for being connected with the S input end and the second signal used for being connected with the R input end are both 1, and correspondingly inputs the converted signals to the S input end and/or the R input end;
the combinational logic circuit comprises a first pin for receiving the first signal, a second pin for receiving the second signal, a first NOT gate connected with the first pin, a second NOT gate connected with the second pin, a first AND gate connected with the first NOT gate and the second NOT gate, a third NOT gate connected with the output end of the first AND gate, a first gating device with a 0 pin connected with the output end of the first AND gate through the third NOT gate and with a 1 pin input signal of 0, a second gating device with a 0 pin connected with the output end of the first gating device and with a 1 pin input signal of 1, a second output end connected with the output end of the second gating device and used for being connected with the R input end, a fourth NOT gate connected with the second pin, a second AND gate connected with the first pin and with the second pin through the fourth NOT gate, a fifth NOT gate connected with the first pin through the third NOT gate, a fifth NOT gate connected with the output end of the first pin and with a third input end of the S gate connected with the third gate and with a 0 input end of the third AND gate;
the output end of the second AND gate is also connected with the control pin of the first gating device, and the output end of the third AND gate is connected with the control pin of the second gating device and the control pin of the third gating device.
2. The RS latch according to claim 1, wherein when the combinational logic circuit is connected to the S input terminal or the R input terminal, if the first signal and the second signal are not equal to 1, the combinational logic circuit keeps a signal corresponding to an input terminal connected thereto in an original state, and inputs the signal kept in the original state to the input terminal connected to the combinational logic circuit;
correspondingly, the other input end in the RS latch body directly receives a signal for accessing the RS latch body.
3. The RS latch according to claim 1, wherein when the combinational logic circuit is connected to both the S input terminal and the R input terminal, if the first signal and the second signal are not equal to 1, the combinational logic circuit maintains the original states of the first signal and the second signal, and the first signal which passes through the combinational logic circuit and is maintained in the original state is correspondingly input to the S input terminal, and the second signal which passes through the combinational logic circuit and is maintained in the original state is correspondingly input to the R input terminal.
4. The RS latch according to claim 1, wherein the RS latch body further comprises a first nor gate having a first input connected to the S input, a second nor gate having a first input connected to the R input;
the output end of the first nor gate is connected with the second input end of the second nor gate and the QN output end of the RS latch body, and the output end of the second nor gate is connected with the second input end of the first nor gate and the Q output end of the RS latch body.
5. The RS latch according to claim 1, wherein the RS latch body further comprises a first nand gate having a first input connected to the S input, and a second nand gate having a first input connected to the R input;
the output end of the first NAND gate is connected with the second input end of the second NAND gate and the Q output end of the RS latch body, and the output end of the second NAND gate is connected with the second input end of the first NAND gate and the QN output end of the RS latch body.
6. An RS flip-flop, comprising:
the RS trigger comprises an RS trigger body, a control circuit and a control circuit, wherein the RS trigger body comprises an S input end and an R input end;
the combination logic circuit is connected with the RS trigger body, converts the first signal and/or the second signal into 0 when the first signal used for being connected with the S input end and the second signal used for being connected with the R input end are both 1, and correspondingly inputs the converted signals to the S input end and/or the R input end;
the combinational logic circuit comprises a first pin for receiving the first signal, a second pin for receiving the second signal, a first NOT gate connected with the first pin, a second NOT gate connected with the second pin, a first AND gate connected with the first NOT gate and the second NOT gate, a third NOT gate connected with the output end of the first AND gate, a first gating device with a 0 pin connected with the output end of the first AND gate through the third NOT gate and with a 1 pin input signal of 0, a second gating device with a 0 pin connected with the output end of the first gating device and with a 1 pin input signal of 1, a second output end connected with the output end of the second gating device and used for being connected with the R input end, a fourth NOT gate connected with the second pin, a second AND gate connected with the first pin and with the second pin through the fourth NOT gate, a fifth NOT gate connected with the first pin through the third NOT gate, a fifth NOT gate connected with the output end of the first pin and with a third input end of the S gate connected with the third gate and with a 0 input end of the third AND gate;
the output end of the second AND gate is also connected with the control pin of the first gating device, and the output end of the third AND gate is connected with the control pin of the second gating device and the control pin of the third gating device.
7. A controller comprising an RS latch as claimed in any one of claims 1 to 5 or an RS flip-flop as claimed in claim 6.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103701450A (en) * 2013-12-25 2014-04-02 北京理工大学 Tristable RS trigger capable of supporting multiple value logic
CN108055022A (en) * 2017-12-08 2018-05-18 北京时代民芯科技有限公司 A kind of rest-set flip-flop circuit with resistant and oscillation resistant structure
CN108155892A (en) * 2017-12-26 2018-06-12 电子科技大学 A kind of RS trigger architectures for eliminating nondeterministic statement
CN109743040A (en) * 2019-01-03 2019-05-10 上海科世达-华阳汽车电器有限公司 A kind of rest-set flip-flop and controller

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103701450A (en) * 2013-12-25 2014-04-02 北京理工大学 Tristable RS trigger capable of supporting multiple value logic
CN108055022A (en) * 2017-12-08 2018-05-18 北京时代民芯科技有限公司 A kind of rest-set flip-flop circuit with resistant and oscillation resistant structure
CN108155892A (en) * 2017-12-26 2018-06-12 电子科技大学 A kind of RS trigger architectures for eliminating nondeterministic statement
CN109743040A (en) * 2019-01-03 2019-05-10 上海科世达-华阳汽车电器有限公司 A kind of rest-set flip-flop and controller

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