CN108055022B

CN108055022B - RS trigger circuit with anti-oscillation structure

Info

Publication number: CN108055022B
Application number: CN201711298921.0A
Authority: CN
Inventors: 胡春艳; 陆时进; 李阳; 刘琳; 张晓晨
Original assignee: Beijing Microelectronic Technology Institute; Mxtronics Corp
Current assignee: Beijing Microelectronic Technology Institute; Mxtronics Corp
Priority date: 2017-12-08
Filing date: 2017-12-08
Publication date: 2022-02-22
Anticipated expiration: 2037-12-08
Also published as: CN108055022A

Abstract

The invention discloses an RS trigger circuit with an anti-oscillation structure, which is provided with an anti-oscillation circuit, and when the output of the RS trigger is in an uncertain state, one output is clamped, so that the output can quickly reach a stable state. In the RS flip-flop circuit formed by the NAND gates, when the input is converted from 00 to 11 and the output is in an uncertain state, the output of one NAND gate is clamped to 1, so that the defect that the input of the RS flip-flop circuit formed by the NAND gates does not allow 00 is overcome, and the function of the RS flip-flop circuit is more complete. When the input of the RS trigger circuit formed by the NOR gates is changed from 11 to 00, the output of one NOR gate is clamped to 0 under the condition that the output is in an uncertain state, thereby overcoming the defect that the input of the RS trigger circuit formed by the NOR gates is not allowed to be 11 and further improving the function of the RS trigger circuit.

Description

RS trigger circuit with anti-oscillation structure

Technical Field

The invention relates to an RS trigger circuit with an anti-oscillation structure, and belongs to the field of digital integrated circuit design.

Background

The RS flip-flop has the functions of set, reset, and hold, and is a basic component constituting various functional blocks in the digital logic circuit.

The basic RS flip-flop realized by adopting the cross-coupled NAND gate is allowed to have three states of setting, resetting and keeping when in normal operation, and two outputs of the basic RS flip-flop are always in complementary states. When R and S are both 1, the trigger is in a holding state, and both outputs maintain the previous output value; when R is changed into 0, Qn output is forced to enter a 1 state, the complementary output end Q is changed into a 0 state because the input of the NAND gate connected with the complementary output end Q is high, and the RS trigger is reset; conversely, when S becomes 0, the Q output is forced to the 1 state, at which time the complementary output Qn becomes the 0 state due to both the nand gate inputs connected thereto being high, at which time the RS flip-flop is set. However, in the flip-flop characteristic table, when an input mode in which R and S inputs are both 0 is generally considered to be not allowed, in the input mode, Q and Qn outputs are both high level, if two input signals simultaneously become high level, the whole circuit can be regarded as a cross-coupled inverter, and because the levels of the two inverter inputs are the same and both have the same propagation delay, the same-frequency and same-phase oscillation of the RS flip-flop output will occur, and the final state of the flip-flop cannot be predicted.

When the external input signal is unconstrained, the normal RS flip-flop may cause malfunction in practical applications. For example, when applied to arbitration and token circuits, the RS flip-flop determines which of the two inputs arrives first, so that it is inevitable that the flip-flop will be in an indeterminate state in an input mode in which the R and S signals of the inputs change from 0 to 1 at the same time, resulting in a failure of the circuit function.

Specifically, in the RS flip-flop including the nand gate, when the input is changed from 00 to 11, the output may oscillate, and in the RS flip-flop including the nor gate, when the input is changed from 11 to 00, the output may oscillate.

Disclosure of Invention

The technical problem of the invention is solved: the RS trigger circuit with the anti-vibration structure overcomes the defects of a common RS trigger, eliminates the oscillation and the indefinite state caused by the RS trigger in a special input mode, and greatly improves the operation reliability of the RS trigger.

The technical scheme of the invention is as follows:

provided is an RS flip-flop circuit with an anti-oscillation structure, including: the first NAND gate, the second NAND gate and the anti-oscillation circuit; the output end of the anti-oscillation circuit is connected with the input end of the first NAND gate after being connected with the phase of the R signal or the S signal;

and when the outputs of the first NAND gate and the second NAND gate are both 0, the anti-oscillation control circuit outputs 0, otherwise, the output of the anti-oscillation control circuit is 1.

Preferably, the first nand gate and the second nand gate are three-input nand gates, the output end of the anti-oscillation circuit is connected with the first input end of the first nand gate, the second input end of the first nand gate is connected with an R signal or an S signal, and the third input end of the first nand gate is connected with the output end of the second nand gate; the first input end of the second NAND gate is connected with a high level, the second input end of the second NAND gate is connected with an R signal or an S signal which is not connected with the second input end of the first NAND gate, and the third input end of the second NAND gate is connected with the output end of the first NAND gate.

Preferably, the first nand gate and the second nand gate are two-input nand gates, the output end of the anti-oscillation circuit is connected with the first input end of the first nand gate after being connected with the R signal or the S signal phase through the AND gate, and the second input end of the first nand gate is connected with the output end of the second nand gate; the first input end of the second NAND gate is connected with the R signal or the S signal which is not connected with the AND gate, and the second input end of the second NAND gate is connected with the output end of the first NAND gate.

Preferably, the anti-oscillation circuit comprises a first inverter, a second inverter and a third nand gate;

the first inverter is used for receiving the output signal Qn of the first NAND gate, and the output end of the first inverter is connected with one input end of the third NAND gate;

the second inverter is used for receiving the output signal Q of the second NAND gate, and the output end of the second inverter is connected with the other input end of the third NAND gate;

the output end of the third NAND gate is used as the output end of the anti-oscillation circuit.

Preferably, the first nand gate and the second nand gate adopt the same structural elements.

Provided is an RS flip-flop circuit with an anti-oscillation structure, including: the circuit comprises a first NOR gate, a second NOR gate and an anti-oscillation circuit; the output end of the anti-oscillation circuit is connected with the input end of the first NOR gate after or in phase with the R signal or the S signal;

and when the outputs of the first NOR gate and the second NOR gate are both 1, the output of the anti-oscillation control circuit is 1, otherwise, the output of the anti-oscillation control circuit is 0.

Preferably, the first nor gate and the second nor gate are three-input nor gates, the output end of the anti-oscillation circuit is connected with the first input end of the first nor gate, the second input end of the first nor gate is connected with the R signal or the S signal, and the third input end of the first nor gate is connected with the output end of the second nor gate; the first input end of the second NOR gate is connected with a low level, the second input end of the second NOR gate is connected with the R signal or the S signal which is not connected with the second input end of the first NOR gate, and the third input end of the second NOR gate is connected with the output end of the first NOR gate.

Preferably, the first nor gate and the second nor gate are two-input nor gates, the output end of the anti-oscillation circuit is connected with the first input end of the first nor gate after being connected with the R signal or the S signal through the or gate, and the second input end of the first nor gate is connected with the output end of the second nor gate; the first input end of the second NOR gate is connected with the R signal or the S signal which is not connected with the OR gate, and the second input end of the second NOR gate is connected with the output end of the first NOR gate.

Preferably, the anti-oscillation circuit comprises a first nand gate and a first inverter;

the first NAND gate is used for receiving output signals of the first NOR gate and the second NOR gate, and the output end of the first NAND gate is connected with the input end of the first inverter;

the output end of the first phase inverter is used as the output end of the anti-oscillation circuit.

Preferably, the first nor gate and the second nor gate use the same structural elements.

The invention has the following advantages:

(1) the invention provides an RS trigger circuit with an anti-vibration structure, when the circuit is simultaneously raised due to input so that two output ends Q and Qn generate in-phase oscillation, the anti-vibration control feedback circuit is used for detecting an output signal and generating a feedback signal to be transmitted to the input end of a trigger, the oscillation condition of the RS trigger is damaged, the trigger is reset at the same time, the state of Q or Qn is limited when oscillation occurs, the oscillation and the indeterminate state caused under a special input mode are eliminated, and the operation reliability of the RS trigger is greatly improved.

(2) When the input of the RS flip-flop circuit formed by the NAND gates is converted from 00 to 11, the output of one NAND gate is clamped to 1 under the condition that the output is in an uncertain state, so that the defect that the input of the RS flip-flop circuit formed by the NAND gates does not allow 00 is overcome, and the function of the RS flip-flop circuit is more complete.

(3) When the input of the RS trigger circuit formed by the NOR gates is changed from 11 to 00, the output of one NOR gate is clamped to 0 under the condition that the output is in an uncertain state, thereby overcoming the defect that the input of the RS trigger circuit formed by the NOR gates is not allowed to be 11 and further improving the function of the RS trigger circuit.

Drawings

FIG. 1 is a schematic diagram of an RS flip-flop circuit with a vibration-resistant structure according to an embodiment of the present invention;

FIG. 2 is an exemplary circuit for implementing an RS flip-flop with an anti-vibration structure according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of an RS flip-flop with anti-vibration structure according to another embodiment of the present invention;

FIG. 4 is a specific circuit example of an RS trigger with an anti-vibration structure in an embodiment of the present invention;

FIG. 5 is a simulation waveform of an RS trigger circuit without adding a vibration-resistant structure;

fig. 6 is a simulation waveform of an RS flip-flop circuit with a vibration-resistant structure in an example of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, common embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

Fig. 1 shows a schematic circuit diagram of an RS flip-flop with a vibration-resistant structure in an embodiment of the present invention, including: first nand gate 100, second nand gate 200, and anti-oscillation circuit 300; the output ends of the first nand gate 100 and the second nand gate 200 are connected to the input of the anti-oscillation control circuit 300, and the output end of the anti-oscillation control circuit 300 is connected to one input end of the first nand gate 100.

A first nand gate circuit 100 for receiving an external input signal R, generating a flip-flop output signal Qn in response to a change in an external level, and connecting the flip-flop output signal Qn to an input terminal of the anti-oscillation control circuit 300 and an input terminal of the second nand gate 200;

a second nand gate circuit 200 for receiving an external input signal S, generating a trigger output signal Q, and connecting to the input terminal of the anti-oscillation control circuit 300 and the input terminal of the first nand gate circuit 100;

in this embodiment, one of the inputs of the second nand gate 200 is connected to a high level, and the R terminal of the first nand gate 100 and the S input of the second nand gate can receive any variable input level. In the normal input mode, the RS flip-flop normally works in the holding, set, and reset states, and in the special input mode, i.e., when R and S are simultaneously inverted from the 0 state to the 1 state, the anti-oscillation structure 300 can play a role in suppressing the output oscillation, forcing the output to be in the reset state.

And an anti-oscillation control circuit 300 for processing the outputs of first nand gate 100 and second nand gate 200 to obtain an anti-oscillation feedback signal C to control first nand gate 100.

In the present embodiment, the anti-oscillation circuit 300 monitors the states of the output signals Q and Qn, and outputs the low level of csl for controlling the first nand gate 100 with a certain delay once both become the 0 state. Specifically, the method comprises the following steps:

referring to fig. 2, which shows an embodiment of the anti-oscillation RS flip-flop of the present invention, the first nand gate 100 includes: a first three-input NAND gate (NAND3) circuit 101; second nand gate circuit 200 includes: a second three-input NAND gate (NAND3) circuit 201.

The first three-input NAND gate (NAND3) circuit 101 is used for receiving an external input signal R, and the output feedback signal Q of the second NAND3 circuit 201 and the output signal C of the anti-oscillation control circuit. Processing the R signal, the feedback signal and the control signal to obtain a Qn signal and outputting the Qn signal;

the second three-input NAND gate (NAND3) circuit 201 is used for receiving an external input signal S and outputting a feedback signal Qn of the first NAND3 circuit 101. Processing the S signal and the feedback signal to obtain a Q signal and outputting the Q signal;

the anti-oscillation control circuit structure 300 includes: a first inverter 301, a second inverter 302, and a first two-input NAND gate (NAND2) circuit 303;

a first inverter 301, configured to receive the output signal Qn of the first NAND3 gate 101, and process the Qn signal to obtain a Qn1 signal; a second inverter 302, configured to receive the output signal Q of the second NAND3 gate 201, and process the Q signal to obtain a Q1 signal; a first NAND2 module 303, configured to connect the output signal Qn1 of the first inverter 301 and the output signal Q1 of the second inverter 302, and perform an and operation on the two signals to obtain a C signal, and output the C signal;

wherein, the output signal C of the first NAND2 circuit module is the output signal of the anti-oscillation control circuit, and is used for controlling one input end of the first NAND gate circuit.

It should be noted that, when the flip-flop operates in the normal mode, i.e., the set, reset or hold state, the anti-oscillation circuit structure 300 outputs two complementary signals, and the logic value of the output signal C of the anti-oscillation circuit is always 1, so that the whole circuit can be simplified into the cross-coupled NAND basic flip-flop structure formed by the first NAND3 gate 101 and the second NAND3 gate 201, one of which is 1. When R and S are simultaneously inverted from 0 to 1, and assuming that two NAND3 gates have the same propagation delay, Q and Qn are simultaneously inverted from the initial 1 level to 0 level, if there is no anti-oscillation circuit structure 300 (the output is 1 by default), the whole circuit can be simplified into an oscillation ring formed by two inverters, the RS flip-flop falls into the oscillation state shown in FIG. 5, and the outputs Q and Qn are cyclically inverted with the same frequency and phase.

The anti-oscillation circuit structure 300 has an effect of rapidly suppressing oscillation, and it should be noted that the propagation delay of the anti-oscillation circuit needs to be set as required because the input signals of the first NAND3 gate 101 and the second NAND3 gate 201 are signals with the same frequency and the same phase, and in order to break this oscillation condition, the propagation delay of the anti-oscillation circuit is required not to be an integer multiple of the oscillation period of the RS flip-flop, so as to avoid that the anti-oscillation control signal C is with the same frequency and the same phase as Q and Qn. Optimally, the oscillation feedback propagation delay is one half of the oscillation period. After two outputs Q and Qn are simultaneously changed into 0, when the output low level of the anti-vibration circuit is transmitted to the input end of the first NAND3 gate, if Q and Qn are just 1 level, then the Qn output of the RS trigger maintains 1 level, and Q is changed into 0 level, thereby resetting the trigger. Fig. 6 shows a simulated waveform in a special input mode after the anti-oscillation structure is added, and it can be seen from fig. 6 that when the input is changed from 00 to 11, the output can quickly reach a stable state, and the anti-oscillation structure is proved to effectively realize the function of suppressing the circuit oscillation.

As a supplementary embodiment, fig. 3 shows a schematic diagram of another anti-oscillation RS flip-flop, comprising: a first nor gate circuit 400, a second nor gate circuit 500, and an anti-oscillation circuit 600; wherein, the output ends of the first nor gate circuit 400 and the second nor gate circuit 500 are connected to the input of the anti-oscillation control circuit 600, and the output end of the anti-oscillation control circuit 600 is connected to one input end of the second nor gate 500.

A first nor gate circuit 400 for receiving an external input signal S, generating a trigger output signal Q in response to a change in an external level, and connecting to an input terminal of the anti-oscillation control circuit 600 and an input terminal of the second nor gate 500 circuit;

a second nor gate circuit 500 for receiving an external input signal R, generating a trigger output signal Qn and connecting to the input terminal of the anti-oscillation control circuit 600 and the input terminal of the first nor gate circuit 400;

in this embodiment, one of the inputs of the second nor gate 500 is connected to a low level, and the S terminal of the first nor gate 400 and the R input terminal of the second nor gate can receive any variable input level. In a normal input mode, the RS flip-flop normally works in a holding, set, and reset state, and in a special input mode, i.e., when R and S are simultaneously inverted from a 1 state to a 0 state, the anti-oscillation structure 600 may play a role in suppressing output oscillation, forcing the output to be in a reset state.

The anti-oscillation control circuit 600 is configured to process outputs of the first nor gate circuit 400 and the second nor gate circuit 500 to obtain an anti-oscillation feedback signal C to control the first nor gate circuit 400.

In the present embodiment, the anti-oscillation circuit 600 monitors the states of the output signals Q and Qn, and outputs C high level with a certain delay once both become 1 state, which is effective for controlling the first nor gate circuit 400. Specifically, the method comprises the following steps:

referring to fig. 4, there is shown still another embodiment of an anti-oscillation RS flip-flop of the present invention, wherein the first nor gate circuit 400 includes: a first three-input NOR (NOR3) circuit 401; the second nor gate 500 includes: a second three-input NOR (NOR3) circuit 501.

The first three-input NOR (NOR3) circuit 401 is used to receive an external input signal S, and the output feedback signal Qn of the second NOR3 circuit 501 and the output signal C of the anti-oscillation control circuit 600. Processing the S signal, the feedback signal and the control signal to obtain a Q signal and outputting the Q signal;

a second three-input NOR (NOR3) circuit 501 is used to receive an external input signal R and the output feedback signal Q of the first NOR3 circuit 401. Processing the S signal and the feedback signal to obtain and output a Qn signal;

the anti-oscillation control circuit structure 600 includes: a second two-input NAND gate (NAND2) circuit 601 and a third inverter 602;

the second NAND2 module 601 is configured to connect the output signal Q of the first NOR3 module 401 and the output signal Qn of the second NOR3 module 501, and perform an and operation on the two signals to obtain a C0 signal; and the third inverter 602 is configured to receive the output signal C0 of the second NAND2 gate 601, process the C0 signal, obtain a C signal, and output the C signal.

In summary, in the RS flip-flop circuit with the anti-vibration structure according to the embodiment of the present invention, when the circuit inputs the two output terminals Q and Qn to oscillate in phase due to the simultaneous rising (the RS flip-flop implemented by the NAND structure) or the simultaneous falling (the RS flip-flop implemented by the NOR structure), the anti-vibration control feedback circuit detects the output signal and generates the feedback signal to be transmitted to the input terminal of the flip-flop, so as to destroy the oscillation condition of the RS flip-flop, and reset the flip-flop at the same time, that is, Q is stable in the 0 state, and Qn is kept in the 1 state. The circuit effectively eliminates oscillation and indeterminate states caused under a special input mode, and greatly improves the operation reliability of the RS trigger.

The above description is only for the two types of RS flip-flops according to the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention shall be covered by the scope of the present invention.

Those skilled in the art will appreciate that the invention may be practiced without these specific details.

Claims

1. An RS trigger circuit with an anti-oscillation structure is characterized by comprising: a first NAND gate (100), a second NAND gate (200) and an anti-oscillation circuit (300); the output end of the anti-oscillation circuit (300) is connected with the input end of the first NAND gate (100);

when the outputs of the first NAND gate (100) and the second NAND gate (200) are both 0, the anti-oscillation circuit (300) outputs 0, otherwise, the output of the anti-oscillation circuit (300) is 1;

the anti-oscillation circuit comprises a first inverter (301), a second inverter (302) and a third NAND gate (303);

the first inverter (301) is used for receiving an output signal of the first NAND gate (100), and the output end of the first inverter is connected with one input end of the third NAND gate (303);

the second inverter (302) is used for receiving the output signal of the second NAND gate (200), and the output end of the second inverter is connected with the other input end of the third NAND gate (303);

the output end of the third NAND gate (303) is used as the output end of the anti-oscillation circuit;

the first NAND gate (100) and the second NAND gate (200) are three-input NAND gates, the output end of the anti-oscillation circuit (300) is connected with the first input end of the first NAND gate (100), the second input end of the first NAND gate (100) is connected with an R signal or an S signal, and the third input end of the first NAND gate (100) is connected with the output end of the second NAND gate (200); the first input end of the second NAND gate (200) is connected with high level, the second input end is connected with the R signal or S signal which is not connected with the second input end of the first NAND gate (100), and the third input end is connected with the output end of the first NAND gate (100).

2. The RS flip-flop circuit with an anti-oscillation structure of claim 1, wherein the first nand gate and the second nand gate employ the same structural elements.

3. An RS trigger circuit with an anti-oscillation structure is characterized by comprising: a first NAND gate (100), a second NAND gate (200) and an anti-oscillation circuit (300); the output end of the anti-oscillation circuit (300) is connected with the input end of the first NAND gate (100) after being connected with the phase of the R signal or the phase of the S signal;

the first NAND gate and the second NAND gate are two-input NAND gates, the output end of the anti-oscillation circuit (300) is connected with the first input end of the first NAND gate after being connected with the R signal or the S signal phase through the AND gate, and the second input end of the first NAND gate is connected with the output end of the second NAND gate; the first input end of the second NAND gate is connected with the R signal or the S signal which is not connected with the AND gate, and the second input end of the second NAND gate is connected with the output end of the first NAND gate.

4. The RS flip-flop circuit with an anti-oscillation structure of claim 3, wherein the first NAND gate and the second NAND gate use the same structural elements.

5. An RS trigger circuit with an anti-oscillation structure is characterized by comprising: a first nor gate (400), a second nor gate (500), and an anti-oscillation circuit (600); the output end of the anti-oscillation circuit (600) is connected with the input end of the first NOR gate (400) after the phase or the phase of the R signal or the S signal;

when the outputs of the first NOR gate (400) and the second NOR gate (500) are both 1, the anti-oscillation circuit outputs 1, otherwise, the anti-oscillation control circuit outputs 0;

the anti-oscillation circuit comprises a first NAND gate (601) and a first inverter (602);

a first NAND gate (601) for receiving the output signals of the first NOR gate (400) and the second NOR gate (500), and the output end is connected with the input end of the first inverter (602);

the output of the first inverter (602) serves as the output of the anti-oscillation circuit.

6. The RS flip-flop circuit with an anti-oscillation structure of claim 5, wherein the first nor gate (400) and the second nor gate (500) are three-input nor gates, an output terminal of the anti-oscillation circuit (600) is connected to a first input terminal of the first nor gate (400), a second input terminal of the first nor gate (400) is connected to an R signal or an S signal, and a third input terminal of the first nor gate (400) is connected to an output terminal of the second nor gate (500); the first input end of the second NOR gate (500) is connected with low level, the second input end is connected with the R signal or the S signal which is not connected with the second input end of the first NOR gate (400), and the third input end is connected with the output end of the first NOR gate (400).

7. The RS flip-flop circuit with an anti-oscillation structure of claim 5, wherein the first NOR gate (400) and the second NOR gate (500) are two-input NOR gates, an output terminal of the anti-oscillation circuit is connected to a first input terminal of the first NOR gate (400) after being phase-or-connected with an R signal or an S signal through the OR gate, and a second input terminal of the first NOR gate is connected to an output terminal of the second NOR gate (500); a first input terminal of the second NOR gate (500) is connected to the R signal or the S signal to which the OR gate is not connected, and a second input terminal thereof is connected to an output terminal of the first NOR gate.

8. The RS flip-flop circuit with an anti-oscillation structure of any one of claims 5 to 7, wherein the first NOR gate and the second NOR gate employ the same structural elements.