CN108055022A - A kind of rest-set flip-flop circuit with resistant and oscillation resistant structure - Google Patents
A kind of rest-set flip-flop circuit with resistant and oscillation resistant structure Download PDFInfo
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- CN108055022A CN108055022A CN201711298921.0A CN201711298921A CN108055022A CN 108055022 A CN108055022 A CN 108055022A CN 201711298921 A CN201711298921 A CN 201711298921A CN 108055022 A CN108055022 A CN 108055022A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
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Abstract
The invention discloses a kind of rest-set flip-flop circuits with resistant and oscillation resistant structure, set resistant and oscillation resistant circuit, when rest-set flip-flop output is in nondeterministic statement, clamper are carried out to an output, so that output is quick to reach stable state.The rest-set flip-flop circuit that the present invention forms NAND gate, 11 are transformed by 00 when inputting, is 1 by the output clamper of a NAND gate in the case of exporting as nondeterministic statement, the defects of overcoming the rest-set flip-flop circuit input of NAND gate composition does not allow 00, the function of making rest-set flip-flop circuit is more perfect.The rest-set flip-flop circuit that the present invention forms nor gate, when input is transformed into 00 by 11, in the case of exporting as nondeterministic statement, it is 0 by the output clamper of a nor gate, the defects of overcoming the rest-set flip-flop circuit input of nor gate composition does not allow 11, the function of making rest-set flip-flop circuit is more perfect.
Description
Technical field
The present invention relates to a kind of rest-set flip-flop circuits with resistant and oscillation resistant structure, belong to Design of Digital Integrated Circuit field.
Background technology
Rest-set flip-flop has the function of set, reset and holding, is to form various functions module in Digital Logical Circuits
Element.
Using the basic RS filpflop that coupling NAND gate is handed over to realize, allow have set, reset and holding in normal work
Three kinds of states, two output are always at complementary state.I.e. when R and S are 1, trigger is in hold mode, and two defeated
Go out and all maintain an output valve thereon；When R becomes 0, Qn outputs will be caused to be forced into 1 state, at this moment complementary output terminal Q because
NAND gate input connected to it is height and becomes 0 state, and rest-set flip-flop is reset at this time；Conversely, when S becomes 0, Q is defeated
Go out and be forced into 1 state, at this moment complementary output terminal Qn becomes 0 state due to NAND gate connected to it input is high, this
When rest-set flip-flop be set.However in trigger mark sheet, when R and S input terminals are typically considered to simultaneously for 0 input pattern
Do not allow, it is high level that Q and Qn is exported under the input pattern, whole if two input signals become high level simultaneously
A circuit is considered as cross-linked phase inverter, and because two inverter input level are identical and the two is with identical
Propagation delay, it will rest-set flip-flop output is caused to occur that the end-state of trigger with frequency in-phase oscillation, can not be predicted.
When external input signal is unfettered, common rest-set flip-flop may cause maloperation in practical applications.Example
When being such as applied in arbitration and token circuit, rest-set flip-flop determines which signal first reaches in two inputs, can inevitably run into
The input pattern that 0 to 1 variation occurs simultaneously for R and S signals is inputted, trigger will be in indeterminate state, circuit function is caused to fail.
The rest-set flip-flop specifically formed for NAND gate is inputted when being transformed into 11 by 00, and output can be caused to vibrate, for
The rest-set flip-flop that nor gate is formed is inputted when being transformed into 00 by 11, and output can be caused to vibrate, and how to avoid what rest-set flip-flop exported
Unstable state is the technical issues of this field is urgently to be resolved hurrily.
The content of the invention
The technology of the present invention solves the problems, such as：Overcome the shortcomings of common rest-set flip-flop, a kind of RS with vibration proof structure is provided and is touched
Device circuit is sent out, eliminates vibration and indeterminate state that rest-set flip-flop triggers under special input pattern, RS triggerings greatly improved
The operating reliability of device.
Technical scheme is as follows：
A kind of rest-set flip-flop circuit with resistant and oscillation resistant structure is provided, including：First NAND gate, the second NAND gate and resistant and oscillation resistant
Circuit；The output terminal of resistant and oscillation resistant circuit and R signal or S signals phase and the rear input terminal for being connected the first NAND gate；
Wherein, when the first NAND gate and the output of the second NAND gate are 0, resistant and oscillation resistant control circuit exports 0, otherwise resistant and oscillation resistant
Control circuit output is 1.
Preferably, the first NAND gate and the second NAND gate are three input nand gates, the output terminal connection of resistant and oscillation resistant circuit the
The first input end of one NAND gate, the second input terminal connection R signal or S signals of the first NAND gate, the 3rd of the first NAND gate the
Input terminal connects the output terminal of the second NAND gate；The first input end connection high level of second NAND gate, the connection of the second input terminal
The R signal or S signals that second input terminal of the first NAND gate is not connected with, the 3rd input terminal connect the output terminal of the first NAND gate.
Preferably, the first NAND gate and the second NAND gate are two input nand gates, the output terminal of resistant and oscillation resistant circuit by with
Door and R signal or S signals phase and the first input end for being connected the first NAND gate afterwards, the second input terminal of the first NAND gate connect the
The output terminal of two NAND gates；The R signal or S signals that the first input end connection of second NAND gate is not connected with door, the second input
The output terminal of the first NAND gate of end connection.
Preferably, resistant and oscillation resistant circuit includes the first phase inverter, the second phase inverter and the 3rd NAND gate；
First phase inverter, for receiving the output signal Qn of first NAND gate, output terminal connects the 3rd NAND gate
One input terminal；
Second phase inverter, for receiving the output signal Q of second NAND gate, output terminal connects the another of the 3rd NAND gate
One input terminal；
Output terminal of the output terminal of 3rd NAND gate as resistant and oscillation resistant circuit.
Preferably, the first NAND gate and the second NAND gate use structural elements.
A kind of rest-set flip-flop circuit with resistant and oscillation resistant structure is provided, including：First nor gate, the second nor gate and resistant and oscillation resistant
Circuit；The output terminal of resistant and oscillation resistant circuit and R signal or S signals phase or the rear input terminal for being connected the first nor gate；
Wherein, when the first nor gate and the output of the second nor gate are 1, resistant and oscillation resistant control circuit exports 1, otherwise resistant and oscillation resistant
Control circuit output is 0.
Preferably, the first nor gate and the second nor gate are three input nor gates, the output terminal connection of resistant and oscillation resistant circuit the
The first input end of one nor gate, the second input terminal connection R signal or S signals of the first nor gate, the 3rd of the first nor gate the
Input terminal connects the output terminal of the second nor gate；The first input end connection low level of second nor gate, the connection of the second input terminal
The R signal or S signals that second input terminal of the first nor gate is not connected with, the 3rd input terminal connect the output terminal of the first nor gate.
Preferably, the first nor gate and the second nor gate are two input nor gates, the output terminal of resistant and oscillation resistant circuit by or
Door and R signal or S signals phase or the rear first input end for being connected the first nor gate, the second input terminal of the first nor gate connect the
The output terminal of two nor gates；The R signal or S signals that the first input end connection OR gate of second nor gate is not connected with, the second input
The output terminal of the first nor gate of end connection.
Preferably, resistant and oscillation resistant circuit includes the first NAND gate and the first phase inverter；
First NAND gate, for receiving the output signal of first nor gate and the second nor gate, output terminal connection the
The input terminal of one phase inverter；
Output terminal of the output terminal of first phase inverter as resistant and oscillation resistant circuit.
Preferably, the first nor gate and the second nor gate use structural elements.
The present invention has the following advantages：
(1) present invention provide the rest-set flip-flop circuit with vibration proof structure, circuit because input simultaneously rise and make two it is defeated
When in-phase oscillation occurs for outlet Q and Qn, by resistant and oscillation resistant feedback control circuit, to output signal detection and feedback signal biography is generated
The input terminal of trigger is transported to, destroys the condition that rest-set flip-flop vibrates, while trigger is resetted, by vibrating
The state of Q or Qn is limited during generation, the vibration triggered under special input pattern and indeterminate state is eliminated, RS greatly improved and touch
Send out the operating reliability of device.
(2) the rest-set flip-flop circuit that the present invention forms NAND gate, when input is transformed into 11 by 00, it is uncertain to export
It is 1 by the output clamper of a NAND gate in the case of state, the rest-set flip-flop circuit input for overcoming NAND gate composition is not permitted
Perhaps 00 the defects of, the function of making rest-set flip-flop circuit is more perfect.
(3) the rest-set flip-flop circuit that the present invention forms nor gate, when input is transformed into 00 by 11, it is uncertain to export
It is 0 by the output clamper of a nor gate in the case of state, the rest-set flip-flop circuit input for overcoming nor gate composition is not permitted
Perhaps 11 the defects of, the function of making rest-set flip-flop circuit is more perfect.
Description of the drawings
Fig. 1 is a kind of schematic diagram of the rest-set flip-flop circuit with vibration proof structure in the embodiment of the present invention；
Fig. 2 is a kind of specific implementation examples of circuits with vibration proof structure rest-set flip-flop in the embodiment of the present invention；
Fig. 3 is rest-set flip-flop circuit diagram of another in the embodiment of the present invention with vibration proof structure；
Fig. 4 is specific implementation examples of circuits of another in the embodiment of the present invention with vibration proof structure rest-set flip-flop；
Fig. 5 is the rest-set flip-flop circuit simulation waveform for not increasing vibration proof structure；
Fig. 6 is a kind of band vibration proof structure rest-set flip-flop circuit simulation waveform in example of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, it is public to the present invention below in conjunction with attached drawing
Embodiment is described in further detail.
Fig. 1 shows a kind of rest-set flip-flop circuit diagram with vibration proof structure in the embodiment of the present invention, including：First with
Not circuit 100, the second NAND gate circuit 200 and resistant and oscillation resistant circuit 300；Wherein, the first NAND gate circuit 100 and second with it is non-
The input of 200 output terminal of gate circuit connection resistant and oscillation resistant control circuit 300, the output terminal of resistant and oscillation resistant control circuit 300 are connected to the
One input terminal of one NAND gate 100.
First NAND gate circuit 100, for receiving external input signal R, the variation of response external level generates trigger
Output signal Qn is simultaneously connected to 200 circuit input end of 300 input terminal of resistant and oscillation resistant control circuit and the second NAND gate；
Second NAND gate circuit 200, for receiving external input signal S, generation trigger output signal Q is simultaneously connected to anti-
100 input terminal of 300 input terminal of oscillation control circuit and the first NAND gate circuit；
In the present embodiment, one of input termination high level of the second NAND gate circuit 200, the first NAND gate 100
R ends and the S input terminals of the second NAND gate can receive the incoming level of arbitrary variation.It commonly enters under pattern, rest-set flip-flop
It works normally in holding, set, reset state, when special input pattern, that is, R and S are simultaneously 1 state by the overturning of 0 state, resists
Oscillating structure 300 can play the role of inhibiting to export vibration, force output in reset state.
Resistant and oscillation resistant control circuit 300, for the output to the first NAND gate circuit 100 and the second NAND gate circuit 200 into
Row processing obtains resistant and oscillation resistant feedback signal C and controls the first NAND gate circuit 100.
In the present embodiment, the state of 300 monitoring output signal Q and Qn of resistant and oscillation resistant circuit, once both become 0 shape
State, then by certain delay output C low levels effective for controlling the first NAND gate circuit 100.Specifically：
With reference to Fig. 2, a kind of resistant and oscillation resistant rest-set flip-flop specific embodiment of the invention, above-mentioned first NAND gate electricity are shown
Road 100 includes：One or three input nand gate (NAND3) circuit 101；Second NAND gate circuit 200 includes：Two or three input with it is non-
Door (NAND3) circuit 201.
One or three input nand gate (NAND3) circuit 101 for receive external input signal R and, described second
The output signal C of the output feedback signal Q of NAND3 circuits 201 and the resistant and oscillation resistant control circuit.To the R signal and feedback
Signal and control signal are handled, and are obtained Qn signals and are exported；
Two or three input nand gate (NAND3) circuit 201 for receive external input signal S and, described first
The output feedback signal Qn of NAND3 circuits 101.S signals, feedback signal are handled, obtain Q signal and exported；
The resistant and oscillation resistant controling circuit structure 300 includes：First phase inverter 301, the second phase inverter 302 and first liang of input
NAND gate (NAND2) circuit 303；
First phase inverter 301, for receiving the output signal Qn of the first NAND3 doors 101, and to Qn signals at
Reason, obtains Qn1 signals；Second phase inverter 302, for receiving the output signal Q of the 2nd NAND3 doors 201, and to Q signal
It is handled, obtains Q1 signals；First NAND2 modules 303 export signal Qn1 and institute for connecting first phase inverter 301
The output signal Q1 of the second phase inverter 302 is stated, two paths of signals is carried out and is operated, C signal is obtained and exports；
Wherein, the output signal C of the first NAND2 circuit modules is the output signal of the resistant and oscillation resistant control circuit,
For controlling an input terminal of first NAND gate circuit.
It should be noted that resistant and oscillation resistant circuit structure 300 in flip-flop operation in the normal mode, i.e., set, reset or
During hold mode, export as two complementary signals, at this moment resistant and oscillation resistant circuit output signal B logic value is always 1, entire circuit
It can be reduced to cross-linked by being formed in three inputs there are one the first NAND3 doors 101 for 1 and the 2nd NAND3 doors 201
The basic trigger structures of NAND.When R and S is simultaneously 1 by 0 overturning, it is assumed that two NAND3 have identical propagation delay, Q
It is overturn simultaneously as 0 level by 1 initial level with Qn, if at this moment without resistant and oscillation resistant circuit structure 300 (it is 1 to give tacit consent to its output),
Entire circuit can be reduced to the oscillation rings being made of two phase inverters, and rest-set flip-flop will sink into oscillatory regime as shown in Figure 5,
Q and Qn is exported to occur to overturn with the cycling of phase with frequency.
Resistant and oscillation resistant circuit structure 300 plays the quick effect for inhibiting vibration, it should be noted that the biography of resistant and oscillation resistant circuit
Broadcasting delay needs to set on demand, because the reason for rest-set flip-flop vibrates is exactly because the first NAND3 doors 101 and second
The input signal of NAND3 doors 201 is the signal with phase with frequency, to break this oscillating condition, it is desirable that the propagation of resistant and oscillation resistant circuit
Delay cannot be the integral multiple of rest-set flip-flop cycle of oscillation, to avoid resistant and oscillation resistant control signal C and Q and Qn with the same phase of frequency.Most preferably
In the case of, concussion feedback propagation delay is the half in concussion cycle.After two output Q and Qn become 0 simultaneously, anti-skip circuitry
When output low level is transferred to the first NAND3 input terminals, if Q and Qn are just 1 level, the at this moment Qn outputs of rest-set flip-flop are tieed up
1 level is held, Q becomes 0 level, so as to by trigger reset.Fig. 6, which is shown, to be increased after resistant and oscillation resistant structure under special input pattern
Simulation waveform, as seen from Figure 6 when input is 11 by 00 variation, output can quickly reach stable state, it was demonstrated that antivibration knot
Structure effectively realizes the effect of suppression circuit vibration.
As a kind of supplement embodiment, Fig. 3 shows another resistant and oscillation resistant rest-set flip-flop schematic diagram, including：First or non-
Gate circuit 400, the second OR-NOT circuit 500 and resistant and oscillation resistant circuit 600；Wherein, the first OR-NOT circuit 400 and the second nor gate
The input of 500 output terminal of circuit connection resistant and oscillation resistant control circuit 600, the output terminal of resistant and oscillation resistant control circuit 600 are connected to second
One input terminal of nor gate 500.
First OR-NOT circuit 400, for receiving external input signal S, the variation of response external level generates trigger
Output signal Q is simultaneously connected to 500 circuit input end of 600 input terminal of resistant and oscillation resistant control circuit and the second nor gate；
Second OR-NOT circuit 500, for receiving external input signal R, generation trigger output signal Qn is simultaneously connected to
400 input terminal of 600 input terminal of resistant and oscillation resistant control circuit and the first OR-NOT circuit；
In the present embodiment, one of input termination low level of the second OR-NOT circuit 500, the first nor gate 400
S ends and the R input of the second nor gate can receive the incoming level of arbitrary variation.It commonly enters under pattern, rest-set flip-flop
It works normally in holding, set, reset state, when special input pattern, that is, R and S are simultaneously 0 state by the overturning of 1 state, resists
Oscillating structure 600 can play the role of inhibiting to export vibration, force output in reset state.
Resistant and oscillation resistant control circuit 600, for the output to the first OR-NOT circuit 400 and the second OR-NOT circuit 500 into
Row processing obtains resistant and oscillation resistant feedback signal C and controls the first OR-NOT circuit 400.
In the present embodiment, the state of 600 monitoring output signal Q and Qn of resistant and oscillation resistant circuit, once both become 1 shape
State, then by certain delay output C high level effective for controlling the first OR-NOT circuit 400.Specifically：
With reference to Fig. 4, another resistant and oscillation resistant rest-set flip-flop specific embodiment of the invention, above-mentioned first nor gate are shown
Circuit 400 includes：One or three input nor gate (NOR3) circuit 401；Second OR-NOT circuit 500 includes：Two or three input or
NOT gate (NOR3) circuit 501.
One or three input nor gate (NOR3) circuit 401 for receive external input signal S and, the 2nd NOR3 circuits
The 501 output feedback signal Qn and output signal C of resistant and oscillation resistant control circuit 600.To the S signals and feedback signal and control
Signal is handled, and is obtained Q signal and is exported；
Two or three input nor gate (NOR3) circuit 501 is used to receive external input signal R and the first NOR3 circuits
401 output feedback signal Q.S signals, feedback signal are handled, obtain Qn signals and exported；
The resistant and oscillation resistant controling circuit structure 600 includes：Second liang of input nand gate (NAND2) circuit 601 and the 3rd is anti-
Phase device 602；
2nd NAND2 modules 601, for connecting the first NOR3 modules 401 output signal Q and the 2nd NOR3 modules
501 output signal Qn carries out two paths of signals and operates, obtains C0 signals；3rd phase inverter 602, for receiving described
The output signal C0 of two NAND2 doors 601, and C0 signals are handled, it obtains C signal and exports.
In conclusion the rest-set flip-flop circuit with vibration proof structure described in the embodiment of the present invention, in circuit because input simultaneously
Rise (rest-set flip-flop that NAND structures are realized) or simultaneously decline (rest-set flip-flop that NOR structures are realized) and make two output terminal Q
With Qn occur in-phase oscillation when, by resistant and oscillation resistant feedback control circuit to output signal detection and generate feedback signal transmission to touch
It sending out the input terminal of device, destroys the condition that rest-set flip-flop vibrates, while trigger is resetted, i.e. Q stablizes in 0 state,
Qn is maintained at 1 state.The circuit effectively eliminates the vibration triggered under special input pattern and indeterminate state, and RS greatly improved
The operating reliability of trigger.
The above is only the corresponding embodiment of the two class rest-set flip-flops of the present invention, but protection scope of the present invention is simultaneously
Not limited to this, any one skilled in the art in the technical scope disclosed by the present invention, can readily occur in
Change or replacement should be covered by the protection scope of the present invention.
The content not being described in detail in description of the invention belongs to the known technology of professional and technical personnel in the field.
Claims (10)
1. a kind of rest-set flip-flop circuit with resistant and oscillation resistant structure, which is characterized in that including：First NAND gate (100), second with it is non-
Door (200) and resistant and oscillation resistant circuit (300)；The output terminal of resistant and oscillation resistant circuit (300) is connected first with R signal or S signal phases with after
The input terminal of NAND gate (100)；
Wherein, when the first NAND gate (100) and the second NAND gate (200) output are 0, resistant and oscillation resistant circuit (300) output 0,
Otherwise resistant and oscillation resistant circuit (300) output is 1.
2. the rest-set flip-flop circuit with resistant and oscillation resistant structure as described in claim 1, which is characterized in that the first NAND gate (100)
It is three input nand gates with the second NAND gate (200), the output terminal of resistant and oscillation resistant circuit (300) connects the first NAND gate (100)
First input end, the second input terminal connection R signal or S signals of the first NAND gate (100), the 3rd of the first NAND gate (100) the
Input terminal connects the output terminal of the second NAND gate (200)；The first input end connection high level of second NAND gate (200), second
The R signal or S signals that the second input terminal that input terminal connects the first NAND gate (100) is not connected with, the 3rd input terminal connection first
The output terminal of NAND gate (100).
3. the rest-set flip-flop circuit with resistant and oscillation resistant structure as described in claim 1, which is characterized in that the first NAND gate and second
NAND gate is two input nand gates, and the output terminal of resistant and oscillation resistant circuit (300) with door with R signal or S signal phases with after by being connected
The first input end of first NAND gate, the second input terminal of the first NAND gate connect the output terminal of the second NAND gate；Second with it is non-
The R signal or S signals, the second input terminal that the first input end connection of door is not connected with door connect the output terminal of the first NAND gate.
4. the rest-set flip-flop circuit with resistant and oscillation resistant structure as described in one of claims 1 to 3, which is characterized in that resistant and oscillation resistant electricity
Road includes the first phase inverter (301), the second phase inverter (302) and the 3rd NAND gate (303)；
First phase inverter (301), for receiving the output signal of first NAND gate (101), output terminal connection the 3rd with it is non-
One input terminal of door (303)；
Second phase inverter (302), for receiving the output signal of second NAND gate (201), output terminal connection the 3rd with it is non-
Another input terminal of door (303)；
Output terminal of the output terminal of 3rd NAND gate (303) as resistant and oscillation resistant circuit.
5. the rest-set flip-flop circuit with resistant and oscillation resistant structure as described in one of claims 1 to 3, which is characterized in that first with it is non-
Door and the second NAND gate use structural elements.
6. a kind of rest-set flip-flop circuit with resistant and oscillation resistant structure, which is characterized in that including：First nor gate (400), second or non-
Door (500) and resistant and oscillation resistant circuit (600)；The output terminal of resistant and oscillation resistant circuit (600) and R signal or S signals phase or after be connected first
The input terminal of nor gate (400)；
Wherein, the first nor gate (400) and the second nor gate (500) output are when being 1, resistant and oscillation resistant circuit output 1, otherwise antivibration
It is 0 to swing control circuit output.
7. the rest-set flip-flop circuit with resistant and oscillation resistant structure as claimed in claim 6, which is characterized in that the first nor gate (400)
It is three input nor gates with the second nor gate (500), the output terminal of resistant and oscillation resistant circuit (600) connects the first nor gate (400)
First input end, the second input terminal connection R signal or S signals of the first nor gate (400), the 3rd of the first nor gate (400) the
Input terminal connects the output terminal of the second nor gate (500)；The first input end connection low level of second nor gate (500), second
The R signal or S signals that the second input terminal that input terminal connects the first nor gate (400) is not connected with, the 3rd input terminal connection first
The output terminal of nor gate (400).
8. the rest-set flip-flop circuit with resistant and oscillation resistant structure as claimed in claim 6, which is characterized in that the first nor gate (400)
Be two input nor gates with the second nor gate (500), the output terminal of resistant and oscillation resistant circuit by OR gate and R signal or S signals phase or
The first input end of the first nor gate (400) is connected afterwards, and the second input terminal of the first nor gate connects the second nor gate (500)
Output terminal；The R signal or S signals that the first input end connection OR gate of second nor gate (500) is not connected with, the connection of the second input terminal
The output terminal of first nor gate.
9. the rest-set flip-flop circuit with resistant and oscillation resistant structure as described in one of claim 6 to 8, which is characterized in that resistant and oscillation resistant electricity
Road includes the first NAND gate (601) and the first phase inverter (602)；
First NAND gate (601), it is defeated for receiving the output signal of first nor gate (401) and the second nor gate (501)
Outlet connects the input terminal of the first phase inverter (602)；
Output terminal of the output terminal of first phase inverter (602) as resistant and oscillation resistant circuit.
10. the rest-set flip-flop circuit with resistant and oscillation resistant structure as described in one of claim 6 to 8, which is characterized in that first or non-
Door and the second nor gate use structural elements.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711298921.0A CN108055022B (en) | 2017-12-08 | 2017-12-08 | RS trigger circuit with anti-oscillation structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711298921.0A CN108055022B (en) | 2017-12-08 | 2017-12-08 | RS trigger circuit with anti-oscillation structure |
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| CN108055022A true CN108055022A (en) | 2018-05-18 |
| CN108055022B CN108055022B (en) | 2022-02-22 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111030669A (en) * | 2019-12-30 | 2020-04-17 | 科世达(上海)机电有限公司 | RS latch, RS trigger and controller |
| CN112994681A (en) * | 2021-04-20 | 2021-06-18 | 中科院微电子研究所南京智能技术研究院 | Logic operation circuit for memory calculation |
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|---|---|---|---|---|
| CN111030669A (en) * | 2019-12-30 | 2020-04-17 | 科世达(上海)机电有限公司 | RS latch, RS trigger and controller |
| CN111030669B (en) * | 2019-12-30 | 2023-08-04 | 科世达(上海)机电有限公司 | RS latch, RS trigger and controller |
| CN112994681A (en) * | 2021-04-20 | 2021-06-18 | 中科院微电子研究所南京智能技术研究院 | Logic operation circuit for memory calculation |
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| Publication number | Publication date |
|---|---|
| CN108055022B (en) | 2022-02-22 |
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