CN101686037A - Oscillator as well as drive circuit thereof and oscillating method - Google Patents
Oscillator as well as drive circuit thereof and oscillating method Download PDFInfo
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- CN101686037A CN101686037A CN200810165690A CN200810165690A CN101686037A CN 101686037 A CN101686037 A CN 101686037A CN 200810165690 A CN200810165690 A CN 200810165690A CN 200810165690 A CN200810165690 A CN 200810165690A CN 101686037 A CN101686037 A CN 101686037A
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Abstract
The invention discloses an oscillator as well as a drive circuit thereof and an oscillating method. The drive circuit is suitable for in parallel coupling quartz crystals to generate clock signals, and comprises a buffering unit and a control unit; the buttering unit is connected with the quartz crystals in parallel in order to amplify oscillating signals output by the quartz crystals as the clock signals; the control unit is coupled with the buffering unit and generates control signals to the buffering unit; the control unit decides the voltage level of the control signals by detecting whether the clock signals or the oscillating signals achieve the oscillating conditions of the quartz crystals, thereby controlling the gain value of the buffering unit. Therefore, the noise of the clock signal loaded into different frequency ranges can be avoided.
Description
Technical field
The present invention relates to a kind of oscillator, particularly relate to a kind of oscillator and drive circuit and oscillation method of avoiding clock signal to be written into the different frequency range noise.
Background technology
Along with the prosperity day by day of science and technology, electronic product is constantly weeded out the old and bring forth the new, and electronic product can be operated normally, the oscillator that just provides clock (oscillator) that is relied on.Produce clock accurately by oscillator, allow the chip of electronic product inside can sequential processing its received data or signal, and be sent to the circuit of its next stage in the correct time.And quartz (controlled) oscillator (quartzoscillator) not only can provide clock comparatively accurately, and has the characteristic that factors such as the temperature of not being subject to, humidity, processing procedure, operating voltage are disturbed simultaneously, so electronic product can use quartz (controlled) oscillator that its needed clock is provided mostly.
Fig. 1 is the circuit diagram of traditional oscillators.Please refer to Fig. 1, oscillator 100 comprises quartz crystal 101, inverter 102, resistance R and capacitor C.Because it is very stable that quartz crystal 101 electromechanics own resonate, so the operating principle of oscillator 100 is an above-mentioned characteristic of utilizing quartz crystal 101, exports a comparatively stable clock signal.But also because of so, whether quartz crystal 101 quality can influence oscillator 100 can starting of oscillation, and the waveform of clock signal Xtal_out after the starting of oscillation.
In general, the designer is when design oscillator 100, can't learn the quality quality of the employed quartz crystal 101 of user in advance, and in order to eliminate the influence of quartz crystal 101 quality discrepancies, and cause the possibility that oscillator 100 can't starting of oscillation, usually use the bigger inverter 102 of multiplication factors in that oscillator 100 is inner, so that there is bigger thrust allow oscillator 100 easy starting of oscillations.
But be to use the bigger inverter of multiplication factor 102, can amplify giving equally, and can cause its waveform may reach full swing (Full Swing) via the amplitude of clock signal Xtal_out after the starting of oscillation of quartz crystal 101.This full swing waveform is written into the noise of other different frequency ranges easily, so that may cause the instability of clock signal Xtal_out waveform, and then influences the frequency of clock signal Xtal_out.
For an oscillator, best waveform is a sine wave (Sine) waveform, be difficult for having the noise of different frequency range to be written under this waveform most, and the frequency of the clock signal that it provided can be the most stable.Yet concerning the oscillator that uses big multiplication factor inverter, because the influence of full swing waveform, if the quartz crystal quality of using is bad, then the noise of different frequency range that quartz crystal produces can be exaggerated, to such an extent as to influence the waveform and the frequency of oscillator clock.
Summary of the invention
The invention provides a kind of drive circuit, it is according to the yield value of the voltage level controller buffer of clock signal or oscillator signal.
The present invention also provides a kind of oscillator, can avoid clock signal to be written into the noise of different frequency range.
The present invention also provides a kind of oscillation method, and it reduces the yield value of buffer behind the vibrational stabilization of clock signal, excessively amplified with the noise of avoiding quartz crystal to produce.
The present invention proposes a kind of drive circuit, is suitable for the coupled in parallel quartz crystal, to produce a clock signal.This drive circuit comprises buffer cell and control unit.Buffer cell is in parallel with quartz crystal, in order to the oscillator signal that amplifies quartz crystal output as clock signal.Control unit couples buffer cell, and generation controls signal to buffer cell.Control unit is by detecting the oscillating condition whether clock signal or oscillator signal reach quartz crystal, and the voltage level of decision control signal is used the yield value of controlling buffer cell.
The present invention also proposes a kind of oscillator, and it comprises quartz crystal and drive circuit.Drive circuit comprises buffer cell and control unit.Drive circuit coupled in parallel quartz crystal is with clocking.Buffer cell is in parallel with quartz crystal, in order to the oscillator signal that amplifies quartz crystal output as clock signal.Control unit couples buffer cell, and generation controls signal to buffer cell.Control unit is by detecting the oscillating condition whether clock signal or oscillator signal reach quartz crystal, and the voltage level of decision control signal is used the yield value of controlling buffer cell.
In one embodiment of this invention, above-mentioned control unit comprises first latch module and detection module.First latch module has input, output, trigger end and the end of resetting, input coupling system voltage wherein, and trigger end receives triggering signal, and the replacement termination is received reset signal, output output control signal.First latch module determines the voltage level of control signal simultaneously according to the voltage level of triggering signal and reset signal.Detection module has input, first output and second output, input receives oscillator signal, first output couples the trigger end of first latch module, second output couples the replacement end of first latch module, in order to the voltage level decision triggering signal of foundation oscillator signal and the voltage level of this reset signal.
In one embodiment of this invention, above-mentioned detection module comprises first trigger, second trigger, resistance, the first transistor and transistor seconds.First trigger has first end and second end, and first termination is received oscillator signal, and second end couples the trigger end of first latch module, if the amplitude of oscillator signal is during greater than preset value, and the voltage level of handoff trigger signal then.Second trigger has first end and second end, and second end couples the replacement end of first latch module.The first end coupling system voltage of resistance.The first source-drain electrode end of the first transistor couples second end of resistance, and its second source-drain electrode end couples first end of second trigger, and its gate terminal couples second end of first trigger.The first source-drain electrode end of transistor seconds couples first end of second trigger, and its second source-drain electrode end couples an earthed voltage, and its gate terminal couples second end of first trigger.At one time, first and second transistor only has one of them can conducting, and at second trigger when receiving earthed voltage, second trigger switches the voltage level of reset signal.
In one embodiment of this invention, above-mentioned buffer cell comprises first driving element and second driving element.First driving element has first end, second end and output, and its first end couples the output of first latch module, and second end couples quartz crystal, if the voltage level of control signal is patrolled voltage level for high volume, then amplifies oscillator signal.Second driving element has first end, second end and output, the first end coupling system voltage, and second end couples quartz crystal, in order to amplify oscillator signal.Wherein the yield value of second driving element is 1, and the yield value of first driving element is greater than the yield value of second driving element.
In one embodiment of this invention, drive circuit also comprises the electric power detecting unit, and it couples buffer cell, and output detection signal is to buffer cell.Whether the electric power detecting unit reaches the voltage level that stable condition determines detection signal according to system voltage, uses the control buffer cell and whether amplifies oscillator signal.
In one embodiment of this invention, above-mentioned control unit comprises second latch module and the 3rd trigger.The input coupling system voltage of second latch module, its trigger end receives triggering signal, and its end of resetting couples the electric power detecting unit, its output output control signal.Second latch module determines the voltage level of control signal simultaneously according to the voltage level of triggering signal and detection signal.First end of the 3rd trigger couples quartz crystal, and its second end couples the trigger end of second latch module, in order to oscillator signal is converted to triggering signal.
In one embodiment of this invention, above-mentioned buffer cell comprises the 3rd driving element, the moving element of 4 wheel driven.The 3rd driving element has first end, second end, the 3rd end and output, and its first end couples the output of second latch module, and its second end couples quartz crystal, and its 3rd end couples the electric power detecting unit.The 3rd driving element determines whether to amplify oscillator signal according to the voltage level of control signal and detection signal simultaneously.The moving element of 4 wheel driven has first end, second end, the 3rd end and output, its first end coupling system voltage, and second end couples quartz crystal, and its 3rd end couples the electric power detecting unit.The moving element of 4 wheel driven is according to voltage level decision whether amplification oscillator signal of detection signal.Wherein the yield value of the moving element of 4 wheel driven is 1, and the yield value of the 3rd driving element is greater than the yield value of the moving element of 4 wheel driven.
In one embodiment of this invention, the first above-mentioned latch module and second latch module are all and latch, and this is latched as the D type and latchs, first and second transistor is respectively PMOS and nmos pass transistor, first, second, third and the moving element of 4 wheel driven be all NAND gate, and first, second and third trigger is all this schmitt trigger (Schmitt trigger).
The present invention also proposes a kind of oscillation method of oscillator, is suitable for driving the oscillator with quartz crystal, and with clocking, the method comprises the following steps.At first, amplify the oscillator signal of quartz crystal output as clock signal.Then, detect the oscillating condition whether clock signal or oscillator signal reach quartz crystal.At last, control the yield value that amplifies oscillator signal according to the result who detects.
In one embodiment of this invention, the above-mentioned step of controlling the yield value of buffer cell according to the result who detects comprises: if the amplitude of oscillator signal is then controlled described yield value greater than preset value; And, if the amplitude of oscillator signal does not then change described yield value not greater than preset value.
In one embodiment of this invention, the oscillation method of oscillator also comprises the following steps: detection system voltage, and judges that whether system voltage is stable, if system voltage is unstable, then do not amplify oscillator signal; And, if system voltage is own stable, then amplify oscillator signal.
In one embodiment of this invention, above-mentioned oscillating condition comprises that the amplitude of oscillator signal is greater than preset value.
Oscillator of the present invention and drive circuit thereof and oscillation method, by detecting the vibration that clock signal or oscillator signal confirm that quartz crystal is whether stable, behind vibrational stabilization, then reduce the yield value that clock signal is amplified, excessively amplified with the noise of avoiding quartz crystal to produce.By this, can avoid clock signal to be written into the noise of different frequency range, to improve the stability of clock signal frequency.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and be described with reference to the accompanying drawings as follows.
Description of drawings
Fig. 1 is the circuit diagram of traditional oscillators.
Fig. 2 A is the system block diagrams of the oscillator of one embodiment of the invention.
Fig. 2 B is the pierce circuit figure of Fig. 2 A embodiment.
Fig. 2 C is the oscillogram of system voltage, triggering signal, reset signal, control signal, oscillator signal and the clock signal of Fig. 2 B.
Fig. 3 A is the system block diagrams of the oscillator of another embodiment of the present invention.
Fig. 3 B is the circuit diagram of the oscillator of Fig. 3 A embodiment.
Fig. 3 C is the oscillogram of system voltage, detection signal, control signal, oscillator signal and the clock signal of Fig. 3 B.
Fig. 4 is the application schematic diagram of one embodiment of the invention.
Fig. 5 is the oscillation method flow chart of one embodiment of the invention.
Fig. 6 is the oscillation method flow chart of another embodiment of the present invention.
Fig. 7 is the oscillation method flow chart of further embodiment of this invention.
The reference numeral explanation
100,200,300: oscillator
101, X1: quartz crystal
102: inverter
210,310: drive circuit
211,311: buffer cell
211a, 211b, 311a, 311b: NAND gate
212,312: control unit
212a, 312a: latch
212b, 212c, 312b: trigger
313: the electric power detecting unit
400: chip
410: block
420: the physical layer block
C, C1, C2: electric capacity
R, R1, R2: resistance
VCC: system voltage
M1, M2: transistor
S
TRI: triggering signal
S
RS: reset signal
S
COL: control signal
S
OSC: oscillator signal
S
CLK: clock signal
S
DT: detection signal
S501～S503, S601～S604, S701～S707: steps flow chart
Embodiment
Have influence on the frequency and the waveform of clock signal for fear of the bad quartz crystal of oscillator using character, so propose oscillator and drive circuit and oscillation method, to reduce the yield value that amplifies oscillator signal, improve the bad influence that quartz crystal caused of quality.In order to make content of the present invention more clear, below the example that can implement according to this really as the present invention especially exemplified by embodiment.
Fig. 2 A is the system block diagrams of the oscillator of one embodiment of the invention.Please refer to Fig. 2 A, oscillator 200 comprises quartz crystal X1, drive circuit 210, capacitor C 1, C2 and resistance R 1.Drive circuit 210 quartz crystal X1 in parallel.Capacitor C 1 is coupled between the end and earthed voltage of quartz crystal X1.Capacitor C 2 is coupled between the other end and earthed voltage of quartz crystal X1.And resistance R 1 parallel connection buffer unit 211.Drive circuit 210 comprises buffer cell 211 and control unit 212.Buffer cell 211 quartz crystal X1 in parallel are in order to amplify the oscillator signal S of quartz crystal X1 output
OSC, with the output of the signal after amplifying with as clock signal S
CLKAnd capacitor C 2 can be filtered oscillator signal S
OSCNoise, and capacitor C 1 and resistance R 1 can utilize its electrical characteristic to revise clock signal S
CLKWaveform so that clock signal S
CLKWaveform more level off to string ripple (Sine).Simultaneously, resistance R 1 can determine the DC voltage level of this control signal.Then, clock signal S
CLKCan be converted to oscillator signal S again via quartz crystal X1
OSC, and the oscillator signal S after the conversion
OSCCan be cushioned unit 211 again amplifies with as clock signal S
CLK, allow oscillator 200 produce vibration by this.
For instance, rigidly connect when receiving power supply oscillator signal S when oscillator 200
OSCAmplitude be about zero, and because buffer cell 211 can anti-phase amplification oscillator signal S
OSCAmplitude, make oscillator 200 beginning starting of oscillations, and oscillator signal S
OSCAmplitude also can increase gradually.And, use bigger gain at starting of oscillation stage buffer cell 211 in order to make the oscillator 200 can fast start-up, be 10 at yield values of this hypothesis buffer cell 211 maximums, and this maximum yield value can be required and changed according to the user.At oscillator signal S
OSCAmplitude when not reaching preset value, represent the still unstabilized vibration of oscillator 200.This moment, oscillator 200 still needed bigger gain to quicken quartz crystal X1 starting of oscillation, and then control unit 212 outputs have the control signal S of logic high voltage level (for example being system voltage VCC)
COLReceive control signal S with logic high voltage level when buffer cell 211
COLThe time, represent oscillator 200 still to need bigger gain, be 10 so buffer cell 211 can be adjusted its yield value.
After starting of oscillation a period of time, oscillator signal S
OSCAmplitude can be greater than preset value, just representing the vibration of quartz crystal X1, oneself is stable.200 on oscillator needs the gain of low power to keep vibration at this moment, and then control unit 212 meeting outputs have the control signal S of logic low voltage level (for example being earthed voltage)
COLReceive control signal S with logic low voltage level when buffer cell 211
COLThe time, represent oscillator 200 not need bigger gain, so buffer cell 211 can be turned down its yield value (for example yield value is 1), keep vibration for oscillator 200.By this, oscillator 200 can avoid excessively amplifying the noise of quartz crystal different frequency range that X1 produces behind vibrational stabilization, to avoid clock signal S
CLKBe written into above-mentioned noise.
In addition, be noted that though the yield value that above-mentioned execution mode is a hypothesis buffer cell 211 when the firm starting of oscillation of oscillator 200 is 10, and after oscillator 200 stable oscillation stationary vibrations, the yield value of buffer cell 211 is 1, but above-mentioned example only is a kind of execution mode.Any those skilled in the art can spirit design buffer cell 211 according to the present invention yield value and the yield value of buffer cell 211 after oscillator 200 stable oscillation stationary vibrations when the firm starting of oscillation of oscillator 200.In addition, though above-mentioned execution mode is to suppose to receive the control signal S with logic high voltage level when buffer cell 211
COLThe time, represent oscillator 200 still to need bigger gain, but above-mentioned example only is a kind of execution mode.Any those skilled in the art can be according to spirit design control signal S of the present invention
COLSignificance signal.
Can be at this again for an embodiment, so that those skilled in the art more can understand the execution mode of the foregoing description.Fig. 2 B is the pierce circuit figure of Fig. 2 A embodiment.Please refer to Fig. 2 A and Fig. 2 B, in the present embodiment, buffer cell 211 comprises the first driving element 211a and the second driving element 211b, at this driving element is that example is with explanation with the NAND gate, but those skilled in the art, can also one or door (input all connects not gate) or other logical circuits that is equivalent to NAND gate wait and replace.Explain orally for convenience at this, the gain value settings of the second NAND gate 211b is 1, and the yield value of the first NAND gate 211a can be greater than the yield value of the second NAND gate 211b, gain value settings at this second NAND gate 211b is 10, and the demand when wherein the yield value of NAND gate 211a and 211b can be complied with design is changed.Control unit 212 comprises the first latch module 212a and detection module 212d.And detection module 212d comprises the first trigger 212b, the second trigger 212c, the first transistor M1, transistor seconds M2 and resistance R 2.Wherein, the first latch module 212a is latched as example with explanation with the D type, the first transistor M1 and transistor seconds M2 for example are respectively PMOS and nmos pass transistor, and the first trigger 212b and the second trigger 212c for example are this schmitt trigger (Schmitt trigger).
The first trigger 212b has first end and second end, and its first end couples quartz crystal X1, and its second end couples the trigger end CK that latchs 212a.The first end coupling system voltage VCC of resistance R 2, its second end couples the source terminal of the first transistor M1.The drain electrode end of the first transistor M1 couples first end of the second trigger 212c, and its gate terminal couples second end of the first trigger 212b.The drain electrode end of transistor seconds couples first end of the second trigger 212c, and its source terminal couples earthed voltage, and gate terminal couples second end of the first trigger 212a.
Fig. 2 C is system voltage VCC, the triggering signal S of Fig. 2 B
TRI, reset signal S
RS, control signal S
COL, oscillator signal S
OSCAnd clock signal S
CLKOscillogram.Please refer to Fig. 2 B and Fig. 2 C, when oscillator 200 begins to raise at system voltage VCC, the voltage level that its inner member equally can corresponding system voltage VCC at that time and produce voltage, trigger 212b, 212c then can preset the output logic low voltage level.System voltage VCC rise to stable time, represent the element in the oscillator to begin normal operation.At this moment, because of default output logic low voltage level (that is the reset signal S of trigger 212c
RS), make that latching 212a is Reset Status, that is latch the output Q meeting output logic low voltage level of 212a that the reversed-phase output Q that latchs 212a can output logic high-voltage level (that is control signal S
COL).
In buffer cell 211, first end of the NAND gate 211a of this moment can receive has logic high voltage level control signal S
COL, make NAND gate 211a understand the oscillator signal S that its second termination of anti-phase amplification is received
OSCBecause of the first end coupling system voltage VCC (treating as the receive logic high-voltage level) of NAND gate 211b, so the oscillator signal S that its second termination of the anti-phase amplification of NAND gate 211b meeting is received
OSC NAND gate 211a and 211b in the buffer cell 211 all can anti-phase amplification oscillator signal S at this moment
OSC, the yield value that buffer cell 211 is amplified can be the summation (that is yield value is 11) of NAND gate 211a and NAND gate 211b yield value.By amplifying oscillator signal S
OSCTo quicken the starting of oscillation of quartz crystal X1.
Then look down again, though the yield value that buffer cell 211 amplifies is 11, because oscillator signal S at the beginning
OSCAmplitude almost nil, so oscillator signal S at the beginning
OSCAnd clock signal S
CLKAmplitude less.After amplifying for more than 211 time via many resonance of quartz crystal X1 and buffer cell, amplitude can be exaggerated gradually.At oscillator signal S
OSCWhen the voltage level that the amplitude of signal is amplified to its crest and trough is enough to order about trigger 212b and changes the voltage level of its output, oscillator signal S
OSCCan make trigger 212b produce waveform is the narrow square wave shape or the triggering signal S of pulse type
TRI, wherein this moment oscillator signal S
OSCAmplitude be enough to order about trigger 212b and change its output triggering signal S
TRIVoltage level the time, make simultaneously trigger 212c switch its output reset signal S indirectly
RSVoltage level, the clock signal S of expression this moment
CLKOr oscillator signal S
OSCReach the oscillating condition of quartz crystal X1.
See also the triggering signal S of Fig. 2 B and Fig. 2 C again
TRIAnd reset signal S
RS, at triggering signal S
TRILevel in logic high voltage level H
1The time, because of transistor M1 is the logic low voltage level conducting, and transistor M2 is the logic high voltage level conducting, so transistor M2 conducting this moment makes earthed voltage be sent to trigger 212c.Because of the default output logic low voltage level of trigger 212c, thus before receiving earthed voltage reset signal S
RSVoltage level be logic low voltage level.When receiving earthed voltage, order about trigger 212c and can switch reset signal S
RSVoltage level be logic high voltage level, the reset signal S among its waveform such as Fig. 2 C
RSShown in, in addition, in Fig. 2 C, reset signal S
RSBecoming the generation of the time delay of logic high voltage level by logic low voltage level, is because transistor M2 can charge when transistor M1 conducting, in triggering signal S
TRIAfter switching its voltage level, transistor M1 can present not conducting and transistor M1 can conducting to discharge, the voltage level of transistor M2 and M1 link is enough to order about trigger 212c and switches it and export reset signal S to be reduced to through discharge by the time
RSVoltage level the time (for example being earthed voltage), make the voltage level of control signal SCOL switch to logic low voltage level just now.
Then, again referring to triggering signal S
TRI, the logic low voltage level L after above-mentioned logic high voltage level
1At this moment, transistor M1 for meeting because the logic low voltage level conducting, make system voltage VCC to be sent to trigger 212c, but, allow the voltage level that is sent to trigger 212c be not enough to order about trigger 212c switching reset signal S because resistance R 2 has produced pressure drop via resistance R 2
RSVoltage level.At triggering signal S
TRILogic high voltage level allow reset signal S
RSVoltage level switch to logic high voltage level after, triggering signal S
TRILogic high voltage level just can't change reset signal S again
RSVoltage level, make reset signal S
RSVoltage level can be held in logic high voltage level.
Please see the triggering signal S of Fig. 2 B and Fig. 2 C again
TRIAnd reset signal S
RS, triggering signal S
TRIImpulse waveform can be sent to always and latch 212a, latch 212a with triggering the system voltage VCC that its input D receives can be sent to its output Q.And at reset signal S
RSVoltage level switch to before the logic high voltage level because reset signal S
RSBe in logic low voltage level, allow and latch 212a and be in Reset Status, make that the output Q that latchs 212a can the output logic low voltage level, its reversed-phase output Q can the output logic high-voltage level.At reset signal S
RSVoltage level when switching to logic high voltage level, if triggering signal S
TRI212a is latched in triggering, then latch 212a and the system voltage VCC that its input D receives can be able to be sent to output Q, make the output Q output system voltage VCC (can be considered logic high voltage level) that latchs 212a, and latch reversed-phase output Q meeting output logic low voltage level (that is the control signal S of 212a
COL).
And the control signal S with logic low voltage level
COLWhen being sent to first end of NAND gate 211a, can make the output of NAND gate 211a can present floating (floating), that is NAND gate 211a and clock signal S
CLKPresent disconnection, make that NAND gate 211a can't anti-phase again amplification oscillator signal S
OSCSo that this moment, buffer cell only remained NAND gate 211 in running, and the yield value of buffer cell can become 1.By this, can avoid because of the excessive amplification of signal or because of the bad noise that produces of quartz crystal quality, to avoid clock signal S
CLKMake and influence its frequency and waveform because of being written into above-mentioned noise.
In some other embodiment, the buffer cell 211 of oscillator 200 also can only utilize NAND gate 211a to come anti-phase amplification oscillator signal S when starting of oscillation
OSC, utilize NAND gate 211b to come anti-phase amplification oscillator signal S and behind vibrational stabilization, just switch to
OSCCertainly, in these additional embodiments, can decide the yield value of control buffer cell 211 equally according to whether stablizing of vibration.
In addition, because before system voltage VCC is unstable, the running of its circuit relatively also can be unstable, if the bad words of circuit design, can make that oscillator exerts an adverse impact, so can add the electric power detecting unit in an embodiment, after system voltage VCC is stable, just come into operation with the control buffer cell.Fig. 3 A is the system block diagrams of the oscillator of another embodiment of the present invention.Please refer to Fig. 2 A and Fig. 3 A, the difference of its maximum is the electric power detecting unit 313 in the oscillator 300, and buffer cell 311 and control unit 312 is similar with buffer cell 211 and control unit 212 function modes in the oscillator 200, so then repeat no more at this in this function mode similar to oscillator 200.
Electric power detecting unit 313 couples buffer cell 311, with output detection signal S
DTTo buffer cell 311, and whether stablize according to system voltage VCC and to decide detection signal S
DTVoltage level, use control buffer cell 311 whether amplify oscillator signal S
OSC, wherein can whether reach preset value and judge whether system voltage VCC is stable according to system voltage VCC.For instance, when system voltage VCC did not stablize, electric power detecting unit 313 can transmit the detection signal S with logic low voltage level
DTTo buffer cell 311.This moment, buffer cell 311 received the detection signal S with logic low voltage level
DTAfter, then do not amplify oscillator signal S
OSCOtherwise when oneself stablized as system voltage VCC, electric power detecting unit 313 can transmit the detection signal S with logic high voltage level
DTTo buffer cell 311.This moment, buffer cell 311 received the detection signal S of logic high voltage level
DTAfter, then just can amplify oscillator signal S
OSCBy this, can avoid oscillator running when system voltage VCC is unstable, to quicken the speed of oscillator 300 starting of oscillations.
With the next embodiment that carries again, at length to explain orally the execution mode of oscillator 300.Fig. 3 B is the circuit diagram of the oscillator of Fig. 3 A embodiment.Please refer to Fig. 3 A and Fig. 3 B, in the present embodiment, buffer cell 311 comprises the 3rd driving element 311a and the moving element 311b of 4 wheel driven, is that example is with explanation with the NAND gate at this driving element.Control unit comprises the second latch module 312a and the 3rd trigger 312b.Wherein the second latch module 312a is latched as example with explanation with the D type, and the 3rd trigger 312b for example is the Si Mite inverter trigger.And the execution mode of electric power detecting unit is numerous, for example realize with this schmitt trigger, or other those skilled in the art known execution mode.Explain orally for convenience at this, the yield value of NAND gate 311b for example is 1, and with the yield value of door 311a can be greater than the yield value of NAND gate 311b, so be example with 10 at the yield value of this NAND gate 311a.
Latch the input D coupling system voltage VCC of 312a, its trigger end CK couples trigger 312b to receive triggering signal S
TRI, its end RS that resets couples electric power detecting unit 313 to receive detection signal S
DT, its reversed-phase output Q couples NAND gate 311a with output control signal S
COLTo NAND gate 311a.First end of 312b trigger couples quartz crystal X1 to receive oscillator signal S
OSC, its second end couple latch 312a trigger end CK so that triggering signal S to be provided
TRI NAND gate 311a has first end, second end, the 3rd end and output, and its first end couples the reversed-phase output Q that latchs 312a to receive control signal S
COL, its second end couples electric power detecting unit 313 to receive detection signal S
DT, its 3rd end and output coupled in parallel quartz crystal X1.The second NAND gate 311b has first end, second end, the 3rd end and output, and its first end coupling system voltage VCC, its second end couple electric power detecting unit 313 to receive detection signal S
DT, its 3rd end and output coupled in parallel quartz crystal X1.
Fig. 3 C is system voltage VCC, the detection signal S of Fig. 3 B
DT, control signal S
COL, oscillator signal S
OSCAnd clock signal S
CLKOscillogram.Please refer to Fig. 3 B and Fig. 3 C, in the present embodiment, whether first detection system voltage VCC is stable for 313 meetings of electric power detecting unit, stable as if system voltage VCC, then detection signal S
DTVoltage level can be logic low voltage level.This has the detection signal S of logic low voltage level
DTCan cause and latch the 312a replacement, so that latch the control signal S of the reversed-phase output Q output of 312a
COLBe logic high voltage level.In the same manner, NAND gate 311a and 311b also receive the detection signal S with logic low voltage level
DT, make the output of NAND gate 311a and 311b can present floating, so that NAND gate 311a and 311b can't anti-phase amplification oscillator signal S
OSCWaveform shown in Fig. 3 C, so when system voltage VCC rises, control signal S
COL, oscillator signal S
OSCAnd clock signal S
CLKThe voltage level of voltage level correspondence system voltage VCC at that time.
Look down, present when stablizing at system voltage VCC, electric power detecting unit 313 output-voltage levels are the detection signal S of logic high voltage level
DTAt this moment, be not Reset Status, the oscillator signal S in the time of therefore though latch 312a
OSCAlso can't order about driver 312b handoff trigger signal S
TRIVoltage level, that is latch the system voltage VCC that the input D of 312a received and can not be sent to output Q keep the logic high voltage level of output originally as control signal S so that latch the reversed-phase output Q of 312a
COLVoltage level.And NAND gate 311a and 311b are receiving the detection signal S with logic high voltage level
DTThe time, 311b can begin anti-phase amplification oscillator signal S
OSCThen if control signal S with logic high voltage level
COLBe sent to NAND gate 311a, NAND gate 311a can begin anti-phase amplification oscillator signal S
OSCSo far, buffer cell 311 can begin to amplify oscillator signal S
OSCAllowing oscillator 300 beginning starting of oscillations, and this moment buffer cell 311 yield value can equal the summation (that is yield value is 11) of NAND gate 311a and 311b yield value.
Again referring to Fig. 3 C, when oscillator 300 beginning starting of oscillations, oscillator signal S
OSCAnd clock signal S
CLKEqually can be by not having to having, and its amplitude can become greatly gradually, so that the convergence all-wave width of cloth.Please see Fig. 3 B, as oscillator signal S
OSCAmplitude big to ordering about trigger 312b handoff trigger signal S
TRIVoltage level the time, triggering signal S
TRIVoltage level can switch to logic high voltage level by logic low voltage level, and the action of this switching can trigger latchs 312a so that system voltage VCC (treating as logic high voltage level) is sent to its output Q, and the reversed-phase output Q output logic low voltage level that latchs 312a is as control signal S
COLVoltage level.When first termination of NAND gate 311a is received the control signal S with logic low voltage level
COLThe time, make the output of NAND gate 311a present floating, to such an extent as to NAND gate 311a can't anti-phase again amplification oscillator signal S
OSC311 surplus NAND gate 311b of buffer cell this moment are in running, that is the yield value of buffer cell 311 becomes 1.
The foregoing description can be used to be integrated in the chip.Fig. 4 is the application schematic diagram of one embodiment of the invention.Please refer to Fig. 4, Fig. 4 is the block diagram of chip 400, and the buffer cell of above-mentioned all embodiment, control unit and resistance, or even the electric power detecting unit all can be integrated into block 410, and pin Xin and Xout couple the two ends of quartz crystal, reach coupling capacitance C1 and C2 separately, and the clock signal S that oscillator produced
CLKPhysical layer (PHY) block to chip 400 can be provided, but so that chip normal operation.
From another viewpoint, it is oscillation method that above-mentioned all embodiment can converge whole, reintroduces some embodiment below, with the oscillation method of the explanation embodiment of the invention.Fig. 5 is the oscillation method flow chart of one embodiment of the invention.Please refer to Fig. 5, the oscillation method of present embodiment can be applicable to the oscillator of Fig. 2 A.At first, in step S501, can amplify earlier the oscillator signal of quartz crystal output, with as clock signal, the increment that this moment, oscillator signal amplified is high-gain values (for example yield value is 10).Then, step S502 can detect the oscillating condition whether clock signal or oscillator signal reach quartz crystal.At last, in step S503, can control the yield value that amplifies oscillator signal according to the testing result of step S502.
For instance, if when clock signal and oscillator signal all do not reach the oscillating condition of quartz crystal, then do not change the yield value (that is yield value is 10) that oscillator signal amplifies; Otherwise,, then reduce the yield value (for example yield value is 1) that oscillator signal amplifies if when clock signal or oscillator signal have reached the oscillating condition of quartz crystal.Therefore, before vibrational stabilization, can use high-gain values to amplify oscillator signal at quartz crystal, to quicken the starting of oscillation of quartz crystal.After the quartz crystal vibrational stabilization, can use the low gain value to amplify oscillator signal, with avoid because of signal excessively or because of the bad noise that is produced of quartz crystal quality.And above-mentioned use low gain amplifies the behavior of oscillator signal and is still after quartz crystal stable oscillation stationary vibration and continues to carry out, and this continues to amplify the oscillator signal S of the behavior of oscillator signal as Fig. 2 C
OSCThe waveform of stable oscillation stationary vibration.
Furthermore, the oscillation method that can carry an embodiment again describes a kind of practical manner of Fig. 5 embodiment in detail, and this oscillation method can be applicable to the embodiment of Fig. 2 B.Fig. 6 is the oscillation method flow chart of another embodiment of the present invention.Please refer to Fig. 6, in this enforcement, similarly earlier can execution in step S601, as clock signal, and the yield value that oscillator signal amplifies for example is 10 with the oscillator signal that amplifies quartz crystal output, and the behavior of amplifying oscillator signal is still and continues to carry out.Then, the amplitude of step S602 meeting detection oscillator signal.Then step S603 can judge oscillator signal amplitude whether greater than preset value, this preset value for example is clock signal S
CLKIn 1/2nd of full swing amplitude of wave form, but this preset value can adjust with different needs.If the judged result of step S603 is a "No", that is this moment oscillator signal amplitude not greater than preset value, then return step S602, to continue the amplitude of detection oscillator signal.When the amplitude of oscillator signal during greater than preset value, then the judged result of step S603 is a "Yes", then can execution in step S604, to reduce the yield value that amplifies oscillator signal, for example yield value is reduced to 1.
With Fig. 5 embodiment, its other execution mode also can detect the amplitude of clock signal or detect clock signal and oscillator signal simultaneously, by detecting the mode of clock signal or oscillator signal, confirm the vibration that quartz crystal is whether stable, to control the yield value of amplification oscillator signal according to whether stablize of vibration.
In addition, according to oscillator 300, can reintroduce the embodiment of an energy detection system voltage.Fig. 7 is the oscillation method flow chart of further embodiment of this invention.Please refer to Fig. 7, in the present embodiment, at first step S701 meeting detection system voltage is followed step S702 and can be judged whether system voltage is stable.If when system voltage was not stablized, the judged result of step S702 can be "No", follow execution in step S703, so that oscillator signal is not exaggerated.And then get back to step S701, to continue detection system voltage.Before system voltage was unstable, the method can continue execution in step S701～S703.When system voltage was stablized, this moment, the judged result of step S702 can be "Yes", then meeting execution in step S704, to amplify oscillator signal, at this, the yield value that amplifies oscillator signal for example is 10, and the behavior meeting of amplifying after this, oscillator signal continues to carry out.Then, the amplitude of step S705 meeting detection oscillator signal.Then, whether step S706 can judge the amplitude of oscillator signal greater than preset value, and this preset value for example is that clock signal is in 1/2nd of full swing amplitude of wave form.If the judged result of step S706 is a "No", that is this moment oscillator signal amplitude not greater than preset value, then return step S705, to continue the amplitude of detection oscillator signal.When the amplitude of oscillator signal during greater than preset value, then the judged result of step S603 can be "Yes", then can execution in step S707, to reduce the yield value that amplifies the control oscillator signal, for example yield value is reduced to 1.In addition, what deserves to be explained is the method can a firmware or hardware implement.
In sum, whether oscillator of the present invention and drive circuit thereof and oscillation method can be stablized by first detection system voltage, determine whether amplifying oscillator signal, after system voltage is stable, just amplify oscillator signal to quicken the quartz crystal starting of oscillation.Then, behind vibrational stabilization, then reduce the yield value that amplifies oscillator signal, excessively amplified with the noise of avoiding quartz crystal to produce by detecting the vibration that clock signal or oscillator signal confirm that quartz crystal is whether stable.By this, can quicken the speed of quartz crystal starting of oscillation, and the noise that can avoid amplifying quartz crystal amplified exceedingly, and make clock signal can not be written into the noise of different frequency range, to improve the stability of clock signal frequency.
Though the present invention discloses as above with embodiment; right its is not in order to limit the present invention; those skilled in the art can do some changes and retouching under the premise without departing from the spirit and scope of the present invention, so protection scope of the present invention is as the criterion with claim of the present invention.
Claims (31)
1. a drive circuit is suitable for coupled in parallel one quartz crystal, to produce a clock signal, comprising:
One buffer cell, in parallel with this quartz crystal, in order to the oscillator signal that amplifies the output of this quartz crystal as this clock signal; And
One control unit couples this buffer cell, and produces one and control signal to this buffer cell, and whether this control unit reaches an oscillating condition of this quartz crystal to control the yield value of this buffer cell by detecting this clock signal or this oscillator signal.
2. drive circuit as claimed in claim 1, wherein this oscillating condition comprises that the amplitude of this oscillator signal is greater than a preset value.
3. drive circuit as claimed in claim 2, wherein this control unit comprises:
One first latch module, have an input, an output, a trigger end and a replacement end, wherein this input couples a system voltage, this trigger end receives a triggering signal, this replacement termination is received a reset signal, wherein this first latch module determines the voltage level of this control signal simultaneously according to the voltage level of this triggering signal and this reset signal, and exports this control signal in this output; And
One detection module, have an input, one first output and one second output, this input receives this oscillator signal, this first output couples the trigger end of this first latch module, this second output couples the replacement end of this first latch module, in order to determine the voltage level of this triggering signal and this reset signal according to this oscillator signal.
4. drive circuit as claimed in claim 3, wherein this first latch module is to latch.
5. drive circuit as claimed in claim 4, wherein this is latched as a D type and latchs.
6. drive circuit as claimed in claim 3, wherein this detection module comprises:
One first trigger has one first end and one second end, and this first end couples this quartz crystal, and this second end couples the trigger end of this first latch module, if the amplitude of this oscillator signal during greater than this preset value, then switches the voltage level of this triggering signal;
One second trigger has one first end and one second end, and this second end couples the replacement end of this first latch module;
One resistance, its first end couples this system voltage;
One the first transistor, its source terminal couple second end of this resistance, and its drain electrode end couples first end of this second trigger, and its gate terminal couples second end of this first trigger; And
One transistor seconds, its drain electrode end couple first end of this second trigger, and its source terminal couples an earthed voltage, and its gate terminal couples second end of this first trigger;
Wherein at one time in, this first and this transistor seconds wherein a conducting is only arranged, and when this second trigger received this earthed voltage, this second trigger switched the voltage level of this reset signal.
7. drive circuit as claimed in claim 6, wherein this first and this transistor seconds be respectively a PMOS and nmos pass transistor.
8. drive circuit as claimed in claim 6, wherein this first and this second trigger be all this schmitt trigger.
9. drive circuit as claimed in claim 3, wherein this buffer cell can be lower than the gain running that receives before this control signal with one after receiving this control signal.
10. drive circuit as claimed in claim 9, wherein this buffer cell comprises:
A plurality of driving elements, wherein those driving elements are all in order to amplifying this oscillator signal, and after this buffer cell received this control signal, those driving elements partly can disconnect with this quartz crystal.
11. drive circuit as claimed in claim 9, wherein this buffer cell comprises:
One first driving element, have one first end, one second end and an output, this first end couples the output of this first latch module, and this second end couples this quartz crystal, if the voltage level of this control signal is a preset reset voltage level, then amplify this oscillator signal; And
One second driving element has one first end, one second end and an output, and this first end couples this system voltage, and this second end couples this quartz crystal, in order to amplify this oscillator signal;
Wherein, the yield value of this first driving element is greater than the yield value of this second driving element.
12. drive circuit as claimed in claim 11, wherein this preset reset voltage level is a logic high voltage level.
13. drive circuit as claimed in claim 11, wherein this first and this second driving element be all a NAND gate.
14. drive circuit as claimed in claim 1 also comprises:
One electric power detecting unit couples this buffer cell, and exports a detection signal to this buffer cell, and wherein this electric power detecting unit is whether to reach a preset value to indicate this buffer cell whether to amplify this oscillator signal by this detection signal according to this system voltage.
15. drive circuit as claimed in claim 14, wherein this control unit comprises:
One second latch module, its input couples a system voltage, its trigger end receives a triggering signal, its end of resetting couples this electric power detecting unit, its output is exported this control signal, wherein this second latch module determines the voltage level of this control signal simultaneously according to the voltage level of this triggering signal and this detection signal, exports this control signal in its output; And
One the 3rd trigger, its first end couples this quartz crystal, and its second end couples the trigger end of this second latch module, produces this triggering signal according to this oscillator signal.
16. drive circuit as claimed in claim 15, wherein this second latch module is to latch.
17. drive circuit as claimed in claim 16, wherein this is latched as a D type and latchs.
18. drive circuit as claimed in claim 15, wherein the 3rd trigger is a Si Mite inverter trigger.
19. drive circuit as claimed in claim 15, wherein this buffer cell comprises:
One the 3rd driving element, have one first end, one second end, one the 3rd end and an output, wherein this first end couples the output of this second latch module, this second end couples this quartz crystal, the 3rd end couples this electric power detecting unit, and the 3rd driving element determines whether to amplify this oscillator signal according to the voltage level of this control signal and this detection signal simultaneously; And
One 4 wheel driven moves element, have one first end, one second end, one the 3rd end and an output, wherein this first end couples this system voltage, this second end couples this quartz crystal, the 3rd end couples this electric power detecting unit, and the moving element of this 4 wheel driven is according to this oscillator signal of voltage level decision whether amplification of this detection signal;
Wherein, the yield value of the 3rd driving element is greater than the yield value of the moving element of this 4 wheel driven.
20. drive circuit as claimed in claim 19, wherein the 3rd and the moving element of 4 wheel driven be all a NAND gate.
21. drive circuit as claimed in claim 1, wherein this control unit is controlled the yield value of this buffer cell by the voltage level of this control signal.
22. an oscillator comprises:
One quartz crystal;
One drive circuit, this quartz crystal of coupled in parallel to produce a clock signal, comprising:
One buffer cell, in parallel with this quartz crystal, in order to the oscillator signal that amplifies the output of this quartz crystal as this clock signal; And
One control unit couples this buffer cell, and produces one and control signal to this buffer cell, and whether this control unit reaches an oscillating condition of this quartz crystal to control the yield value of this buffer cell by detecting this clock signal or this oscillator signal.
23. oscillator as claimed in claim 22, wherein this control unit comprises:
One first latch module, have an input, an output, a trigger end and a replacement end, wherein this input couples a system voltage, this trigger end receives a triggering signal, this replacement termination is received a reset signal, wherein this first latch module determines the voltage level of this control signal simultaneously according to the voltage level of this triggering signal and this reset signal, and exports this control signal in this output; And
One detection module, have an input, one first output and one second output, this input receives this oscillator signal, this first output couples the trigger end of this first latch module, this second output couples the replacement end of this first latch module, in order to determine the voltage level of this triggering signal and this reset signal according to this oscillator signal.
24. oscillator as claimed in claim 22, wherein this buffer cell can be lower than the gain running that receives before this control signal with one after receiving this control signal.
25. oscillator as claimed in claim 24, wherein this buffer cell comprises:
A plurality of driving elements, wherein those driving elements are all in order to amplify this oscillator signal;
Wherein, those driving elements partly can disconnect with this quartz crystal after receiving this control signal.
26. oscillator as claimed in claim 22 also comprises:
One electric power detecting unit, couple this buffer cell, and export a detection signal to this buffer cell, wherein, this electric power detecting unit is whether to reach a preset value to indicate this buffer cell whether to amplify this oscillator signal by this detection signal according to this system voltage.
27. oscillator as claimed in claim 26, wherein this buffer cell comprises:
One the 3rd driving element, have one first end, one second end, one the 3rd end and an output, wherein this first end couples the output of this second latch module, this second end couples this quartz crystal, the 3rd end couples this electric power detecting unit, and the 3rd driving element determines whether to amplify this oscillator signal according to the voltage level of this control signal and this detection signal simultaneously; And
One 4 wheel driven moves element, have one first end, one second end, one the 3rd end and an output, wherein this first end couples this system voltage, this second end couples this quartz crystal, the 3rd end couples this electric power detecting unit, and the moving element of this 4 wheel driven is according to this oscillator signal of voltage level decision whether amplification of this detection signal;
Wherein, the yield value of the 3rd driving element is greater than the yield value of the moving element of this 4 wheel driven.
28. the oscillation method of an oscillator is suitable for driving the oscillator with a quartz crystal, to produce a clock signal, comprising:
An oscillator signal that amplifies this quartz crystal output is as this clock signal;
Detect the oscillating condition whether this clock signal or this oscillator signal reach this quartz crystal; And
Control a yield value of this amplification oscillator signal according to the result who detects.
29. the oscillation method of oscillator as claimed in claim 28, wherein this oscillating condition comprises that the amplitude of this oscillator signal is greater than a preset value.
30. the oscillation method of oscillator as claimed in claim 29 wherein comprises according to the step that the result who detects controls the yield value of this buffer cell:
If the amplitude of this oscillator signal is then controlled this yield value greater than this preset value; And
If the amplitude of this oscillator signal does not then change this yield value not greater than this preset value.
31. the oscillation method of oscillator as claimed in claim 30 also comprises:
Detect a system voltage
Judge whether this system voltage is stable;
If this system voltage is unstable, then do not amplify this oscillator signal; And
If this system voltage is stable, then amplify this oscillator signal.
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| CN2008101656900A CN101686037B (en) | 2008-09-24 | 2008-09-24 | Oscillator as well as drive circuit thereof and oscillating method |
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| CN102710217A (en) * | 2011-03-28 | 2012-10-03 | 联咏科技股份有限公司 | Oscillator and control circuit thereof |
| CN104038156A (en) * | 2014-06-12 | 2014-09-10 | 珠海市杰理科技有限公司 | Crystal oscillator |
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| US4956618A (en) * | 1989-04-07 | 1990-09-11 | Vlsi Technology, Inc. | Start-up circuit for low power MOS crystal oscillator |
| US5982246A (en) * | 1998-04-06 | 1999-11-09 | Microchip Technology Incorporated | Crystal oscillator having prestressing bias circuit to provide fast start-up |
| US6194973B1 (en) * | 1998-05-29 | 2001-02-27 | Intel Corporation | Oscillator with automatic gain control |
| TW200524285A (en) * | 2004-01-09 | 2005-07-16 | Sunplus Technology Co Ltd | Crystal accelerated oscillator |
| US7009460B2 (en) * | 2004-07-21 | 2006-03-07 | Sony Ericsson Mobile Communications Ab | Method and apparatus for reducing the start time of a VCXO |
| US7292114B2 (en) * | 2005-08-01 | 2007-11-06 | Marvell World Trade Ltd. | Low-noise high-stability crystal oscillator |
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| CN102710217A (en) * | 2011-03-28 | 2012-10-03 | 联咏科技股份有限公司 | Oscillator and control circuit thereof |
| CN102710217B (en) * | 2011-03-28 | 2014-12-17 | 联咏科技股份有限公司 | Oscillator and control circuit thereof |
| CN104038156A (en) * | 2014-06-12 | 2014-09-10 | 珠海市杰理科技有限公司 | Crystal oscillator |
| CN105207620A (en) * | 2015-09-16 | 2015-12-30 | 苏州大学张家港工业技术研究院 | Colpitts oscillator |
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| WO2019169617A1 (en) * | 2018-03-09 | 2019-09-12 | 深圳市汇顶科技股份有限公司 | Crystal oscillator |
| US10848102B2 (en) | 2018-03-09 | 2020-11-24 | Shenzhen GOODIX Technology Co., Ltd. | Crystal oscillator |
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