JP2002312071A - Reset circuit and reset method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem that rash current intensively generated in each internal block in reset releasing causes a reset malfunction due to lowering of the power source voltage of an no-board power source. SOLUTION: Level switching timing of a reset signal RST is differentiated, in order to keep internal all current Iall including rush current IA to IC in each internal block 5A to 5C smaller than current supplying capacity I max of no-board power source at all times.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset circuit and a reset method for releasing reset of each internal block of an LSI (Large Scale Integrated Circuit).
In particular, the present invention relates to a reset circuit and a reset method for preventing a rush current from being concentrated at the time of reset release and preventing a reset malfunction of a system.

[0002]

2. Description of the Related Art At present, in many cases, an "on-board power supply" having a power supply mounted on a board is required for improving the reliability of a system. As a reset signal generation mechanism for controlling reset of each internal block on the LSI, a method of outputting a reset signal while the power supply voltage is rising and releasing the reset when the power supply voltage is stabilized. Is generally adopted.

[0003] With the recent improvement in LSI manufacturing technology, the number of elements in an LSI tends to increase, and accordingly, the power consumption inside the LSI also tends to increase. On the other hand, as compared with the increasing trend of the power consumption of the LSI, the increasing trend of the power supply of the on-board power supply is gentle.

[0004] Here, the following problem occurs. Immediately after the power is turned on, the on-board power supply gradually increases the voltage, during which a power-on reset signal is output. Thereafter, when the on-board power supply finishes rising to the specified voltage, the power-on reset signal is released. However, depending on the circuit structure inside the LSI, a rush current flows inside the chip when the power-on reset signal is released.

FIG. 7 is a diagram for explaining a rush current generated at the time of reset release. Point A in FIG.
Voltage VA of (reset terminal of flip-flop 101)
Rises with time t (FIG. 7B), the current IFF flowing through the flip-flop 101 becomes the voltage VA at the point A.
Is highest in the section where
02 occurs (FIG. 7 (c)).

The rush current 102 is generated by all the flip-flops 101 in the chip. As described above, since the number of elements of the LSI is increasing, when an LSI having a large number of elements is present on the substrate,
There is a possibility that the amount of current due to the occurrence of the rush current 102 exceeds the current supply capability of the on-board power supply.

When the amount of current at the time of the power-on reset exceeds the current supply capability of the on-board power supply, the power supply voltage of the on-board power supply decreases, and a power-on reset signal is output again with the decrease of the power supply voltage. Will be lost. The operation at this time will be described with reference to the drawings.

FIG. 8 is a diagram showing a configuration of a conventional reset circuit, and FIG. 9 is a diagram for explaining a reset malfunction in the conventional reset circuit. In FIG. 8, 103
Is a board; 104 is a power-on reset circuit provided on the board 103;
SI and 107 are reset terminals of the LSI 105, 107A
107C are internal blocks on the LSI 105, and 108 is a power-on reset circuit 1 from an on-board power supply (not shown).
Reference numeral 109 denotes a power supply line for the power supply voltage V supplied to the power supply circuit 04, and reference numeral 109 denotes a signal line for an external reset signal supplied from the outside to the power-on reset circuit 104.

In FIGS. 8 and 9, a power supply voltage V supplied from an on-board power supply (not shown) starts increasing at time T0, and exceeds a voltage threshold Vth of the power-on reset circuit 104 at time T1. (FIG. 9A). Subsequently, at time T when a predetermined delay time D has elapsed from time T1
2, the power-on reset signal R output from the power-on reset circuit 104 to each of the internal blocks A to C
The level of ST switches from “L” to “H” (FIG. 9)
(B)) All the internal blocks A to C are simultaneously released from the power-on reset.

At the moment of time T2, each of the internal blocks A to
The rush currents IA to IC are simultaneously concentrated in all the flip-flops provided in C (FIG. 9).
(C)). Due to the concentrated occurrence of the rush currents IA to IC, the total internal current Iall (total of the rush currents IA to IC, IA + IB + IC) exceeds the current supply capability Imax of the on-board power supply at time T3 (FIG. 9).
(D)), the power supply voltage V starts to decrease from the time T3 (FIG. 9A).

When the power supply voltage V supplied to the power-on reset circuit 104 falls below the voltage threshold Vth at time T4 (FIG. 9A), the power-on reset circuit 104
Of the power-on reset signal RST is “H”
To "L" (FIG. 9B), the internal blocks A to C are reset, and a reset malfunction occurs.

Particularly in the worst case, the time T5
.. To T8,..., The same operation as the times T1 to T4 is repeated indefinitely, and the system goes out of control.

[0013]

The conventional reset circuit and reset method are configured as described above.
When a rush current is concentrated in each LSI internal block at the time of reset release, there is a problem that a power supply voltage of an on-board power supply drops and a reset malfunction occurs.

In particular, in the worst case, a reset malfunction is repeated, resulting in a system runaway.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and a reset circuit and a reset capable of preventing a reset malfunction and a system runaway at the time of reset release and improving system operation reliability. The aim is to configure the method.

[0016]

SUMMARY OF THE INVENTION A reset circuit according to the present invention is configured such that when a plurality of rush currents occur in a plurality of LSI internal blocks, the level of the reset signal is set so that all of the plurality of rush currents are time-separated. The switching timing is made different.

The reset circuit according to the present invention comprises a plurality of L
The power supply voltage of the on-board power supply is provided for each of the SI internal blocks. The power supply voltage is compared with the voltage threshold. When the power supply voltage exceeds the voltage threshold, the level of the reset signal is switched after a predetermined delay time has elapsed. A plurality of power-on circuits for outputting to a corresponding LSI internal block are provided, and the plurality of power-on circuits have different voltage thresholds from each other.

The reset circuit according to the present invention includes a plurality of L
The power supply voltage of the on-board power supply is provided for each of the SI internal blocks. The power supply voltage is compared with the voltage threshold. When the power supply voltage exceeds the voltage threshold, the level of the reset signal is switched after a predetermined delay time has elapsed. A plurality of power-on circuits for outputting to corresponding LSI internal blocks are provided, and the plurality of power-on circuits have different delay times from each other.

The reset circuit according to the present invention includes a plurality of L
A plurality of level switching detection circuits, which are serially connected by the same number as that of the SI internal blocks, sequentially pass reset signals, and when the level switching of the reset signal is detected, output the level-switched reset signals to a plurality of LSI internal blocks. Respectively provided between the level switching detection circuits,
And a delay circuit for giving a delay time to the reset signal.

The reset circuit according to the present invention comprises a plurality of L
A plurality of power-on circuits provided corresponding to each of the SI internal blocks, comparing a power supply voltage of an on-board power supply with a voltage threshold, and switching and outputting a reset signal when the power supply voltage exceeds the voltage threshold. And a delay time is given to reset signals from a plurality of power-on circuits,
And a plurality of delay circuits each outputting to the I internal block, wherein the plurality of delay circuits have different delay times from each other.

A reset circuit according to the present invention compares a power supply voltage of an on-board power supply with a voltage threshold, and when the power supply voltage exceeds the voltage threshold, switches a level of a reset signal and outputs a reset signal. A reset signal delay circuit group configured by serially connecting the same number of delay circuits for providing a delay time to a plurality of LSI internal blocks and outputting a reset signal from a power-on circuit to the plurality of LSI internal blocks for each delay circuit Is provided.

In a reset circuit according to the present invention, in a reset signal delay circuit group, a delay time of a delay circuit to which a reset signal is directly input from a power-on circuit is set to 0.

In the reset method according to the present invention, a plurality of L
When a plurality of rush currents occur in the SI internal block, the level switching timing of the reset signal is changed so that all of the plurality of rush currents are time-separated.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a diagram showing a configuration of a reset circuit according to a first embodiment of the present invention. In FIG. 1, 1 is a board, 2A to 2C are power-on circuits provided on the board 1, respectively, 3 is an LSI provided on the board 1, 4A
To 4C are reset terminals of LSI3, 5A to 5C, respectively.
Is an internal block (LSI internal block) on the LSI 3; 6 is a power supply line for a power supply voltage V supplied from an on-board power supply (not shown) to the power-on circuits 2A to 2C;
Reference numeral 7 denotes a signal line for an external reset signal supplied from outside to the power-on circuits 2A to 2C.

The power-on circuits 2A to 2C are connected to the internal blocks 5A to 5C via reset terminals 4A to 4C of the LSI 3.
The reset signals RST1 to RST3 are output to C. These power-on circuits 2A to 2C are:
Both perform the same logical operation, but the reset signal R
In order to make all the output timings of ST1 to RST3 different, different voltage thresholds Vth1 to Vth3 (Vth1 ≠
Vth2 ≠ Vth3) is set.

Next, the operation will be described. When the power is turned on by an on-board power supply (not shown), each of the power-on circuits 2A to 2C detects the rise of the power supply voltage V based on the voltage thresholds Vth1 to Vth3. Power supply voltage V
Respectively exceed the voltage thresholds Vth1 to Vth3, the power-on circuits 2A to 2C output reset signals RST1 to RST
ST3 is output. Since the values of the voltage thresholds Vth1 to Vth3 are different at the time of detecting the rise of the power supply voltage V, the reset signals RST1 to RST3 are output from the power-on circuits 2A to 2C at different timings.

FIG. 2 is a diagram for explaining the operation of the reset circuit according to the first embodiment of the present invention. FIG. 2 (a)
2D show the power supply voltage V and the reset signal R
The level of ST, the currents I (IA to IC) flowing through the internal blocks 5A to 5C, and the total internal current Iall of the LSI 3 are shown. The horizontal axis in FIGS. 2A to 2D is a common time t.

Power supply voltage V supplied from on-board power supply
Starts rising at time T0, exceeds voltage threshold Vth1 of power-on circuit 2A at time T1, raises voltage threshold Vth2 of power-on circuit 2B at time T2, and raises voltage threshold Vth3 of power-on circuit 2C at time T3. (Fig. 2
(A)).

Subsequently, at time T4 when a predetermined delay time D has elapsed from time T1, the level of the reset signal RST1 from the power-on circuit 2A switches from "L" to "H" (FIG. 2 (b)). , The reset of the internal block A alone is released.

As described above, the rush current IA occurs in the internal block 2A at the moment of time T4 (FIG. 2C). However, at this time T4, since the delay time D has not elapsed from the times T2 and T3,
The reset signals RST2 and RST3 both remain 'L'. Therefore, the reset of the internal blocks 5B and 5C is not released, and no rush current IB or IC occurs in the internal blocks 5B and 5C.

That is, the internal total current Iall at this time is almost only the rush current IA (FIG. 2).
(D)) The total internal current Iall does not exceed the current supply capability Imax of the on-board power supply, and the power supply voltage V remains stable.

Next, at time T5 when a predetermined delay time D has elapsed from time T2, the rush current IA goes to a sufficiently low level, and the level of the reset signal RST2 from the power-on circuit 2B changes from "L" to "H". '(FIG. 2 (b)), the internal block 5B alone is reset released.

At the moment of time T5, a rush current IB occurs in the internal block 5B (FIG. 2C). However, at this time T5, the rush current IA has already occurred and is at a sufficiently low level. Further, since the delay time D has not elapsed from the time T3, the level of the reset signal RST3 remains "L", the reset of the internal block 5C is not released, and the rush current IC of the internal block 5C is generated. I haven't.

That is, the internal total current Iall at this time is almost only the rush current IB (FIG. 2).
(D)) The total internal current Iall does not exceed the current supply capability Imax of the on-board power supply, and the power supply voltage V remains stable.

Subsequently, at time T6 when a predetermined delay time D has elapsed from time T3, the rush current IB goes to a sufficiently low level, and the level of the reset signal RST3 from the power-on circuit 2C changes from "L" to "H". '(FIG. 2 (b)), and the internal block 5C alone is reset released.

At the instant of time T6, a rush current IC occurs in the internal block 5C (FIG. 2C). However, at this time T6, the rush currents IA, IB
All have already occurred and are at a sufficiently low level.

Therefore, the total internal current Ial at this time
1 is almost only a rush current IC (FIG. 2)
(D)) The total internal current Iall does not exceed the current supply capability Imax of the on-board power supply, and the power supply voltage V remains stable.

As described above, the voltage threshold Vt of the power-on circuits 2A to 2C for detecting the rise of the power supply voltage V
h1 to Vth3 are set to different values, respectively, and at time T4
Since the output timings of the reset signals RST1 to RST3 output to the internal blocks 5A to 5C are shifted from T6 to T6, the rush currents IA to IC generated in the internal blocks 5A to 5C are generated independently at dispersed timings. I will be. That is, the rush currents IA to IC are temporally separated, so that the total internal current I
It is possible to avoid a state where all exceeds the current supply capability Imax, and it is possible to prevent a reset malfunction when reset is released.

The voltage threshold V of each of the power-on circuits 2A to 2C
Th1 to Vth3 may be set to the same voltage threshold Vth, and instead, the delay time D from when the power supply voltage V is detected by the voltage threshold Vth to when the levels of the reset signals RST1 to RST3 are switched may be made different. That is,
In each of the power-on circuits 2A to 2C, the delay time D1,
D2 and D3 (D1 ≠ D2 ≠ D3) are set.

For example, when each delay time is set to D1 <D2 <D3, when the delay time D1 elapses after the power supply voltage V exceeds the voltage threshold Vth, first, the power-on circuit 2A
Switches the level of the reset signal RST1, and the internal block 5A alone is reset released.

Similarly, when the delay time D2 elapses after the power supply voltage V exceeds the voltage threshold value Vth, the power-on circuit 2B switches the level of the reset signal RST2, and the internal block 5B alone is reset released. When the delay time D3 elapses after the power supply voltage V exceeds the voltage threshold Vth, the power-on circuit 2C outputs the reset signal RST
By switching the level of No. 3, the reset of the internal block 5C alone is released. Even in this case, Rush Current I
It is possible to shift the generation timing of A to IC,
Similar effects can be obtained.

When setting the respective values of the voltage thresholds Vth1 to Vth3 and the delay times D1 to D3, the internal supply current Imax of the on-board power supply> the internal total current Iall is always satisfied. The rush currents IA to IC generated in the blocks 5A to 5C are temporally separated.

Furthermore, the order of switching the levels of the reset signals RST1 to RST3 of the power-on circuits 2A to 2C is not particularly limited. That is, the power supply voltages Vth1 to Vth1
The magnitude relationship between Vth3 and the delay times D1 to D3 can be set arbitrarily.

Further, the number of power-on circuits 2A to 2C is not particularly limited, and may be provided according to the number of internal blocks 5A to 5C of LSI 3.

As described above, according to the first embodiment, the rush current IA is generated in each of the internal blocks 5A to 5C.
~ When IC occurs, these rush current IA
~ Reset signal RS so that all ICs are time-separated
The rising timing of T1 to RST3 is set to time T4 to T
6, the reset malfunction and the runaway of the system at the time of reset release can be prevented, and the effect that the operation reliability of the system can be improved can be obtained.

Further, according to the first embodiment, the power supply voltage V of the on-board power supply provided for each of the internal blocks 5A to 5C is compared with the voltage thresholds Vth1 to Vth3 having different values. Then, when the power supply voltage V exceeds the voltage thresholds Vth1 to Vth3, the predetermined delay time D
After the time elapses, the reset signals RST1 to RST3 are switched from "L" to "H", and the power-on circuits 2A to 2C for outputting to the corresponding internal blocks are provided. Can be prevented, and the operation reliability of the system can be improved.

Further, according to the first embodiment, each of the internal blocks 5A to 5C is provided correspondingly.
The power supply voltage V of the on-board power supply is compared with the voltage threshold Vth, and when the power supply voltage V exceeds the voltage threshold Vth, the reset signals RST1 to RST3 are set to “L” after delay times D1 to D3 having different values have elapsed. To "H", and a plurality of power-on circuits 2A to 2C for outputting to the corresponding internal blocks 5A to 5C are provided.
There is an effect that a reset malfunction and a runaway of the system at the time of reset release can be prevented, and the operation reliability of the system can be improved.

Embodiment 2 FIG. 3 is a diagram showing a configuration of a reset circuit according to a second embodiment of the present invention. The same or corresponding components as those in FIG. 1 are denoted by the same reference numerals.

In FIG. 3, 8A to 8C are all LS
It is a rising detection circuit (level switching detection circuit) arranged inside I3. The rise detection circuits 8A to 8C
When the rising edge of the external reset signal is detected, reset signals RST1 to RST3 are output to the internal blocks 5A to 5C, respectively. 9A and 9B are delay circuits such as a signal delay buffer for giving a delay time to the passing reset signal. The delay circuits 9A and 9B are provided between the rise detection circuits 8A and 8B and between the rise detection circuits 8B and 8C, respectively.

Next, the operation will be described. FIG. 4 is a diagram for explaining an operation of the reset circuit according to the second embodiment of the present invention. Each vertical axis in FIG. 4A to FIG.
Power supply voltage V, level of external reset signal, level of reset signal RST1, level of reset signal RST2, level of reset signal RST3, total internal current I of LSI3
all respectively. 4 (a) to FIG.
The horizontal axis of (f) is a common time t.

When an external reset is performed on the LSI 3,
The power supply voltage V of the on-board power supply (not shown) starts increasing at time T0, and at time T1, the power supply voltage V exceeds the voltage threshold Vth (FIG. 4A), and at time T2 when a delay time D1 has elapsed from time T1. , The level of the external reset signal is switched from “L” to “H” (FIG. 4B).

The rising detection circuit 8A detects the switching of the external reset signal level at time T2,
At time T3 after a lapse of the delay time D2 from 2, the level of the reset signal RST1 is switched from “L” to “H” (FIG. 4C). At this time, as in the first embodiment, since only the internal block 5A is reset by the reset signal RST1, the internal total current Iall is only the rush current IA (FIG. 4 (f)), and a reset malfunction occurs. Never.

The reset signal RST1 is input from the rise detection circuit 8A to the rise detection circuit 8B via the delay circuit 9A. The delay circuit 9A outputs the reset signal RST1
Is given a delay time D3, so that the rise detection circuit 8B
At a time T4 which is delayed from the time T3 by a delay time D3, the level of the reset signal RST1 becomes 'L'.
Is switched to "H" (FIG. 4 (c)).

The rise detection circuit 8B detects the rise of the reset signal RST1 at time T4, and changes the level of the reset signal RST2 from "L" to "H" at time T5 when a predetermined time delay D4 has elapsed from time T4.
(FIG. 4D). At this time, the internal block 5
Since only B is released from reset by the reset signal RST2, the internal total current Iall becomes the rush current IB
(FIG. 4F), and no reset malfunction occurs.

The reset signal RST2 is input from the rise detection circuit 8B to the rise detection circuit 8C via the delay circuit 9B. The delay circuit 9B outputs the reset signal RST2
To the rising edge detection circuit 8C
Therefore, at time T6, which is delayed from the time T5 by the delay time D5, the level of the reset signal RST2 becomes "L".
To "H" (FIG. 4D).

The rise detection circuit 8C detects the rise of the reset signal RST2 at time T6, and changes the level of the reset signal RST3 from "L" to "H" at time T7 after a lapse of a predetermined time delay D6 from time T6.
(FIG. 4D). At this time, the internal block 5
Since only C is reset by the reset signal RST3, the internal total current Iall is changed to the rush current IC.
(FIG. 4F), and no reset malfunction occurs.

Therefore, according to the first embodiment, delay times D3 and D5 of delay circuits 9A and 9B are set, and rush currents IA to IC generated in internal blocks 5A to 5C are separated by time. The total internal current Iall can always be suppressed lower than the current supply capability Imax. That is, a reset malfunction can be avoided.

The number of rise detection circuits 8A to 8C is not particularly limited, and may be provided according to the number of internal blocks 5A to 5C of LSI 3. And
The number of the delay circuits 9A and 9B is determined by the rise detection circuit 8A.
1C less than the number of ８8C.

As described above, according to the second embodiment, the same number of the internal blocks 5A to 5C are connected in series and the reset signals are sequentially passed, and the reset signal 'L' is output.
When the level switching from "H" to "H" is detected, the reset signals RST1 to RST3 whose levels have been switched are transmitted to the internal blocks 5A.
5A to 5C and the rise detection circuits 8A to 8C connected in series, respectively, and the reset signal RST includes delay times D3 and D
Since the delay circuits 9A and 9B for providing 5 are provided, it is possible to prevent a reset malfunction and a runaway of the system at the time of reset release, thereby improving the operation reliability of the system.

Embodiment 3 FIG. 5 is a diagram showing a configuration of a reset circuit according to a third embodiment of the present invention. Figure 1
The same or corresponding components as in FIG. 3 are denoted by the same reference numerals. In FIG. 5, 9A to 9C are internal blocks 5A.
5C are delay circuits inside the LSI 3 provided for the respective LSIs. The delay circuits 9A to 9C include a power-on circuit 2A.
2C are given different delay times, and are output to the internal blocks 5A to 5C, respectively.

Here, the voltage thresholds and delay times of the power-on circuits 2A to 2C are set to the same value, and the reset signals RST from the power-on circuits 2A to 2C all have the same output timing. The timing of these reset signals RST may be shifted by the delay circuits 9A to 9C inside the LSI 3, and the same effect can be obtained.

As described above, according to the third embodiment, the power supply voltage V of the on-board power supply and the voltage threshold Vth are provided corresponding to each of the internal blocks 5A to 5C.
When the power supply voltage V exceeds the voltage threshold Vth, the power-on circuits 2A to 2C that switch the level of the reset signal RST and output the reset signal RST and the reset signal RST from the power-on circuits 2A to 2C have different delays. The delay circuits 9A to 9C for giving time and outputting the signals to the internal blocks 5A to 5C are provided, thereby preventing reset malfunction and system runaway when reset is released.
The effect that the operation reliability of the system can be improved can be obtained.

Embodiment 4 FIG. 6 is a diagram showing a configuration of a reset circuit according to a fourth embodiment of the present invention. Figure 1
The same or corresponding components as in FIG. 3 are denoted by the same reference numerals. In FIG. 6, reference numeral 2 denotes a power-on circuit on the board 1, and 3A to 3C denote internal blocks 5A to 5C and a delay circuit 9.
A to 9C are LSIs provided respectively. The delay circuits 9A to 9C are connected in series to form a reset signal delay circuit group.

Next, the operation will be described. When power is supplied to the board 1 from an on-board power supply (not shown), the power-on circuit 2 receives the power supply voltage V of the power supply line 6 and the external reset signal of the signal line 7, and the power-on circuit 2
And outputs a reset signal RST to the LSIs 3A to 3C arranged on the same board 1.

Each of the LSIs 3A to 3C has a delay circuit 9A to 9
C are provided, and the reset signal RST from the power-on circuit 2 sequentially passes through the delay circuits 9A to 9C of the reset signal delay circuit group, and a delay time is given to each of the delay circuits 9A to 9C. The delay circuits 9A to 9C output the reset signals RST to the internal blocks 5A to 5C, respectively, when the delay times are given to the reset signals RST. Thus, each L
Since the delay circuits 9A to 9C are arranged inside the SIs 3A to 3C, the internal blocks 5A of the LSIs 3A to 3C
-5C are reset at different timings.

As a result, even if a rush current is generated inside each of the LSIs 3A to 3C, the rush current is generated at a different timing and all rush currents are time-separated. As a result, it is possible to avoid occurrence of a problem related to reset release.

As described above, according to the fourth embodiment, the power supply voltage V of the on-board power supply is compared with the voltage threshold Vth, and when the power supply voltage V exceeds the voltage threshold Vth, the reset signal RST is reset to a low level. The power-on circuit 2 for switching the level from L 'to' H 'and outputting the same, and the delay circuits 9A to 9C for giving a delay time to the reset signal RST include an internal block 5A.
To 5C, and the reset signals RST from the power-on circuit 2 are supplied to the internal blocks 5A to 5C.
Since the reset signal delay circuit group for outputting each of the delay circuits 9A to 9C to C is provided, reset malfunction and runaway of the system at the time of reset release can be prevented, and the operation reliability of the system can be improved. Is obtained.

The delay time of the delay circuit 9A to which the reset signal RST from the power-on circuit 2 is first input may be set to 0, and the same effect can be obtained. That is, this is equivalent to omitting the delay circuit 9A from the configuration of FIG. If the delay circuit 9A is not omitted, L
Since the delay circuits 9A to 9C are provided in common for the SIs 3A to 3C, the manufacturing process can be simplified and the working efficiency can be improved. On the other hand, when the delay circuit 9A is omitted, the cost can be reduced accordingly.

The level switching of the reset signal is "L".
However, the present invention is not limited to “H” and “H”. Even if “H” to “L”, exactly the same effect can be obtained, and it is not an essential problem for the present invention.

[0070]

As described above, according to the present invention, when a plurality of rush currents occur in a plurality of LSI internal blocks, the level switching of the reset signal is performed so that all of the plurality of rush currents are time-separated. Since the timing is made different, there is an effect that a reset malfunction and a runaway of the system at the time of reset release can be prevented, and the operation reliability of the system can be improved.

According to the present invention, the power supply voltage of the on-board power supply is provided in correspondence with each of a plurality of LSI internal blocks, and the voltage threshold is compared with the power supply voltage. A plurality of power-on circuits for switching the level of a reset signal after a lapse of time and outputting the reset signal to a corresponding LSI internal block are provided, and the plurality of power-on circuits have different voltage thresholds from each other. There is an effect that malfunction and runaway of the system can be prevented, and operation reliability of the system can be improved.

According to the present invention, the power supply voltage of the on-board power supply is provided corresponding to each of a plurality of LSI internal blocks, and the power supply voltage is compared with the voltage threshold. A plurality of power-on circuits for switching the level of a reset signal after a lapse of time and outputting the reset signal to a corresponding LSI internal block are provided, and the plurality of power-on circuits have different delay times from each other. There is an effect that malfunction and runaway of the system can be prevented, and operation reliability of the system can be improved.

According to the present invention, the reset signals are serially connected by the same number as the plurality of LSI internal blocks, sequentially pass the reset signals, and when the level change of the reset signal is detected, the reset signals whose levels have been switched are output to the plurality of LSI internal blocks. Since there are provided a plurality of level switching detection circuits and a delay circuit provided between the series-connected level switching detection circuits and providing a delay time to the reset signal, a reset malfunction upon reset release / runaway of the system And the operation reliability of the system can be improved.

According to the present invention, the power supply voltage of the on-board power supply is provided in correspondence with each of the plurality of LSI internal blocks, and the voltage threshold is compared with the power supply voltage. A plurality of power-on circuits for switching levels and outputting, and a plurality of delay circuits for giving delay times to reset signals from the plurality of power-on circuits and outputting the reset signals to a plurality of LSI internal blocks, respectively. Since each delay time is different from each other, reset malfunction at reset release
This has the effect of preventing runaway of the system and improving the operational reliability of the system.

According to the present invention, the power supply voltage of the on-board power supply is compared with the voltage threshold, and when the power supply voltage exceeds the voltage threshold, the power-on circuit that switches the level of the reset signal and outputs the reset signal, A delay circuit for providing a delay time is connected in series by the same number as a plurality of LSI internal blocks, and a reset signal from a power-on circuit is supplied to a plurality of L
A reset signal delay circuit group that outputs each delay circuit to the SI internal block is provided, so that reset malfunction and system runaway when reset is released can be prevented, and system operation reliability can be improved. There is.

According to the present invention, in the reset signal delay circuit group, the delay time of the delay circuit to which the reset signal is directly input from the power-on circuit is set to 0, so that the reset malfunction at the time of reset release and the system failure This has the effect of preventing runaway and improving the operation reliability of the system.

According to the present invention, when a plurality of rush currents occur in a plurality of LSI internal blocks,
So that multiple rush currents are all separated by time,
Since the level switching timing of the reset signal is made different, reset malfunction at reset release
This has the effect of preventing runaway of the system and improving the operational reliability of the system.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a reset circuit according to a first embodiment of the present invention;

FIG. 2 is a diagram for explaining an operation of the reset circuit according to the first embodiment of the present invention;

FIG. 3 is a diagram illustrating a configuration of a reset circuit according to a second embodiment of the present invention;

FIG. 4 is a diagram for explaining an operation of the reset circuit according to the second embodiment of the present invention;

FIG. 5 is a diagram showing a configuration of a reset circuit according to a third embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of a reset circuit according to a fourth embodiment of the present invention.

FIG. 7 is a diagram for explaining a rush current that occurs when reset is released.

FIG. 8 is a diagram showing a configuration of a conventional reset circuit.

FIG. 9 is a diagram for explaining a reset malfunction in a conventional reset circuit.

[Explanation of symbols]

1 Board, 2, 2A-2C power-on circuit, 3, 3
A-3C LSI, 4A-4C reset terminal, 5A-
5C internal block (LSI internal block), 6 power supply line, 7 signal line, 8A to 8C rising detection circuit (level switching detection circuit), 9A to 9C delay circuit.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Harubo Kondo 2-3-2 Marunouchi, Chiyoda-ku, Tokyo F-term (reference) in Mitsubishi Electric Corporation 5B054 AA11 BB01 CC07

Claims (8)

[Claims] 1. A reset circuit which receives a power supply voltage from an on-board power supply and switches the level of the reset signal to output to a plurality of LSI internal blocks which are reset by resetting the level of the reset signal. A plurality of rush currents occurring in the LSI internal block, the level switching timing of the reset signal is changed so that all of the plurality of rush currents are time-separated. 2. A power supply voltage of an on-board power supply is provided for each of a plurality of LSI internal blocks. The power supply voltage is compared with a voltage threshold, and when the power supply voltage exceeds the voltage threshold, a predetermined delay time is set. 2. The power supply circuit according to claim 1, further comprising: a plurality of power-on circuits for switching the level of a reset signal after a lapse of time and outputting the reset signal to the corresponding LSI internal block; Reset circuit as described. 3. A power supply voltage of an on-board power supply, which is provided corresponding to each of a plurality of LSI internal blocks, is compared with a voltage threshold, and when the power supply voltage exceeds the voltage threshold, a predetermined delay time is set. 2. The power supply circuit according to claim 1, further comprising: a plurality of power-on circuits for switching the level of a reset signal after a lapse of time and outputting the reset signal to the corresponding LSI internal block, wherein the plurality of power-on circuits have different delay times. Reset circuit as described. 4. A plurality of LSI internal blocks which are connected in series by the same number as the plurality of LSI internal blocks, sequentially pass reset signals, and output the reset level-switched reset signals to the plurality of LSI internal blocks upon detecting a level change of the reset signal. 2. The reset circuit according to claim 1, further comprising a level switching detection circuit, and a delay circuit provided between the series-connected level switching detection circuits and providing a delay time to the reset signal. 5. A power supply voltage of an on-board power supply is provided for each of a plurality of LSI internal blocks. The power supply voltage is compared with a voltage threshold, and when the power supply voltage exceeds the voltage threshold, a reset signal is level-switched. A plurality of power-on circuits for outputting delay signals to the reset signals from the plurality of power-on circuits and outputting the reset signals to the plurality of LSI internal blocks, respectively. 2. The reset circuit according to claim 1, wherein the circuits have different delay times. 6. A power supply voltage of an on-board power supply is compared with a voltage threshold, and when the power supply voltage exceeds the voltage threshold,
A power-on circuit for switching the level of the reset signal and outputting the same, and a delay circuit for giving a delay time to the reset signal, which are connected in series by the same number as a plurality of LSI internal blocks,
The reset signal from the power-on circuit is transmitted to a plurality of Ls.
2. The reset circuit according to claim 1, further comprising: a reset signal delay circuit group for outputting each of the delay circuits to the SI internal block. 7. The reset circuit according to claim 6, wherein the reset signal delay circuit group sets the delay time of the delay circuit to which the reset signal is directly input from the power-on circuit to zero. 8. A reset method in which a power supply voltage is supplied from an on-board power supply and a reset signal is level-switched and output to a plurality of LSI internal blocks whose reset is released by level switching of a reset signal. A plurality of rush currents occurring in the LSI internal block, the level switching timing of the reset signal is changed so that all of the plurality of rush currents are time-separated.