CN102215034A - Flip-flop - Google Patents

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Publication number
CN102215034A
CN102215034A CN2011100893794A CN201110089379A CN102215034A CN 102215034 A CN102215034 A CN 102215034A CN 2011100893794 A CN2011100893794 A CN 2011100893794A CN 201110089379 A CN201110089379 A CN 201110089379A CN 102215034 A CN102215034 A CN 102215034A
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China
Prior art keywords
node
coupled
signal
nmos pass
grid
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CN2011100893794A
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CN102215034B (en
Inventor
简丞星
游永杰
许佳宜
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MediaTek Inc
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MediaTek Inc
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Priority claimed from US13/048,548 external-priority patent/US8471618B2/en
Application filed by MediaTek Inc filed Critical MediaTek Inc
Priority to CN201410264699.2A priority Critical patent/CN104124943B/en
Publication of CN102215034A publication Critical patent/CN102215034A/en
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Abstract

The invention provides a flip-flop. In one embodiment, the flip-flop receives a low swing clock signal, and comprises a first NMOS transistor, a first latch circuit, a second NMOS transistor, and a second latch circuit. The low swing clock signal is inverted to obtain an inverted low swing clock signal. The first NMOS transistor is coupled between a receiving node and a first node, and has a gate coupled to the inverted low swing clock signal. The first latch circuit is coupled between the first node and a second node. The second NMOS transistor is coupled between the second node and a third node. The second latch circuit is coupled between the third node and a fourth node, and generates an output signal on the fourth node.

Description

Trigger
Technical field
The present invention is relevant for trigger (flip-flop), particularly about receiving the trigger of the low amplitude of oscillation (swing) clock signal.
Background technology
Trigger is the circuit with two stable states, and it can be used to storing state message.Two stable states of trigger are the value of being expressed as " 0 " and " 1 " respectively.Trigger is controlled by clock signal usually.According to the value of input signal, clock can cause trigger to change when changing (transition) or keep its output signal.Some trigger changes output in the rising edge of clock signal, and the other trigger changes output in the drop edge of clock signal.
Please refer to Fig. 1, Fig. 1 is the circuit diagram of conventional trigger device 200.Conventional trigger device 200 can comprise reverser 231,232,233, and 234, transfer gate circuit (passing gate circuit) 202 and 206, and latch cicuit 204 and 208.High amplitude of oscillation clock signal C K ' feeds back to reverser 251.Oppositely (be designated hereinafter simply as: reverse clock signal C KB '), and follow reverse clock signal C KB ' oppositely with clocking CK1 ' to produce reverse clock signal C KB ' by reverser 253 with high amplitude of oscillation clock signal C K ' for reverser 251.
Latch cicuit 204 comprises two reversers 213,214 and comprises P-type mos (P-Metallic Oxide Semiconductor, be designated hereinafter simply as PMOS) transmission gate circuit (transmission gate) of transistor 215 and N type metal oxide semiconductor (N-Metallic Oxide Semiconductor is designated hereinafter simply as NMOS) transistor 216.Latch cicuit 208 comprises two reversers 223,224 and comprises PMOS transistor 225 and the gate circuit of nmos pass transistor 226.Reverser 231 with data-signal oppositely to produce reverse data-signal.When clock signal CK1 ' is positioned at logic low and oppositely clock signal C KB ' is positioned at logic high, transfer gate circuit 202 transmits the node 217 of reverse data-signal to latch cicuit 204, comprise that the transmission gate circuit of transistor 215 and 216 cuts off the feedback path of latch cicuit 204, transfer gate circuit 206 is closed, and comprises that the transmission gate circuit of transistor 225 and 226 keeps or set up the feedback path of latch cicuit 208.Then, latch cicuit 204 receives reverse data-signal from node 217, and oppositely this reverse data-signal with in node 218 generation data-signals.When reverse clock signal C KB ' is positioned at logic low and clock signal C K1 ' is positioned at logic high, transfer gate circuit 202 is closed, comprise that the transmission gate circuit of transistor 215 and 216 keeps or set up the feedback path of latch cicuit 204, transfer gate circuit 206 is passed to the node 227 of latch cicuit 208 with the data-signal of node 218, and comprises that the transmission gate circuit of transistor 225 and 226 cuts off the feedback path of latch cicuit 208.Latch cicuit 208 receives data-signals from node 227, and oppositely this data-signal to produce a reverse data-signal in node 228.Then, reverser 232 reverse these reverse data-signals to be producing a data-signal in output node Q, and reverser 233 and 234 data-signals that this is reverse are passed to reverse output node (inverted output node) QB.
The vibration of clock signal can cause power consumption.The clock signal of ifs circuit is with low amplitude of oscillation voltage oscillation, and then the power consumption meeting of circuit reduces a lot.Because total electric weight of portable equipment is limited, therefore, the power consumption that reduces portable equipment is very important.Therefore, the clock signal that is used for having the circuit of limited electric weight should be designed to have low amplitude of oscillation level, to reduce power consumption.But traditional trigger 200 can not directly receive low amplitude of oscillation clock signal. Transfer gate circuit 202 and 206 comprises PMOS transistor 211 and 221 respectively, and PMOS transistor 211 has the grid that is coupled to clock signal C K1 ', and PMOS transistor 221 has the grid that is coupled to reverse clock signal C KB '; And latch cicuit 204 and 208 also comprises PMOS transistor 215 and 225 respectively, and PMOS transistor 215 has the grid that is coupled to reverse clock signal C KB ', and PMOS transistor 225 has the grid that is coupled to clock signal C K1 '.If clock signal C K1 ' and oppositely clock signal C KB ' be low amplitude of oscillation clock signal, PMOS transistor 211,215,221, and 225 can not be closed fully by the low-voltage of clock signal.Therefore, traditional trigger 200 can not normally move under low amplitude of oscillation clock signal.Therefore, be fed to the conventional trigger device in low amplitude of oscillation clock signal, the voltage level of low amplitude of oscillation clock signal must amplify via being low to moderate high level transducer (low-to-high level shifter).Level translator can increase the manufacturing cost of circuit.Can receive low amplitude of oscillation clock signal if be used for the new trigger of circuit, then can not use to be low to moderate the high level transducer to reduce the manufacturing cost of circuit.Therefore, need a kind of new trigger that can receive low amplitude of oscillation clock signal.
Summary of the invention
For power consumption that reduces portable equipment and the manufacturing cost that reduces circuit, the invention provides a kind of trigger, it can receive low amplitude of oscillation clock signal.
The invention provides a kind of trigger, receive low amplitude of oscillation clock signal, wherein, described low amplitude of oscillation clock signal is reversed to obtain oppositely low amplitude of oscillation clock signal, described trigger comprises: first nmos pass transistor, be coupled between receiving node and the first node, and have the grid that is coupled to described oppositely low amplitude of oscillation clock signal, and when described oppositely low amplitude of oscillation clock signal is positioned at logic high, will be passed to described first node from the data-signal of described receiving node; First latch cicuit is coupled between described first node and the Section Point, with described data-signal oppositely to produce reverse data-signal to described Section Point; Second nmos pass transistor, be coupled between described Section Point and the 3rd node, has the grid that is coupled to described low amplitude of oscillation clock signal, and when described low amplitude of oscillation clock signal is positioned at described logic high, will be passed to described the 3rd node from the described reverse data-signal of described Section Point; And second latch cicuit, be coupled between described the 3rd node and the 4th node, described reverse data-signal is oppositely outputed signal to described the 4th node with generation.
The present invention provides a kind of trigger in addition, receive low amplitude of oscillation clock signal, wherein, described low amplitude of oscillation clock signal is reversed to obtain oppositely low amplitude of oscillation clock signal, described trigger comprises: first nmos pass transistor, be coupled between receiving node and the first node, has the grid that is coupled to described oppositely low amplitude of oscillation clock signal, receive data-signal from described receiving node, and when described oppositely low amplitude of oscillation clock signal is positioned at logic high, will be passed to described first node from the described data-signal of described receiving node; First latch cicuit is coupled between described first node and the Section Point, when reset signal is positioned at described logic high, with described data-signal oppositely to produce the data-signal handled to described Section Point; Second nmos pass transistor, be coupled between described Section Point and the 3rd node, has the grid that is coupled to described low amplitude of oscillation clock signal, when described low amplitude of oscillation clock signal is positioned at described logic high, will be passed to described the 3rd node from the described data-signal of having handled of described Section Point; And second latch cicuit, be coupled between described the 3rd node and the 4th node, when described reset signal is positioned at described logic high, the described data-signal of having handled is oppositely outputed signal to described the 4th node with generation, and when described reset signal is positioned at logic low, produce logic high voltage to export described the 4th node to as described output signal.
The present invention provides a kind of trigger in addition, receive low amplitude of oscillation clock signal, wherein, described low amplitude of oscillation clock signal is reversed to obtain oppositely low amplitude of oscillation clock signal, comprise: first nmos pass transistor, be coupled between receiving node and the first node, have the grid that is coupled to described oppositely low amplitude of oscillation clock signal, and when described oppositely low amplitude of oscillation clock signal is positioned at logic high, will be passed to described first node from the data-signal of described receiving node; First latch cicuit is coupled between described first node and the Section Point, when signalization is positioned at described logic high, with described data-signal oppositely to produce the data-signal handled to described Section Point; Second nmos pass transistor, be coupled between described Section Point and the 3rd node, has the grid that is coupled to described low amplitude of oscillation clock signal, and when described low amplitude of oscillation clock signal is positioned at described logic high, will be passed to described the 3rd node from the described data-signal of having handled of described Section Point; And second latch cicuit, be coupled between described the 3rd node and the 4th node, when described signalization is positioned at described logic low, produces logic low-voltage and export described the 4th node to as output signal.
The present invention provides a kind of trigger in addition, receive low amplitude of oscillation clock signal, wherein, described low amplitude of oscillation clock signal is reversed to obtain oppositely low amplitude of oscillation clock signal, described trigger comprises: first nmos pass transistor, be coupled between receiving node and the first node, and have the grid that is coupled to described oppositely low amplitude of oscillation clock signal, and when described oppositely low amplitude of oscillation clock signal is positioned at logic high, will be passed to described first node from the data-signal of described receiving node; First latch cicuit, be coupled between described first node and the Section Point, when signalization is positioned at described logic high, with described data-signal oppositely to produce the data-signal handled to described Section Point, and when described signalization is positioned at logic low, produce logic high voltage to export described Section Point to as the described data-signal of having handled; Second nmos pass transistor, be coupled between described Section Point and the 3rd node, has the grid that is coupled to described low amplitude of oscillation clock signal, and when described low amplitude of oscillation clock signal is positioned at described logic high, will be passed to described the 3rd node from the described data-signal of having handled of described Section Point; And second latch cicuit, be coupled between described the 3rd node and the 4th node, when reset signal is positioned at described logic high, the described data-signal of having handled is oppositely outputed signal to described the 4th node with generation, and when described reset signal is positioned at described logic low, produce logic high voltage with described output signal as described the 4th node.
Trigger provided by the present invention can receive low amplitude of oscillation clock signal, reduces the power consumption that is caused by the vibration of clock signal.Utilize trigger provided by the present invention, can effectively reduce the power consumption of portable equipment, and can not use and be low to moderate the high level transducer to reduce the manufacturing cost of circuit.
Description of drawings
Fig. 1 is the circuit diagram of conventional trigger device 200.
Fig. 2 is comprising of one embodiment of the invention of a plurality of schematic diagrames that can receive the circuit 300 of the trigger that hangs down amplitude of oscillation clock signal.
Fig. 3 is the circuit diagram of the trigger 400 that can receive low amplitude of oscillation clock signal of another embodiment of the present invention.
Fig. 4 is the circuit diagram of the trigger 410 that can receive low amplitude of oscillation clock signal of another embodiment of the present invention.
Fig. 5 A be another embodiment of the present invention comprise that can be accelerated the circuit diagram of trigger 500 that signal produces the input circuit 540 of speed.
Fig. 5 B be another embodiment of the present invention comprise that can be accelerated the circuit diagram of trigger 510 that signal produces the input circuit 540 ' of speed.
Fig. 5 C can accelerate signal for two to produce the input circuit 540 of speed and the circuit diagram of 550 trigger 520 comprising of one embodiment of the invention.
Fig. 5 D can accelerate signal for two to produce the input circuit 540 of speed and the circuit diagram of 550 ' trigger 530 comprising of another embodiment of the present invention.
Fig. 5 E is the circuit diagram of the trigger that comprises two input circuits 560 of another embodiment of the present invention.
Fig. 5 F is the circuit diagram of the trigger that comprises two input circuits 570 of another embodiment of the present invention.
Fig. 5 G is the circuit diagram of the trigger that comprises two input circuits 580 of another embodiment of the present invention.
Fig. 5 H is the circuit diagram of the trigger that comprises two input circuits 590 of another embodiment of the present invention.
Fig. 6 is the circuit diagram of trigger 600 of the reception reset signal of another embodiment of the present invention.
Fig. 7 is the circuit diagram of trigger 700 of the reception signalization of another embodiment of the present invention.
Fig. 8 is the circuit diagram of the trigger 800 of the reception reset signal of another embodiment of the present invention and signalization.
Embodiment
Please refer to Fig. 2, Fig. 2 is comprising of one embodiment of the invention of a plurality of schematic diagrames that can receive the circuit 300 of the trigger that hangs down amplitude of oscillation clock signal.Circuit 300 comprises low amplitude of oscillation clock buffer 311,312,313 and 314, low amplitude of oscillation gate circuit 324 and 325, and high to low transition device 321,322 and 323.In addition, circuit 300 comprises three triggers 331,332 and 333 that can receive low amplitude of oscillation clock signal.The voltage level of the source clock signal C 0 that is produced by root level translator 321 from high to low reduces to produce low amplitude of oscillation clock signal C 1.Then, low amplitude of oscillation clock signal C 1 is sent to low amplitude of oscillation clock buffer 311,312 and 313 to produce low amplitude of oscillation clock signal C 2, C3 and C4.Because trigger 331,332 and 333 can receive low amplitude of oscillation clock signal, then, low amplitude of oscillation clock signal C 2, C3 and C4 can be transferred to trigger 331,332 and 333 respectively without any intervention that is low to moderate the high level transducer.Compare with traditional circuit, circuit 300 does not need to be low to moderate the high level transducer and will hang down amplitude of oscillation clock signal and be converted to high amplitude of oscillation clock signal and can normally move yet; Therefore, the manufacturing cost of circuit 300 will reduce.In certain embodiments, height to low transition device 321,322 and 323 can be replaced by buffer.
Please refer to Fig. 3, Fig. 3 is the circuit diagram of the trigger 400 that can receive low amplitude of oscillation clock signal of another embodiment of the present invention.Low amplitude of oscillation clock signal C K vibrates and can be reversed device 431 and oppositely oppositely hangs down amplitude of oscillation clock signal C KB to produce one, and reverser 433 then will oppositely hang down amplitude of oscillation clock signal C KB oppositely with clocking CK1.Trigger 400 can comprise reverser 401,403, and 405 and 407, transfer gate circuit 402 and 406, and latch cicuit 404 and 408.In certain embodiments, reverser 401,403,405 and 407 can be omitted.Reverser 401 is coupled between input node and the receiving node 409, from input node receiving inputted signal D, and oppositely this input signal D to produce data-signal to receiving node 409.According to present embodiment, transfer gate circuit 402 is a nmos pass transistor, is coupled between receiving node 409 and the node 415, and has the grid that is coupled to oppositely low amplitude of oscillation clock signal C KB.When oppositely hanging down amplitude of oscillation clock signal C KB is logic high, and transfer gate circuit 402 (nmos pass transistor) is passed to node 415 with data-signal by receiving node 409.Latch cicuit 404 is coupled between node 415 and the node 416, receives data-signals from node 415, and oppositely this data-signal to produce a reverse data-signal to node 416.According to present embodiment, transfer gate circuit 406 is a nmos pass transistor, is coupled between node 416 and the node 425, and has the grid that is coupled to low amplitude of oscillation clock signal C K.When low amplitude of oscillation clock signal C K is positioned at logic high, transfer gate circuit 406 (nmos pass transistor) is delivered to node 425 with reverse data-signal by node 416.Latch cicuit 408 is coupled between node 425 and the node 426, receive reverse data-signal from node 425, and oppositely this reverse data-signal outputs signal to node 426 to produce one.Reverser 403 is coupled between node 426 and the output node Q, then, oppositely from the output signal of node 426 to produce a reverse output node Q that outputs signal to.Reverser 405 and 407 coupled in series receive output signals to produce final output signal to reverse output node QB from node 426 between node 426 and reverse output node QB.
In one embodiment, latch cicuit 404 comprises: PMOS transistor 411, reverser 414, and two nmos pass transistors 412 and 413.Reverser 414 is coupled between node 415 and 416, with the data-signal of node 415 oppositely to produce a reverse data-signal to node 416.PMOS transistor 411 is coupled between voltage source DVDD and the node 415, and the grid of PMOS transistor 411 is coupled to node 416.When the voltage of node 416 is positioned at logic low, PMOS transistor 411 is unlocked and is promoted to the level of voltage source DVDD with the voltage with node 415.The drain electrode of nmos pass transistor 412 is coupled to node 415, and grid is coupled to node 416.Nmos pass transistor 413 is coupled between the source electrode and ground voltage DVSS of nmos pass transistor 412, and the grid of nmos pass transistor 413 is coupled to low amplitude of oscillation clock signal C K.When low amplitude of oscillation clock signal C K is positioned at logic high, and the voltage of node 416 is positioned at logic high, and nmos pass transistor 412 and 413 is all opened the level that is low to moderate ground voltage DVSS with the voltage drop with node 415.
In one embodiment, latch cicuit 408 comprises PMOS transistor 421, reverser 424, and two nmos pass transistors 422 and 423.Reverser 424 is coupled between node 425 and 426, and oppositely the reverse data-signal from node 425 outputs signal to node 426 with generation.PMOS transistor 421 is coupled between voltage source DVDD and the node 425, and the grid of PMOS transistor 421 is coupled to node 426.When the voltage of node 426 is positioned at logic low, PMOS transistor 421 is opened, and is promoted to the level of voltage source DVDD with the voltage with node 425.The drain electrode of nmos pass transistor 422 is coupled to node 425, and grid is coupled to node 426.Nmos pass transistor 423 is coupled between the source electrode and ground voltage DVSS of nmos pass transistor 422, and the grid of nmos pass transistor 423 is coupled to oppositely low amplitude of oscillation clock signal C KB.When low amplitude of oscillation clock signal C KB is positioned at logic high, and the voltage of node 426 is positioned at logic high, and then nmos pass transistor 422 and 423 is all opened the level that is low to moderate ground voltage DVSS with the voltage drop with node 425.
Be transfused to as a new input signal D, oppositely low amplitude of oscillation clock signal C KB can be positioned at logic high and low amplitude of oscillation clock signal C K can be positioned at logic low.Then, transfer gate circuit 402 will be passed to the node 415 of latch cicuit 404 from the data-signal of receiving node 409, nmos pass transistor 413 cuts off the feedback path of latch cicuit 404, and transfer gate circuit 406 is closed, and nmos pass transistor 423 keeps or set up the feedback path of latch cicuit 408.Then, latch cicuit 404 receives data-signals from node 415, and oppositely this data-signal to produce reverse data-signal to node 416.Because transfer gate circuit 406 is closed, therefore, latch cicuit 408 will latch reverse data-signal on last stage, rather than receive the reverse data-signal corresponding to new input signal D.Therefore, the value of the reverse output signal of output node Q will equal the value of an input signal rather than the value of new input signal D.
Next, oppositely low amplitude of oscillation clock signal C KB can change into and be positioned at logic low, and low amplitude of oscillation clock signal C K can be positioned at logic high.Then, transfer gate circuit 402 is closed, nmos pass transistor 413 keeps or sets up the feedback path of latch cicuit 404, and the data-signal that transfer gate circuit 406 will be reverse is passed to the node 425 of latch cicuit 408 by node 416, and nmos pass transistor 423 cuts off the feedback path of latch cicuits 408.Then, latch cicuit 408 reverse these reverse data-signals output signal to node 426 with generation.Then, reverser 403 will be from the output signal of node 426 oppositely producing the reverse output node Q that outputs signal to, and the value of the reverse output signal of output node Q this moment equals the value of new input signal D.
The circuit of conventional trigger device 200 as shown in Figure 1 only can run under the clock signal C K1 ' and CKB ' with normal amplitude of oscillation level.If the amplitude of oscillation level drops of clock signal C K1 ' and CKB ' is low to moderate low level, then when clock signal CK1 ' and CKB ' vibration when having low level peak value, transfer gate circuit 202 and 206 PMOS transistor 211 and 221 can not be fully closed, therefore, transfer gate circuit 202 and 206 can not normally move under low amplitude of oscillation clock signal C K1 and CKB.Similarly, if the amplitude of oscillation level drops of clock signal C K1 ' and CKB ' is low to moderate low level, then when clock signal CK1 ' and CKB ' vibration when having low level peak value, latch cicuit 204 and 208 PMOS transistor 215 and 225 can not be fully closed, therefore, latch cicuit 204 and 208 can not normally move under low amplitude of oscillation clock signal C K1 and CKB.Opposite, the circuit of trigger 400 as shown in Figure 3 can normally run under the clock signal C KB and CK with low amplitude of oscillation level.Because transfer gate circuit 402 and 406 only comprises nmos pass transistor 402 and 406, and do not comprise the PMOS transistor, when low amplitude of oscillation clock signal C KB and CK vibration when having low level peak value, nmos pass transistor 402 and 406 can be closed fully, therefore, transfer gate circuit 402 and 406 can normally move under low amplitude of oscillation clock signal C K and CKB.In addition, different with the latch cicuit 204 of conventional trigger device 200 and 208 is, because latch cicuit 404 of the present invention and 408 does not comprise the PMOS transistor by low amplitude of oscillation clock signal C K and CKB control, therefore, latch cicuit 404 and 408 can normally move according to low amplitude of oscillation clock signal C K and CKB.Therefore, trigger 400 provided by the present invention can normally move according to low amplitude of oscillation clock signal C K and CKB.
Please refer to Fig. 4, Fig. 4 is the circuit diagram of the trigger 410 that can receive low amplitude of oscillation clock signal of another embodiment of the present invention.Trigger 410 shown in Figure 4 comprises the circuit element similar to trigger shown in Figure 3 400.Similar circuit element has identical Reference numeral in the trigger 410 and 400.The difference of trigger 410 shown in Figure 4 and trigger 400 shown in Figure 3 is latch cicuit 404 ' and 408 '.Latch cicuit 404 ' as shown in Figure 4 comprises two nmos pass transistors 412 ' and 413 ', wherein the grid of nmos pass transistor 412 ' is coupled to low amplitude of oscillation clock signal C K, rather than node 416, and the grid of nmos pass transistor 413 ' is coupled to node 416, rather than low amplitude of oscillation clock signal C K.Yet latch cicuit 404 ' shown in Figure 4 has similar function to latch cicuit shown in Figure 3 404.Latch cicuit 408 ' as shown in Figure 4 comprises two nmos pass transistors 422 ' and 423 ', wherein, the grid of nmos pass transistor 422 ' is coupled to oppositely low amplitude of oscillation clock signal C KB, rather than node 426, and the grid of nmos pass transistor 423 ' is coupled to node 426, rather than oppositely low amplitude of oscillation clock signal C KB.Yet latch cicuit 408 ' shown in Figure 4 has similar function to latch cicuit shown in Figure 3 408.
Please refer to Fig. 5 A, Fig. 5 A be one embodiment of the invention comprise that can be accelerated the circuit diagram of trigger 500 that signal produces the input circuit 540 of speed (signal generation speed).Low amplitude of oscillation clock signal C K vibrates and can be reversed device 531 and oppositely oppositely hangs down amplitude of oscillation clock signal C KB to produce one, and reverser 533 then will oppositely hang down amplitude of oscillation clock signal C KB oppositely with clocking CK1.Similar to trigger 400 shown in Figure 3, trigger 500 is by low amplitude of oscillation clock signal C K and CKB control.Trigger 500 can comprise reverser 501,503,505, and 507, two transfer gate circuit 502 and 506, and two latch cicuits 504 and 508, wherein, the PMOS transistor 511 and 521 in the trigger 500, reverser 514 and 524 and node 525 and trigger 400 in PMOS transistor 411 and 421, reverser 414 and 424 and node 425 similar.In certain embodiments, reverser 501,503,505, and 507 can be omitted.Trigger 500 further comprises input circuit 540, and input circuit 540 is used to enable latch cicuit 508 to quicken to produce output signal in node 526.Input circuit 540 is coupled between node 516 and the node 526, and it comprises two nmos pass transistors 541 and 542.The grid of nmos pass transistor 541 is coupled to node 516, and drain electrode is coupled to node 526.Nmos pass transistor 542 is coupled between the source electrode and ground voltage DVSS of nmos pass transistor 541, and the grid of nmos pass transistor 542 is coupled to low amplitude of oscillation clock signal C K.When the voltage of node 516 and low amplitude of oscillation clock signal C K all was positioned at logic high, nmos pass transistor 541 and 542 was unlocked and is low to moderate ground voltage DVSS with the voltage drop with node 526, outputed signal to node 526 thereby quicken to produce.In certain embodiments, nmos pass transistor 541 and 542 position can be exchanged, and the grid of nmos pass transistor 541 still is coupled to node 516, and the grid of nmos pass transistor 542 still is coupled to low amplitude of oscillation clock signal C K.
Please refer to Fig. 5 B, Fig. 5 B be another embodiment of the present invention comprise that can be accelerated the circuit diagram of trigger 510 that signal produces the input circuit 540 ' of speed.Trigger 510 has and the similar circuit structure of the trigger 500 shown in Fig. 5 A.Similar circuit element has identical Reference numeral in trigger 500 and the trigger 510.The difference of trigger 510 and trigger 500 is that input circuit 540 ' is different with the input circuit 540 of Fig. 5 A, and wherein, input circuit 540 ' enables latch cicuit 508 and outputs signal to node 526 to quicken to produce.Input circuit 540 ' is coupled between node 515 and the node 526, and comprises PMOS transistor 541 ' and nmos pass transistor 542 '.The grid of PMOS transistor 541 ' is coupled to node 515, and source electrode is coupled to node 526.Nmos pass transistor 542 ' is coupled between the drain electrode and ground voltage DVSS of PMOS transistor 541 ', and the grid of nmos pass transistor 542 ' is coupled to low amplitude of oscillation clock signal C K.When the voltage of node 515 is positioned at logic low, and low amplitude of oscillation clock signal C K is positioned at logic high, PMOS transistor 541 ' and nmos pass transistor 542 ' all are unlocked and are low to moderate ground voltage DVSS with the voltage drop with node 526, output signal to node 526 thereby quicken to produce.Therefore, the nmos pass transistor 541 of the input circuit shown in Fig. 5 A 540 can be substituted by the PMOS transistor 541 ' of the input circuit 540 ' shown in Fig. 5 B.In certain embodiments, transistor 541 ' and 542 ' position can exchange, and the grid of PMOS transistor 541 ' still is coupled to node 515, and the grid of nmos pass transistor 542 ' still is coupled to low amplitude of oscillation clock signal C K.
Please refer to Fig. 5 C, Fig. 5 C can accelerate signal for two to produce the input circuit 540 of speed and the circuit diagram of 550 trigger 520 comprising of one embodiment of the invention.Trigger 520 has and trigger 500 similar circuit configuration shown in Fig. 5 A.Similar circuit element has identical Reference numeral in trigger 500 and the trigger 520.The difference of trigger 520 and trigger 500 is input circuit 550, and input circuit 550 enables latch cicuit 504 to quicken producing reverse data-signal to node 516.Input circuit 550 is coupled between node 509 and the node 516, and comprises two nmos pass transistors 551 and 552.The grid of nmos pass transistor 551 is coupled to node 509, and drain electrode is coupled to node 516.Nmos pass transistor 552 is coupled between the source electrode and ground voltage DVSS of nmos pass transistor 551, and the grid of nmos pass transistor 552 is coupled to oppositely low amplitude of oscillation clock signal C KB.When the voltage of node 509 and oppositely low amplitude of oscillation clock signal C KB all are positioned at logic high, nmos pass transistor 551 and 552 is all opened with the voltage drop with node 516 and is low to moderate ground voltage DVSS, thereby quickens to produce reverse data-signal to node 516.In certain embodiments, nmos pass transistor 541 and 542 position can exchange, and the grid of nmos pass transistor 541 still is coupled to node 516, and the grid of nmos pass transistor 542 still is coupled to low amplitude of oscillation clock signal C K.In certain embodiments, nmos pass transistor 551 and 552 position can exchange, and the grid of nmos pass transistor 551 still is coupled to node 509, and the grid of nmos pass transistor 552 still is coupled to oppositely low amplitude of oscillation clock signal C KB.
Please refer to Fig. 5 D, Fig. 5 D can accelerate signal for two to produce the input circuit 540 of speed and the circuit diagram of 550 ' trigger 530 comprising of another embodiment of the present invention.Trigger 530 has and trigger 500 similar circuit configuration shown in Fig. 5 A.Similar circuit element has identical Reference numeral in trigger 500 and the trigger 530.The difference of trigger 530 and trigger 500 is input circuit 550 ', and input circuit 550 ' enables latch cicuit 504 to quicken producing reverse data-signal to node 516.Input circuit 550 ' is coupled between node 519 and the node 516, and comprises PMOS transistor 551 ' and nmos pass transistor 552 '.The grid of PMOS transistor 551 ' is coupled to node 519, and source electrode is coupled to node 516.Nmos pass transistor 552 ' is coupled between the drain electrode and ground voltage DVSS of PMOS transistor 551 ', and the grid of nmos pass transistor 552 ' is coupled to oppositely low amplitude of oscillation clock signal C KB.When the voltage of node 519 is positioned at logic low and oppositely low amplitude of oscillation clock signal C KB is positioned at logic high, PMOS transistor 551 ' and nmos pass transistor 552 ' are all opened with the voltage drop with node 516 and are low to moderate ground voltage DVSS, output signal to node 516 thereby quicken to produce.Therefore, the nmos pass transistor 551 of the input circuit shown in Fig. 5 C 550 can be replaced by the PMOS transistor 551 ' of the input circuit 550 ' shown in Fig. 5 D.In certain embodiments, nmos pass transistor 541 and 542 position can exchange, and the grid of nmos pass transistor 541 still is coupled to node 516, and the grid of nmos pass transistor 542 still is coupled to low amplitude of oscillation clock signal C K.In certain embodiments, transistor 551 ' and 552 ' position can exchange, and the grid of PMOS transistor 551 ' still is coupled to node 519, and the grid of nmos pass transistor 552 ' still couples oppositely low amplitude of oscillation clock signal C KB.
Fig. 5 E is the circuit diagram of the trigger that comprises two input circuits 560 of another embodiment of the present invention.Fig. 5 F is the circuit diagram of the trigger that comprises two input circuits 570 of another embodiment of the present invention.Except the input circuit 540 of trigger 520 is replaced by the input circuit 540 ' of Fig. 5 B, the trigger 560 shown in Fig. 5 E has and trigger 520 similar circuit configuration shown in Fig. 5 C.Except the input circuit 540 of trigger 530 is replaced by the input circuit 540 ' of Fig. 5 B, the trigger 570 shown in Fig. 5 F has and trigger 530 similar circuit configuration shown in Fig. 5 D.In certain embodiments, transistor 541 ' and 542 ' position can exchange, and the grid of PMOS transistor 541 ' still is coupled to node 515, and the grid of nmos pass transistor 542 ' still is coupled to low amplitude of oscillation clock signal C K.In certain embodiments, nmos pass transistor 551 among Fig. 5 E and 552 position can exchange, and the grid of nmos pass transistor 551 still is coupled to node 509, and the grid of nmos pass transistor 552 still is coupled to oppositely low amplitude of oscillation clock signal C KB.In certain embodiments, transistor 551 ' among Fig. 5 F and 552 ' position can exchange, and the grid of PMOS transistor 551 ' still is coupled to node 519, and the grid of nmos pass transistor 552 ' still is coupled to oppositely low amplitude of oscillation clock signal C KB.
Fig. 5 G is the circuit diagram of the trigger that comprises two input circuits 580 of another embodiment of the present invention.Fig. 5 H is the circuit diagram of the trigger that comprises two input circuits 590 of another embodiment of the present invention.Except the input circuit 550 ' and 540 ' of trigger 570 is replaced by respectively the input circuit 582 and 584 of Fig. 5 G, the trigger 580 shown in Fig. 5 G has and trigger 570 similar circuit configuration shown in Fig. 5 F.Input circuit 582 comprises nmos pass transistor 586.Nmos pass transistor 586 is coupled between input node 519 and the node 516, and the grid of nmos pass transistor 586 is coupled to oppositely low amplitude of oscillation clock signal C KB.When oppositely low amplitude of oscillation clock signal C KB was positioned at logic high, nmos pass transistor 586 was unlocked being coupled to node 519 and node 516, thereby quickens the signal transmission between the node 519 and 516.Input circuit 584 comprises nmos pass transistor 588.Nmos pass transistor 588 is coupled between node 515 and the node 526, and the grid of nmos pass transistor 588 is coupled to low amplitude of oscillation clock signal C K.When low amplitude of oscillation clock signal C K is positioned at logic high, nmos pass transistor 588 is unlocked being coupled to node 515 and node 526, thereby quickens the signal transmission between the node 515 and 526.Except the nmos pass transistor 586 and 588 of the input circuit 582 of the trigger 580 shown in Fig. 5 G and 584 was replaced by the input circuit 582 ' and 584 ' PMOS transistor 586 ' and 588 ' of Fig. 5 H respectively, the trigger 590 shown in Fig. 5 H had and trigger 580 similar circuit configuration shown in Fig. 5 G.When low amplitude of oscillation clock signal C K is positioned at logic low, PMOS transistor 586 ' is unlocked being coupled to node 519 and node 516, thereby quickens the signal transmission between the node 519 and 516.When reverse low amplitude of oscillation clock signal C KB is positioned at logic low, PMOS transistor 588 ' is unlocked being coupled to node 515 and node 526, thereby quickens the signal transmission between the node 515 and 526.
In certain embodiments, nmos pass transistor 512 in the latch cicuit shown in Fig. 5 A to Fig. 5 H 504 and 513 nmos pass transistors 412 ' and 413 ' that can be replaced by in the latch cicuit 404 ' shown in Figure 4.And nmos pass transistor 522 in the latch cicuit 508 shown in Fig. 5 A to Fig. 5 H and 523 nmos pass transistors 422 ' and 423 ' that can be replaced by in the latch cicuit 408 ' shown in Figure 4.
Please refer to Fig. 6, Fig. 6 is the circuit diagram of trigger 600 of the reception reset signal (reset bar signal) of another embodiment of the present invention.Trigger 600 has and trigger 580 similar circuit configuration and the circuit function shown in Fig. 5 G.Low amplitude of oscillation clock signal C K vibrates and can be reversed device 631 and oppositely oppositely hangs down amplitude of oscillation clock signal C KB to produce one, and reverser 633 then will oppositely hang down amplitude of oscillation clock signal C KB oppositely with clocking CK1.In one embodiment, trigger 600 comprises: reverser 601,603,605, and 607, two transfer gate circuit 602 and 606, and two latch cicuits 604 and 608.In certain embodiments, reverser 601,603,605, and 607 can be omitted.When reset signal RB was positioned at logic low, reset signal RB was used to the output voltage of output node Q is reset to logic low-voltage.According to present embodiment, transfer gate circuit 602 is a nmos pass transistor, and it is coupled between receiving node 609 and the node 615, has one and is coupled to the grid that oppositely hangs down amplitude of oscillation clock signal C KB.The data-signal that transfer gate circuit 602 receives from receiving node 609, and when oppositely low amplitude of oscillation clock signal C KB is positioned at logic high, will be passed to node 615 from the data-signal of receiving node 609.When oppositely low amplitude of oscillation clock signal C KB was positioned at logic high, transfer gate circuit 602 (nmos pass transistor) was unlocked will be passed to node 615 from the data-signal of receiving node 609.Latch cicuit 604 is coupled between node 615 and the node 616, when reset signal RB is positioned at logic high, receives the data-signal from node 615, and with this data-signal oppositely to produce the data-signal handled to node 616.According to present embodiment, transfer gate circuit 606 is a nmos pass transistor, be coupled between node 616 and the node 625, has the grid that is coupled to low amplitude of oscillation clock signal C K, and when low amplitude of oscillation clock signal C K is positioned at logic high, will be passed to node 625 from the data-signal of having handled of node 616.When low amplitude of oscillation clock signal C K is positioned at logic high, transfer gate circuit 606 (nmos pass transistor) is unlocked being passed to node 625 from the data-signal of having handled of node 616.Latch cicuit 608 is coupled between node 625 and the node 626, receive the data-signal of having handled from node 625, and when reset signal RB is positioned at logic high, the data-signal of having handled is oppositely outputed signal to node 626 to produce one, and when reset signal RB is positioned at logic low, produce a logic high voltage to node 626.When reset signal RB was positioned at logic low, latch cicuit 608 produced a logic high voltage with as the output signal on the node 626, and reverser 603 with the logic high voltage on the node 626 oppositely to produce a logic low-voltage to output node Q.
Latch cicuit 608 has the combination similar circuit configuration with latch cicuit 508 shown in Fig. 5 G and input circuit 584.The difference of the combination of latch cicuit 608 and latch cicuit 508 and input circuit 584 is: latch cicuit 608 has and non-(NAND) door 624.624 couples of reset signal RB of NAND gate and carry out NOT-AND operation from the data-signal of having handled of node 625 output signal to node 626 to produce one.Therefore, RB is positioned at logic low when reset signal, and latch cicuit 608 produces a logic high voltage and exports node 626 to as output signal.
Latch cicuit 604 has the combination similar circuit configuration with latch cicuit 504 shown in Fig. 5 G and input circuit 582.The difference of the combination of latch cicuit 604 and latch cicuit 504 and input circuit 582 is: latch cicuit 604 has or non-(NOR) door 614.614 pairs of reverse reset signals of NOR gate and carry out NOR operation from the data-signal of node 615 are to produce the data-signal handled to node 616.Therefore, RB is positioned at logic high when reset signal, and NOR gate 614 can be used as a reverser and comes oppositely data-signal from node 615, to produce the data-signal handled to node 616.Another difference of the combination of latch cicuit 604 and latch cicuit 504 and input circuit 582 is: the nmos pass transistor 617 of latch cicuit 604 is coupled between the drain electrode of node 616 and nmos pass transistor 618.The grid of nmos pass transistor 617 is coupled to reset signal RB.RB is positioned at logic low when reset signal, and nmos pass transistor 617 is closed the data path to disconnect from node 619 to node 616.
RB is positioned at logic high when reset signal, and when a new input signal D input was arranged, oppositely low amplitude of oscillation clock signal C KB can be positioned at logic high, and low amplitude of oscillation clock signal C K can be positioned at logic low.Then, transfer gate circuit (nmos pass transistor) 602 is passed to data-signal the node 615 of latch cicuit 604 from receiving node 609, nmos pass transistor 613 cuts off the feedback path of latch cicuit 604, transfer gate circuit (nmos pass transistor) 606 is closed, and nmos pass transistor 623 keeps or set up the feedback path of latch cicuit 608.Then, latch cicuit 604 receives data-signals from node 615, and with this data-signal oppositely to produce a reverse data-signal to node 616.Because transfer gate circuit 606 is closed, latch cicuit 608 will latch reverse data-signal on last stage, rather than receive the reverse data-signal corresponding to new input signal D.Therefore, the value of the reverse output signal of output node Q will equal the value of an input signal rather than the value of new input signal D.Next, oppositely low amplitude of oscillation clock signal C KB can be changed to being positioned at logic low and low amplitude of oscillation clock signal C K can be positioned at logic high.Then, transfer gate circuit 602 is closed, nmos pass transistor 613 keeps or sets up the feedback path of latch cicuit 604, transfer gate circuit 606 will be passed to the node 625 of latch cicuit 608 from the reverse data-signal of node 616, and nmos pass transistor 623 cuts off the feedback path of latch cicuit 608.Latch cicuit 608 then reverse reverse data-signals output signal to node 626 to produce one.Reverser 603 then with the output signal of node 626 oppositely producing a reverse output node Q that outputs signal to, and the value of this reverse output signal of output node Q equals the value of new input signal D.RB is positioned at logic low when reset signal, and latch cicuit 608 produces a logic high voltage to node 626, and then, the value of the signal on the output node Q is reset to logic low.
In certain embodiments, the nmos pass transistor 612 of latch cicuit 604 shown in Figure 6 and 613 can be replaced by the nmos pass transistor 412 ' and 413 ' of latch cicuit 404 ' shown in Figure 4.And the nmos pass transistor 622 of latch cicuit 608 shown in Figure 6 and 623 can be replaced by the nmos pass transistor 422 ' and 423 ' of latch cicuit 408 ' shown in Figure 4.
Please refer to Fig. 7, Fig. 7 is the circuit diagram of trigger 700 of the reception signalization (set bar signal) of another embodiment of the present invention.Trigger 700 has and trigger 580 similar circuit configuration and the circuit function shown in Fig. 5 G.Low amplitude of oscillation clock signal C K vibrates and can be reversed device 731 and oppositely oppositely hangs down amplitude of oscillation clock signal C KB to produce one, and reverser 733 then will oppositely hang down amplitude of oscillation clock signal C KB oppositely with clocking CK1.In one embodiment, trigger 700 comprises reverser 701,703,705, and 707, two transfer gate circuit 702 and 706, and two latch cicuits 704 and 708.In certain embodiments, reverser 701,703,705, and 707 can be omitted.When signalization SB was positioned at logic low, the output voltage that signalization SB is used to output node Q was set to logic high voltage.According to present embodiment, transfer gate circuit 702 is a nmos pass transistor, it is coupled between receiving node 709 and the node 715, have one and be coupled to the grid that oppositely hangs down amplitude of oscillation clock signal C KB, the data-signal that transfer gate circuit 702 receives from receiving node 709, and when oppositely low amplitude of oscillation clock signal C KB is positioned at logic high, will be passed to node 715 from the data-signal of receiving node 709.When oppositely low amplitude of oscillation clock signal C KB was positioned at logic high, transfer gate circuit 702 (nmos pass transistor) was unlocked will be passed to node 715 from the data-signal of receiving node 709.Latch cicuit 704 is coupled between node 715 and the node 716, when signalization SB is positioned at logic high, receives the data-signal from node 715, and with this data-signal oppositely to produce the data-signal handled to node 716.And when signalization SB was positioned at logic low, the data that the conduct of latch cicuit 704 generations one logic high voltage has been handled was to node 716.According to present embodiment, transfer gate circuit 706 is a nmos pass transistor, be coupled between node 716 and the node 725, has the grid that is coupled to low amplitude of oscillation clock signal C K, and when low amplitude of oscillation clock signal C K is positioned at logic high, will be passed to node 725 from the data-signal of having handled of node 716.When low amplitude of oscillation clock signal C K was positioned at logic high, transfer gate circuit 706 (nmos pass transistor) was unlocked being passed to node 725 from the data-signal of having handled of node 716.Latch cicuit 708 is coupled between node 725 and the node 726, receives the data-signal of having handled from node 725, and when signalization SB is positioned at logic high, the data-signal of having handled is oppositely outputed signal to node 726 to produce one.When signalization SB is positioned at logic low, latch cicuit 704 produces a logic high voltage to export node 716 to as the data-signal of having handled, latch cicuit 708 produces a logic low-voltage exporting node 726 to as output signal, and reverser 703 with the logic low-voltage on the node 726 oppositely to produce a logic high voltage to output node Q.
Latch cicuit 704 has the combination similar circuit configuration with latch cicuit 504 shown in Fig. 5 G and input circuit 582.The difference of the combination of latch cicuit 704 and latch cicuit 504 and input circuit 582 is: latch cicuit 704 has NAND gate 714.714 couples of signalization SB of NAND gate and carry out a NOT-AND operation from the data-signal of node 715 are to produce a data-signal of having handled to node 716.Therefore, when signalization SB was positioned at logic low, latch cicuit 704 produced a logic high voltage to export node 716 to as the data-signal of having handled.Another difference of the combination of latch cicuit 704 and latch cicuit 504 and input circuit 582 is: the nmos pass transistor 717 of latch cicuit 704 is coupled between the drain electrode of node 716 and nmos pass transistor 718.The grid of nmos pass transistor 717 is coupled to signalization SB.When signalization SB was positioned at logic low, nmos pass transistor 717 was closed the data path to disconnect from node 719 to node 716.
Latch cicuit 708 has the combination similar circuit configuration with latch cicuit 508 shown in Fig. 5 G and input circuit 584.The difference of the combination of latch cicuit 708 and latch cicuit 508 and input circuit 584 is: latch cicuit 708 has NOR gate 724.724 pairs of reverse signalizations of NOR gate and carry out NOR operation from the data-signal of having handled of node 725 output signal to node 726 to produce one.Therefore, when signalization SB was positioned at logic high, NOR gate 724 was come the reverse data-signal of having handled from node 725 as a reverser, outputs signal to node 726 with generation.
SB is positioned at logic high when signalization, and when a new input signal D input was arranged, oppositely low amplitude of oscillation clock signal C KB can be positioned at logic high, and low amplitude of oscillation clock signal C K can be positioned at logic low.Then, transfer gate circuit (nmos pass transistor) 702 is passed to data-signal the node 715 of latch cicuit 704 from receiving node 709, nmos pass transistor 713 cuts off the feedback path of latch cicuit 704, transfer gate circuit (nmos pass transistor) 706 is closed, and nmos pass transistor 723 keeps or set up the feedback path of latch cicuit 608.Then, latch cicuit 704 receives data-signals from node 715, and with this data-signal oppositely to produce a reverse data-signal to node 716.Because transfer gate circuit 706 is closed, latch cicuit 708 will latch reverse data-signal on last stage, rather than receive the reverse data-signal corresponding to new input signal D.Therefore, the value of the reverse output signal of output node Q will equal the value of an input signal rather than the value of new input signal D.Next, oppositely low amplitude of oscillation clock signal C KB can be changed to being positioned at logic low and low amplitude of oscillation clock signal C K can be positioned at logic high.Then, transfer gate circuit 702 is closed, nmos pass transistor 713 keeps or sets up the feedback path of latch cicuit 704, transfer gate circuit 706 will be passed to the node 725 of latch cicuit 708 from the reverse data-signal of node 716, and nmos pass transistor 723 cuts off the feedback path of latch cicuit 708.Latch cicuit 708 then reverse reverse data-signals output signal to node 726 to produce one.Reverser 703 then with the output signal of node 726 oppositely producing a reverse output node Q that outputs signal to, and the value of this reverse output signal of output node Q equals the value of new input signal D.SB is positioned at logic low when signalization, and latch cicuit 708 produces a logic low-voltage to export node 726 to as output signal, and then, the value of the signal on the output node Q is set to logic high.
In certain embodiments, the nmos pass transistor 712 of latch cicuit 704 shown in Figure 7 and 713 can be replaced by the nmos pass transistor 412 ' and 413 ' of latch cicuit 404 ' shown in Figure 4.And the nmos pass transistor 722 of latch cicuit 708 shown in Figure 7 and 723 can be replaced by the nmos pass transistor 422 ' and 423 ' of latch cicuit 408 ' shown in Figure 4.
Please refer to Fig. 8, Fig. 8 is the circuit diagram of the trigger 800 of the reception reset signal of another embodiment of the present invention and signalization.Low amplitude of oscillation clock signal C K vibrates and can be reversed device 831 and oppositely oppositely hangs down amplitude of oscillation clock signal C KB to produce one, and reverser 833 then will oppositely hang down amplitude of oscillation clock signal C KB oppositely with clocking CK1.In one embodiment, trigger 800 comprises reverser 801,803,805 and 807, two transfer gate circuit 802 and 806, and two latch cicuits 804 and 808.In certain embodiments, reverser 801,803,805 and 807 can be omitted.When reset signal RB was positioned at logic low, reset signal RB was used to the output voltage of output node Q is reset to logic low-voltage.When signalization SB was positioned at logic low, the output voltage that signalization SB is used to output node Q was set to logic high voltage.According to present embodiment, transfer gate circuit 802 is a nmos pass transistor, it is coupled between receiving node 809 and the node 815, have one and be coupled to the grid that oppositely hangs down amplitude of oscillation clock signal C KB, the data-signal that transfer gate circuit 802 receives from receiving node 809, and when oppositely low amplitude of oscillation clock signal C KB is positioned at logic high, will be passed to node 815 from the data-signal of receiving node 809.When oppositely low amplitude of oscillation clock signal C KB was positioned at logic high, transfer gate circuit 802 (nmos pass transistor) was unlocked will be passed to node 815 from the data-signal of receiving node 809.The latch cicuit 804 of trigger 800 has and trigger shown in Figure 7 700 latch cicuits, 704 similar circuit configuration and circuit function.Latch cicuit 804 is coupled between node 815 and the node 816, reception is from the data-signal of node 815, when signalization SB is positioned at logic high, with this data-signal oppositely to produce the data-signal handled to node 816, and when signalization SB is positioned at logic low, produces a logic high voltage and export node 816 to as the data-signal of having handled.According to present embodiment, transfer gate circuit 806 is a nmos pass transistor, it is coupled between receiving node 816 and the node 825, have one and be coupled to the grid that hangs down amplitude of oscillation clock signal C K, when low amplitude of oscillation clock signal C K is positioned at logic high, will be passed to node 825 from the data-signal of having handled of receiving node 816.When low amplitude of oscillation clock signal C K was positioned at logic high, transfer gate circuit 806 (nmos pass transistor) was unlocked being passed to node 825 from the data-signal of having handled of node 816.The latch cicuit 808 of trigger 800 has latch cicuit 608 similar circuit configuration and the circuit function with trigger shown in Figure 6 600.Latch cicuit 808 is coupled between node 825 and the node 826, receive the data-signal of having handled from node 825, when reset signal RB is positioned at logic high, the data-signal of having handled is oppositely outputed signal to node 826 to produce one, and when reset signal RB is positioned at logic low, produce a logic high voltage to export node 826 to as output signal.When reset signal RB was positioned at logic low, latch cicuit 808 produced a logic high voltage exporting node 826 to as output signal, and reverser 803 with the logic high voltage on the node 826 oppositely to produce a logic low-voltage to output node Q.When signalization SB is positioned at logic low, latch cicuit 804 produces a logic high voltage to export node 816 to as the data-signal of having handled, and latch cicuit 808 then oppositely these data-signals of having handled export node 826 to produce a logic low-voltage to as output signal, reverser 803 with the logic low-voltage on the node 826 oppositely to produce a logic high voltage to output node Q.
Latch cicuit 804 has and latch cicuit shown in Figure 7 704 similar circuit configuration.Latch cicuit 804 comprises NAND gate 814, and NAND gate 814 is coupled between node 815 and the node 816.816 couples of signalization SB of NAND gate and carry out a NOT-AND operation from the data-signal of node 815 are to produce a data-signal of having handled to node 816.Therefore, when signalization SB was positioned at logic low, latch cicuit 804 produced a logic high voltage to export node 816 to as the data-signal of having handled.Latch cicuit 808 has and latch cicuit shown in Figure 6 608 similar circuit configuration.Latch cicuit 808 comprises NAND gate 824.824 couples of reset signal RB of NAND gate and carry out NOT-AND operation from the data-signal of having handled of node 825 output signal to node 826 to produce one.Therefore, when reset signal RB was positioned at logic low, latch cicuit 808 produced a logic high voltage and exports node 826 to as output signal.
When signalization SB and reset signal RB all are positioned at logic high, and when a new input signal D input was arranged, oppositely low amplitude of oscillation clock signal C KB can be positioned at logic high, and low amplitude of oscillation clock signal C K can be positioned at logic low.Then, transfer gate circuit (nmos pass transistor) 802 is passed to data-signal the node 815 of latch cicuit 804 from receiving node 809, nmos pass transistor 813 cuts off the feedback path of latch cicuit 804, transfer gate circuit (nmos pass transistor) 806 is closed, and nmos pass transistor 829 keeps or set up the feedback path of latch cicuit 808.Then, latch cicuit 804 receives data-signals from node 815, and with this data-signal oppositely to produce a reverse data-signal to node 815.Because transfer gate circuit 806 is closed, latch cicuit 808 will latch reverse data-signal on last stage, rather than receive the reverse data-signal corresponding to new input signal D.Therefore, the value of the reverse output signal of output node Q will equal the value of an input signal rather than the value of new input signal D.Next, oppositely low amplitude of oscillation clock signal C KB can be changed to being positioned at logic low and low amplitude of oscillation clock signal C K can be positioned at logic high.Then, transfer gate circuit 802 is closed, nmos pass transistor 813 keeps or sets up the feedback path of latch cicuit 804, transfer gate circuit 806 will be passed to the node 825 of latch cicuit 808 from the reverse data-signal of node 816, and nmos pass transistor 829 cuts off the feedback path of latch cicuit 808.Latch cicuit 808 then reverse reverse data-signals output signal to node 826 to produce one.Reverser 803 then with the output signal of node 826 oppositely producing a reverse output node Q that outputs signal to, and the value of this reverse output signal of output node Q equals the value of new input signal D.RB is positioned at logic low when reset signal, and latch cicuit 808 produces a logic high voltage to node 826, and then, the value of the signal on the output node Q is reset to logic low.SB is positioned at logic low when signalization, reset signal RB is positioned at logic high, and when low amplitude of oscillation clock signal C K is positioned at logic high, latch cicuit 804 produces a logic high voltage and exports node 816 to as signal, transfer gate circuit 806 will be passed to the node 825 of latch cicuit 808 from the signal of node 816, then, latch cicuit 808 reverse these signals with produce a logic low-voltage to node 826 with as output signal, and be logic high with value value of establishing of the signal on the output node Q.
In certain embodiments, the nmos pass transistor 818 of latch cicuit 804 shown in Figure 8 and 813 can be substituted by the nmos pass transistor 412 ' of latch cicuit 404 ' shown in Figure 4 and 413 '.And the nmos pass transistor 828 of latch cicuit 808 shown in Figure 8 and 829 can be substituted by the nmos pass transistor 422 ' of latch cicuit 408 ' shown in Figure 4 and 423 '.
Though the present invention discloses as above with preferred embodiment; right its is not that any the technical staff in the technical field is not in departing from the scope of the present invention in order to qualification the present invention; can do some and change, so protection scope of the present invention should be as the criterion with the scope that claim is defined.

Claims (24)

1. a trigger receives low amplitude of oscillation clock signal, and wherein, described low amplitude of oscillation clock signal is reversed to obtain oppositely low amplitude of oscillation clock signal, and described trigger comprises:
First nmos pass transistor, be coupled between receiving node and the first node, have the grid that is coupled to described oppositely low amplitude of oscillation clock signal, and when described oppositely low amplitude of oscillation clock signal is positioned at logic high, will be passed to described first node from the data-signal of described receiving node;
First latch cicuit is coupled between described first node and the Section Point, with described data-signal oppositely to produce reverse data-signal to described Section Point;
Second nmos pass transistor, be coupled between described Section Point and the 3rd node, has the grid that is coupled to described low amplitude of oscillation clock signal, and when described low amplitude of oscillation clock signal is positioned at described logic high, will be passed to described the 3rd node from the described reverse data-signal of described Section Point; And
Second latch cicuit is coupled between described the 3rd node and the 4th node, and described reverse data-signal is oppositely outputed signal to described the 4th node with generation.
2. trigger according to claim 1 is characterized in that: described first latch cicuit comprises:
First reverser is coupled between described first node and the described Section Point, with described data-signal oppositely to produce described reverse data-signal to described Section Point;
The one PMOS transistor is coupled between voltage source and the described first node, has the grid that is coupled to described Section Point;
The 3rd nmos pass transistor has the drain electrode that is coupled to described first node, and has the grid that is coupled to described Section Point; And
The 4th nmos pass transistor is coupled between the source electrode and ground voltage of described the 3rd nmos pass transistor, has the grid that is coupled to described low amplitude of oscillation clock signal.
3. trigger according to claim 1 is characterized in that: described second latch cicuit comprises:
Second reverser is coupled between described the 3rd node and described the 4th node, with described reverse data-signal oppositely to produce described described the 4th node that outputs signal to;
The 2nd PMOS transistor is coupled between voltage source and described the 3rd node, has the grid that is coupled to described the 4th node;
The 5th nmos pass transistor has the drain electrode that is coupled to described the 3rd node, and has the grid that is coupled to described the 4th node; And
The 6th nmos pass transistor is coupled between the source electrode and ground voltage of described the 5th nmos pass transistor, has the grid that is coupled to described oppositely low amplitude of oscillation clock signal.
4. trigger according to claim 1 is characterized in that: described first latch cicuit comprises:
First reverser is coupled between described first node and the described Section Point, with described data-signal oppositely to produce described reverse data-signal to described Section Point;
The one PMOS transistor is coupled between voltage source and the described first node, has the grid that is coupled to described Section Point;
The 3rd nmos pass transistor has the drain electrode that is coupled to described first node, and has the grid that is coupled to described low amplitude of oscillation clock signal; And
The 4th nmos pass transistor is coupled between the source electrode and ground voltage of described the 3rd nmos pass transistor, has the grid that is coupled to described Section Point.
5. trigger according to claim 1 is characterized in that: described second latch cicuit comprises:
Second reverser is coupled between described the 3rd node and described the 4th node, with described reverse data-signal oppositely to produce described described the 4th node that outputs signal to;
The 2nd PMOS transistor is coupled between voltage source and described the 3rd node, has the grid that is coupled to described the 4th node;
The 5th nmos pass transistor has the drain electrode that is coupled to described the 3rd node, and has the grid that is coupled to described oppositely low amplitude of oscillation clock signal; And
The 6th nmos pass transistor is coupled between the source electrode and ground voltage of described the 5th nmos pass transistor, has the grid that is coupled to described the 4th node.
6. trigger according to claim 1 is characterized in that: described trigger further comprises:
The 3rd reverser is coupled between input node and the described receiving node, from described input node receiving inputted signal, and with described input signal oppositely to produce described data-signal to described receiving node;
The 4th reverser is coupled between described the 4th node and the output node, with described output signal oppositely to produce the reverse described output node that outputs signal to; And
The 5th reverser and the 6th reverser, coupled in series will be passed to described reverse output node from the described output signal of described the 4th node between described the 4th node and reverse output node.
7. trigger according to claim 1 is characterized in that: described trigger further comprises first input circuit, is coupled between described Section Point and described the 4th node, and described first input circuit comprises:
The 7th nmos pass transistor has the drain electrode that is coupled to described the 4th node, and has the grid that is coupled to described Section Point; And
The 8th nmos pass transistor is coupled between the source electrode and ground voltage of described the 7th nmos pass transistor, has the grid that is coupled to described low amplitude of oscillation clock signal.
8. trigger according to claim 1 is characterized in that: described trigger further comprises first input circuit, is coupled between described first node and described the 4th node, comprises:
The 3rd PMOS transistor has the source electrode that is coupled to described the 4th node, and has the grid that is coupled to described first node; And
The 8th nmos pass transistor is coupled between described the 3rd PMOS transistor drain and the ground voltage, has the grid that is coupled to described low amplitude of oscillation clock signal.
9. trigger according to claim 1 is characterized in that: described trigger further comprises second input circuit, is coupled between described receiving node and the described Section Point, comprises:
The 9th nmos pass transistor has the drain electrode that is coupled to described Section Point, and has the grid that is coupled to described receiving node; And
The tenth nmos pass transistor is coupled between the source electrode and ground voltage of described the 9th nmos pass transistor, has the grid that is coupled to described oppositely low amplitude of oscillation clock signal.
10. trigger according to claim 1, it is characterized in that: described trigger further comprises the 3rd reverser and second input circuit, wherein said the 3rd reverser is coupled between input node and the described receiving node, from described input node receiving inputted signal, and with described input signal oppositely to produce described data-signal to described receiving node, and described second input circuit is coupled between described input node and the described Section Point, comprises:
The 4th PMOS transistor has the source electrode that is coupled to described Section Point, and has the grid that is coupled to described input node; And
The tenth nmos pass transistor is coupled between described the 4th PMOS transistor drain and the ground voltage, has the grid that is coupled to described oppositely low amplitude of oscillation clock signal.
11. trigger according to claim 1, it is characterized in that: described trigger further comprises the 3rd reverser, described the 3rd reverser is coupled between input node and the described receiving node, from described input node receiving inputted signal, and with described input signal oppositely to produce described data-signal to described receiving node, wherein, described trigger further comprises:
The 11 nmos pass transistor is coupled between described input node and the described Section Point, has the grid that is coupled to described oppositely low amplitude of oscillation clock signal; And
The tenth bi-NMOS transistor is coupled between described first node and described the 4th node, has the grid that is coupled to described low amplitude of oscillation clock signal.
12. trigger according to claim 1, it is characterized in that: described trigger further comprises the 3rd reverser, described the 3rd reverser is coupled between input node and the described receiving node, from described input node receiving inputted signal, and with described input signal oppositely to produce described data-signal to described receiving node, wherein said trigger further comprises:
The 5th PMOS transistor is coupled between described input node and the described Section Point, has the grid that is coupled to described low amplitude of oscillation clock signal; And
The 6th PMOS transistor is coupled between described first node and described the 4th node, has the grid that is coupled to described oppositely low amplitude of oscillation clock signal.
13. a trigger receives low amplitude of oscillation clock signal, wherein, described low amplitude of oscillation clock signal is reversed to obtain oppositely low amplitude of oscillation clock signal, and described trigger comprises:
First nmos pass transistor, be coupled between receiving node and the first node, has the grid that is coupled to described oppositely low amplitude of oscillation clock signal, receive data-signal from described receiving node, and when described oppositely low amplitude of oscillation clock signal is positioned at logic high, will be passed to described first node from the described data-signal of described receiving node;
First latch cicuit is coupled between described first node and the Section Point, when reset signal is positioned at described logic high, with described data-signal oppositely to produce the data-signal handled to described Section Point;
Second nmos pass transistor, be coupled between described Section Point and the 3rd node, has the grid that is coupled to described low amplitude of oscillation clock signal, when described low amplitude of oscillation clock signal is positioned at described logic high, will be passed to described the 3rd node from the described data-signal of having handled of described Section Point; And
Second latch cicuit, be coupled between described the 3rd node and the 4th node, when described reset signal is positioned at described logic high, the described data-signal of having handled is oppositely outputed signal to described the 4th node with generation, and when described reset signal is positioned at logic low, produce logic high voltage to export described the 4th node to as described output signal.
14. trigger according to claim 13, it is characterized in that: described reset signal is reversed to obtain reverse reset signal, and described trigger further comprises first reverser, described first reverser is coupled between input node and the described receiving node, from described input node receiving inputted signal, and oppositely producing described data-signal to described receiving node, and described first latch cicuit comprises with described input signal:
OR-NOT circuit is coupled between described first node and the described Section Point, and described reverse reset signal and described data-signal are carried out NOR operation, to produce the described data-signal of having handled to described Section Point;
The one PMOS transistor is coupled between voltage source and the described first node, has the grid that is coupled to described Section Point;
The 3rd nmos pass transistor has the drain electrode that is coupled to described first node, and has the grid that is coupled to described Section Point;
The 4th nmos pass transistor is coupled between the source electrode and ground voltage of described the 3rd nmos pass transistor, has the grid that is coupled to described low amplitude of oscillation clock signal;
The 5th nmos pass transistor has the drain electrode that is coupled to described Section Point, and has the grid that is coupled to described reset signal; And
The 6th nmos pass transistor is coupled between the source electrode and described input node of described the 5th nmos pass transistor, has the grid that is coupled to described oppositely low amplitude of oscillation clock signal.
15. trigger according to claim 13 is characterized in that: described second latch cicuit comprises:
NAND gate circuit is coupled between described the 3rd node and described the 4th node, described reset signal and the described data-signal of having handled is carried out NOT-AND operation, to produce described described the 4th node that outputs signal to;
The 2nd PMOS transistor is coupled between voltage source and described the 3rd node, has the grid that is coupled to described the 4th node;
The 7th nmos pass transistor has the drain electrode that is coupled to described the 3rd node, and has the grid that is coupled to described the 4th node;
The 8th nmos pass transistor is coupled between the source electrode and ground voltage of described the 7th nmos pass transistor, has the grid that is coupled to described oppositely low amplitude of oscillation clock signal; And
The 9th nmos pass transistor is coupled between described the 4th node and the described first node, has the grid that is coupled to described low amplitude of oscillation clock signal.
16. trigger according to claim 13 is characterized in that: described trigger further comprises:
First reverser is coupled between input node and the described receiving node, from described input node receiving inputted signal, and with described input signal oppositely to produce described data-signal to described receiving node;
Second reverser is coupled between described the 4th node and the output node, will be from the described output signal of described the 4th node oppositely to produce the reverse described output node that outputs signal to; And
The 3rd reverser and the 4th reverser, coupled in series will be passed to described reverse output node from the described output signal of described the 4th node between described the 4th node and reverse output node.
17. a trigger receives low amplitude of oscillation clock signal, wherein, described low amplitude of oscillation clock signal is reversed to obtain oppositely low amplitude of oscillation clock signal, comprises:
First nmos pass transistor, be coupled between receiving node and the first node, have the grid that is coupled to described oppositely low amplitude of oscillation clock signal, and when described oppositely low amplitude of oscillation clock signal is positioned at logic high, will be passed to described first node from the data-signal of described receiving node;
First latch cicuit is coupled between described first node and the Section Point, when signalization is positioned at described logic high, with described data-signal oppositely to produce the data-signal handled to described Section Point;
Second nmos pass transistor, be coupled between described Section Point and the 3rd node, has the grid that is coupled to described low amplitude of oscillation clock signal, and when described low amplitude of oscillation clock signal is positioned at described logic high, will be passed to described the 3rd node from the described data-signal of having handled of described Section Point; And
Second latch cicuit is coupled between described the 3rd node and the 4th node, when described signalization is positioned at described logic low, produces logic low-voltage and exports described the 4th node to as output signal.
18. trigger according to claim 17, it is characterized in that: described trigger further comprises first reverser, described first reverser is coupled between input node and the described receiving node, from described input node receiving inputted signal, and oppositely producing described data-signal to described receiving node, and described first latch cicuit comprises with described input signal:
NAND gate circuit is coupled between described first node and the described Section Point, and described signalization and described data-signal are carried out NOT-AND operation, to produce the described data-signal of having handled to described Section Point;
The one PMOS transistor is coupled between voltage source and the described first node, has the grid that is coupled to described Section Point;
The 3rd nmos pass transistor has the drain electrode that is coupled to described first node, and has the grid that is coupled to described Section Point;
The 4th nmos pass transistor is coupled between the source electrode and ground voltage of described the 3rd nmos pass transistor, has the grid that is coupled to described low amplitude of oscillation clock signal;
The 5th nmos pass transistor has the drain electrode that is coupled to described Section Point, and has the grid that is coupled to described signalization; And
The 6th nmos pass transistor is coupled between the source electrode and described input node of described the 5th nmos pass transistor, has the grid that is coupled to described oppositely low amplitude of oscillation clock signal.
19. trigger according to claim 17 is characterized in that: described signalization is reversed to obtain reverse signalization, and described second latch cicuit comprises:
OR-NOT circuit is coupled between described the 3rd node and described the 4th node, described reverse signalization and the described data-signal of having handled is carried out NOR operation, to produce described described the 4th node that outputs signal to;
The 2nd PMOS transistor is coupled between voltage source and described the 3rd node, has the grid that is coupled to described the 4th node;
The 7th nmos pass transistor has the drain electrode that is coupled to described the 3rd node, and has the grid that is coupled to described the 4th node;
The 8th nmos pass transistor is coupled between the source electrode and ground voltage of described the 7th nmos pass transistor, has the grid that is coupled to described oppositely low amplitude of oscillation clock signal; And
The 9th nmos pass transistor is coupled between described the 4th node and the described first node, has the grid that is coupled to described low amplitude of oscillation clock signal.
20. trigger according to claim 17 is characterized in that: described trigger further comprises:
First reverser is coupled between input node and the described receiving node, from described input node receiving inputted signal, and with described input signal oppositely to produce described data-signal to described receiving node;
Second reverser is coupled between described the 4th node and the output node, will be from the described output signal of described the 4th node oppositely to produce the reverse described output node that outputs signal to; And
The 3rd reverser and the 4th reverser, coupled in series will be passed to described reverse output node from the described output signal of described the 4th node between described the 4th node and reverse output node.
21. a trigger receives low amplitude of oscillation clock signal, wherein, described low amplitude of oscillation clock signal is reversed to obtain oppositely low amplitude of oscillation clock signal, and described trigger comprises:
First nmos pass transistor, be coupled between receiving node and the first node, have the grid that is coupled to described oppositely low amplitude of oscillation clock signal, and when described oppositely low amplitude of oscillation clock signal is positioned at logic high, will be passed to described first node from the data-signal of described receiving node;
First latch cicuit, be coupled between described first node and the Section Point, when signalization is positioned at described logic high, with described data-signal oppositely to produce the data-signal handled to described Section Point, and when described signalization is positioned at logic low, produce logic high voltage to export described Section Point to as the described data-signal of having handled;
Second nmos pass transistor, be coupled between described Section Point and the 3rd node, has the grid that is coupled to described low amplitude of oscillation clock signal, and when described low amplitude of oscillation clock signal is positioned at described logic high, will be passed to described the 3rd node from the described data-signal of having handled of described Section Point; And
Second latch cicuit, be coupled between described the 3rd node and the 4th node, when reset signal is positioned at described logic high, the described data-signal of having handled is oppositely outputed signal to described the 4th node with generation, and when described reset signal is positioned at described logic low, produce logic high voltage with described output signal as described the 4th node.
22. trigger according to claim 21, it is characterized in that: described trigger further comprises first reverser, described first reverser is coupled between input node and the described receiving node, from described input node receiving inputted signal, and oppositely producing described data-signal to described receiving node, and described first latch cicuit comprises with described input signal:
NAND gate circuit is coupled between described first node and the described Section Point, and described signalization and described data-signal are carried out NOT-AND operation, to produce the described data-signal of having handled to described Section Point;
The one PMOS transistor is coupled between voltage source and the described first node, has the grid that is coupled to described reset signal;
The 2nd PMOS transistor is coupled between described voltage source and the described first node, has the grid that is coupled to described Section Point;
The 3rd nmos pass transistor has the drain electrode that is coupled to described first node, and has the grid that is coupled to described reset signal;
The 4th nmos pass transistor has the drain electrode of the source electrode that is coupled to described the 3rd nmos pass transistor, and has the grid that is coupled to described Section Point;
The 5th nmos pass transistor is coupled between the source electrode and ground voltage of described the 4th nmos pass transistor, has the grid that is coupled to described low amplitude of oscillation clock signal;
The 6th nmos pass transistor has the drain electrode that is coupled to described Section Point, and has the grid that is coupled to described reset signal;
The 7th nmos pass transistor has the drain electrode of the source electrode that is coupled to described the 6th nmos pass transistor, and has the grid that is coupled to described signalization; And
The 8th nmos pass transistor is coupled between the source electrode and described input node of described the 7th nmos pass transistor, has the grid that is coupled to described oppositely low amplitude of oscillation clock signal.
23. trigger according to claim 21 is characterized in that: described second latch cicuit comprises:
NAND gate circuit is coupled between described the 3rd node and described the 4th node, described reset signal and the described data-signal of having handled is carried out NOT-AND operation, to produce described described the 4th node that outputs signal to;
The 3rd PMOS transistor is coupled between voltage source and described the 3rd node, has the grid that is coupled to described signalization;
The 4th PMOS transistor is coupled between described voltage source and described the 3rd node, has the grid that is coupled to described the 4th node;
The 9th nmos pass transistor has the drain electrode that is coupled to described the 3rd node, and has the grid that is coupled to described signalization;
The tenth nmos pass transistor has the drain electrode of the source electrode that is coupled to described the 9th nmos pass transistor, and has the grid that is coupled to described the 4th node;
The 11 nmos pass transistor is coupled between the source electrode and ground voltage of described the tenth nmos pass transistor, has the grid that is coupled to described oppositely low amplitude of oscillation clock signal; And
The tenth bi-NMOS transistor is coupled between described the 4th node and the described first node, has the grid that is coupled to described low amplitude of oscillation clock signal.
24. trigger according to claim 21 is characterized in that: described trigger further comprises:
First reverser is coupled between input node and the described receiving node, from described input node receiving inputted signal, and with described input signal oppositely to produce described data-signal to described receiving node;
Second reverser is coupled between described the 4th node and the output node, will be from the described output signal of described the 4th node oppositely to produce the reverse described output node that outputs signal to; And
The 3rd reverser and the 4th reverser, coupled in series will be passed to described reverse output node from the described output signal of described the 4th node between described the 4th node and reverse output node.
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