CN102215034B

CN102215034B - Flip-flop

Info

Publication number: CN102215034B
Application number: CN201110089379.4A
Authority: CN
Inventors: 简丞星; 游永杰; 许佳宜
Original assignee: MediaTek Inc
Current assignee: MediaTek Inc
Priority date: 2010-04-12
Filing date: 2011-04-11
Publication date: 2014-08-20
Anticipated expiration: 2031-04-11
Also published as: CN102215034A

Abstract

The invention provides a flip-flop. In one embodiment, the flip-flop receives a low swing clock signal, and comprises a first NMOS transistor, a first latch circuit, a second NMOS transistor, and a second latch circuit. The low swing clock signal is inverted to obtain an inverted low swing clock signal. The first NMOS transistor is coupled between a receiving node and a first node, and has a gate coupled to the inverted low swing clock signal. The first latch circuit is coupled between the first node and a second node. The second NMOS transistor is coupled between the second node and a third node. The second latch circuit is coupled between the third node and a fourth node, and generates an output signal on the fourth node.

Description

Trigger

Technical field

The present invention has about trigger (flip-flop), particularly about the trigger that receives the low amplitude of oscillation (swing) clock signal.

Background technology

Trigger is the circuit with two stable states, and it can be used to storing state message.Two stable state values of being expressed as " 0 " and " 1 " of trigger.Trigger is conventionally by clock signal control.According to the value of input signal, clock can cause trigger to change or keep its output signal in the time changing (transition).Some trigger changes output in the rising edge of clock signal, and other trigger changes output in the drop edge of clock signal.

Please refer to Fig. 1, Fig. 1 is the circuit diagram of conventional trigger device 200.Conventional trigger device 200 can comprise reverser 231,232,233, and 234, transfer gate circuit (passing gate circuit) 202 and 206, and latch cicuit 204 and 208.High amplitude of oscillation clock signal C K ' feeds back to reverser 251.Reverser 251 by high amplitude of oscillation clock signal C K ' oppositely to produce reverse clock signal C KB ' (being designated hereinafter simply as: oppositely clock signal C KB '), and reverser 253 then by reverse clock signal C KB ' oppositely with clocking CK1 '.

Latch cicuit 204 comprises two reversers 213,214 and comprises P-type mos (P-Metallic Oxide Semiconductor, be designated hereinafter simply as PMOS) transmission gate circuit (transmission gate) of transistor 215 and N-type metal-oxide semiconductor (MOS) (N-Metallic Oxide Semiconductor, is designated hereinafter simply as NMOS) transistor 216.Latch cicuit 208 comprises two reversers 223,224 and comprises PMOS transistor 225 and the gate circuit of nmos pass transistor 226.Reverser 231 by data-signal oppositely to produce reverse data-signal.In the time that clock signal CK1 ' is positioned at logic low and oppositely clock signal C KB ' is positioned at logic high, transfer gate circuit 202 transmits the node 217 of reverse data-signal to latch cicuit 204, comprise that the transmission gate circuit of transistor 215 and 216 cuts off the feedback path of latch cicuit 204, transfer gate circuit 206 is closed, and comprises that the transmission gate circuit of transistor 225 and 226 keeps or set up the feedback path of latch cicuit 208.Then, latch cicuit 204 receives reverse data-signal from node 217, and oppositely this reverse data-signal to produce data-signal in node 218.When reverse clock signal C KB ' is positioned at logic low and clock signal C K1 ' is positioned at logic high, transfer gate circuit 202 is closed, comprise that the transmission gate circuit of transistor 215 and 216 keeps or set up the feedback path of latch cicuit 204, transfer gate circuit 206 is passed to the data-signal of node 218 node 227 of latch cicuit 208, and comprises that the transmission gate circuit of transistor 225 and 226 cuts off the feedback path of latch cicuit 208.Latch cicuit 208 receives data-signal from node 227, and oppositely this data-signal to produce reverse data-signal in node 228.Then, reverse this reverse data-signal of reverser 232 is to produce a data-signal in output node Q, and this reverse data-signal is passed to reverse output node (inverted output node) QB by reverser 233 and 234.

The vibration of clock signal can cause power consumption.If the clock signal of circuit is with low amplitude of oscillation voltage oscillation, the power consumption meeting of circuit reduces a lot.Because total electric weight of portable equipment is limited, therefore, the power consumption that reduces portable equipment is very important.Therefore, should be designed to have low amplitude of oscillation level for the clock signal of the circuit with limited electric weight, to reduce power consumption.But traditional trigger 200 can not directly receive low amplitude of oscillation clock signal.Transfer gate circuit 202 and 206 comprises respectively PMOS transistor 211 and 221, PMOS transistor 211 has the grid that is coupled to clock signal C K1 ', and PMOS transistor 221 has the grid that is coupled to reverse clock signal C KB '; And latch cicuit 204 and 208 also comprises respectively PMOS transistor 215 and 225, PMOS transistor 215 has the grid that is coupled to reverse clock signal C KB ', PMOS transistor 225 has the grid that is coupled to clock signal C K1 '.If clock signal C K1 ' and oppositely clock signal C KB ' are low amplitude of oscillation clock signal, PMOS transistor 211,215,221, and 225 can not be closed completely by the low-voltage of clock signal.Therefore, traditional trigger 200 can not normally move under low amplitude of oscillation clock signal.Therefore,, before low amplitude of oscillation clock signal is fed back to conventional trigger device, the voltage level of low amplitude of oscillation clock signal must amplify via being low to moderate high level transducer (low-to-high level shifter).Level translator can increase the manufacturing cost of circuit.If can receive low amplitude of oscillation clock signal for the new trigger of circuit, can not use and be low to moderate high level transducer to reduce the manufacturing cost of circuit.Therefore, need a kind of new trigger that can receive low amplitude of oscillation clock signal.

Summary of the invention

In order to reduce the power consumption of portable equipment and the manufacturing cost of reduction circuit, the invention provides a kind of trigger, it can receive low amplitude of oscillation clock signal.

The invention provides a kind of trigger, receive low amplitude of oscillation clock signal, wherein, described low amplitude of oscillation clock signal is reversed to obtain reverse low amplitude of oscillation clock signal, described trigger comprises: the first nmos pass transistor, be coupled between receiving node and first node, and there is the grid that is coupled to described reverse low amplitude of oscillation clock signal, and in the time that described reverse low amplitude of oscillation clock signal is positioned at logic high, will be passed to described first node from the data-signal of described receiving node; The first latch cicuit, is coupled between described first node and Section Point, by described data-signal oppositely to produce reverse data-signal to described Section Point; The second nmos pass transistor, be coupled between described Section Point and the 3rd node, there is the grid that is coupled to described low amplitude of oscillation clock signal, and in the time that described low amplitude of oscillation clock signal is positioned at described logic high, will be passed to described the 3rd node from the described reverse data-signal of described Section Point; And second latch cicuit, be coupled between described the 3rd node and the 4th node, described reverse data-signal is oppositely outputed signal to described the 4th node to produce.

The present invention separately provides a kind of trigger, receive low amplitude of oscillation clock signal, wherein, described low amplitude of oscillation clock signal is reversed to obtain reverse low amplitude of oscillation clock signal, described trigger comprises: the first nmos pass transistor, be coupled between receiving node and first node, there is the grid that is coupled to described reverse low amplitude of oscillation clock signal, receive data-signal from described receiving node, and in the time that described reverse low amplitude of oscillation clock signal is positioned at logic high, the described data-signal from described receiving node is passed to described first node; The first latch cicuit, is coupled between described first node and Section Point, in the time that reset signal is positioned at described logic high, by described data-signal oppositely to produce processed data-signal to described Section Point; The second nmos pass transistor, be coupled between described Section Point and the 3rd node, there is the grid that is coupled to described low amplitude of oscillation clock signal, in the time that described low amplitude of oscillation clock signal is positioned at described logic high, described the 3rd node will be passed to from the described processed data-signal of described Section Point; And second latch cicuit, be coupled between described the 3rd node and the 4th node, in the time that described reset signal is positioned at described logic high, described processed data-signal is oppositely outputed signal to described the 4th node to produce, and in the time that described reset signal is positioned at logic low, produce logic high voltage to export described the 4th node to as described output signal.

The present invention separately provides a kind of trigger, receive low amplitude of oscillation clock signal, wherein, described low amplitude of oscillation clock signal is reversed to obtain reverse low amplitude of oscillation clock signal, comprise: the first nmos pass transistor, be coupled between receiving node and first node, there is the grid that is coupled to described reverse low amplitude of oscillation clock signal, and in the time that described reverse low amplitude of oscillation clock signal is positioned at logic high, will be passed to described first node from the data-signal of described receiving node; The first latch cicuit, is coupled between described first node and Section Point, in the time that signalization is positioned at described logic high, by described data-signal oppositely to produce processed data-signal to described Section Point; The second nmos pass transistor, be coupled between described Section Point and the 3rd node, there is the grid that is coupled to described low amplitude of oscillation clock signal, and in the time that described low amplitude of oscillation clock signal is positioned at described logic high, described the 3rd node will be passed to from the described processed data-signal of described Section Point; And second latch cicuit, be coupled between described the 3rd node and the 4th node, in the time that described signalization is positioned at described logic low, produces logic low-voltage and export described the 4th node to as output signal.

The present invention separately provides a kind of trigger, receive low amplitude of oscillation clock signal, wherein, described low amplitude of oscillation clock signal is reversed to obtain reverse low amplitude of oscillation clock signal, described trigger comprises: the first nmos pass transistor, be coupled between receiving node and first node, and there is the grid that is coupled to described reverse low amplitude of oscillation clock signal, and in the time that described reverse low amplitude of oscillation clock signal is positioned at logic high, will be passed to described first node from the data-signal of described receiving node; The first latch cicuit, be coupled between described first node and Section Point, in the time that signalization is positioned at described logic high, by described data-signal oppositely to produce processed data-signal to described Section Point, and in the time that described signalization is positioned at logic low, produce logic high voltage to export described Section Point to as described processed data-signal; The second nmos pass transistor, be coupled between described Section Point and the 3rd node, there is the grid that is coupled to described low amplitude of oscillation clock signal, and in the time that described low amplitude of oscillation clock signal is positioned at described logic high, described the 3rd node will be passed to from the described processed data-signal of described Section Point; And second latch cicuit, be coupled between described the 3rd node and the 4th node, in the time that reset signal is positioned at described logic high, described processed data-signal is oppositely outputed signal to described the 4th node to produce, and in the time that described reset signal is positioned at described logic low, produce logic high voltage using the described output signal as described the 4th node.

Trigger provided by the present invention, can receive low amplitude of oscillation clock signal, reduces the power consumption being caused by the vibration of clock signal.Utilize trigger provided by the present invention, can effectively reduce the power consumption of portable equipment, and can not use and be low to moderate high level transducer to reduce the manufacturing cost of circuit.

Brief description of the drawings

Fig. 1 is the circuit diagram of conventional trigger device 200.

Fig. 2 is the schematic diagram of circuit 300 of comprising of one embodiment of the invention of multiple triggers that can receive low amplitude of oscillation clock signal.

Fig. 3 is the circuit diagram of the trigger that can receive low amplitude of oscillation clock signal 400 of another embodiment of the present invention.

Fig. 4 is the circuit diagram of the trigger that can receive low amplitude of oscillation clock signal 410 of another embodiment of the present invention.

Fig. 5 A is the circuit diagram that can accelerate the trigger 500 of the input circuit 540 of signal generation speed that comprises of another embodiment of the present invention.

Fig. 5 B is the circuit diagram that can accelerate the trigger 510 of the input circuit 540 ' of signal generation speed that comprises of another embodiment of the present invention.

Fig. 5 C is two circuit diagrams that can accelerate the trigger 520 of the input circuit 540 and 550 of signal generation speed that comprise of one embodiment of the invention.

Fig. 5 D can accelerate signal for two to produce the input circuit 540 of speed and the circuit diagram of 550 ' trigger 530 comprising of another embodiment of the present invention.

Fig. 5 E is the circuit diagram of the trigger that comprises two input circuits 560 of another embodiment of the present invention.

Fig. 5 F is the circuit diagram of the trigger that comprises two input circuits 570 of another embodiment of the present invention.

Fig. 5 G is the circuit diagram of the trigger that comprises two input circuits 580 of another embodiment of the present invention.

Fig. 5 H is the circuit diagram of the trigger that comprises two input circuits 590 of another embodiment of the present invention.

Fig. 6 is the circuit diagram of the trigger 600 of the reception reset signal of another embodiment of the present invention.

Fig. 7 is the circuit diagram of the trigger 700 of the reception signalization of another embodiment of the present invention.

Fig. 8 is the circuit diagram of the reception reset signal of another embodiment of the present invention and the trigger 800 of signalization.

Embodiment

Please refer to Fig. 2, the schematic diagram of the circuit 300 that what Fig. 2 was one embodiment of the invention comprise multiple triggers that can receive low amplitude of oscillation clock signal.Circuit 300 comprises low amplitude of oscillation clock buffer 311,312,313 and 314, low amplitude of oscillation gate circuit 324 and 325, and high to low transition device 321,322 and 323.In addition, circuit 300 comprises three triggers 331,332 and 333 that can receive low amplitude of oscillation clock signal.The voltage level of the source clock signal C 0 being produced by root from high to low level translator 321 reduces to produce low amplitude of oscillation clock signal C 1.Then, low amplitude of oscillation clock signal C 1 is sent to low amplitude of oscillation clock buffer 311,312 and 313 to produce low amplitude of oscillation clock signal C 2, C3 and C4.Because trigger 331,332 and 333 can receive low amplitude of oscillation clock signal, then, low amplitude of oscillation clock signal C 2, C3 and C4 can, without any intervention that is low to moderate high level transducer, be transferred to respectively trigger 331,332 and 333.Compared with traditional circuit, circuit 300 does not need to be low to moderate high level transducer and low amplitude of oscillation clock signal is converted to high amplitude of oscillation clock signal can normally moves yet; Therefore, the manufacturing cost of circuit 300 will reduce.In certain embodiments, height to low transition device 321,322 and 323 can be replaced by buffer.

Please refer to Fig. 3, the circuit diagram of the trigger that can receive low amplitude of oscillation clock signal 400 that Fig. 3 is another embodiment of the present invention.Low amplitude of oscillation clock signal C K vibrates and can be reversed device 431 oppositely to produce a reverse low amplitude of oscillation clock signal C KB, and reverser 433 is followed reverse low amplitude of oscillation clock signal C KB oppositely with clocking CK1.Trigger 400 can comprise reverser 401,403, and 405 and 407, transfer gate circuit 402 and 406, and latch cicuit 404 and 408.In certain embodiments, reverser 401,403,405 and 407 can be omitted.Reverser 401 is coupled between input node and receiving node 409, receives input signal D from input node, and oppositely this input signal D to produce data-signal to receiving node 409.According to the present embodiment, transfer gate circuit 402 is nmos pass transistor, is coupled between receiving node 409 and node 415, and has the grid that is coupled to reverse low amplitude of oscillation clock signal C KB.When reverse low amplitude of oscillation clock signal C KB is logic high, transfer gate circuit 402 (nmos pass transistor) is passed to node 415 by data-signal by receiving node 409.Latch cicuit 404 is coupled between node 415 and node 416, receives data-signal from node 415, and oppositely this data-signal to produce reverse data-signal to node 416.According to the present embodiment, transfer gate circuit 406 is nmos pass transistor, is coupled between node 416 and node 425, and has the grid that is coupled to low amplitude of oscillation clock signal C K.When low amplitude of oscillation clock signal C K is positioned at logic high, transfer gate circuit 406 (nmos pass transistor) is delivered to node 425 by reverse data-signal by node 416.Latch cicuit 408 is coupled between node 425 and node 426, receives reverse data-signal from node 425, and oppositely this reverse data-signal outputs signal to node 426 to produce one.Reverser 403 is coupled between node 426 and output node Q, then, oppositely from the output signal of node 426 to produce reverse output node Q that outputs signal to.Reverser 405 and 407 coupled in series, between node 426 and reverse output node QB, receive output signal to produce final output signal to reverse output node QB from node 426.

In one embodiment, latch cicuit 404 comprises: PMOS transistor 411, reverser 414, and two nmos pass transistors 412 and 413.Reverser 414 is coupled between node 415 and 416, by the data-signal of node 415 oppositely to produce reverse data-signal to node 416.PMOS transistor 411 is coupled between voltage source DVDD and node 415, and the grid of PMOS transistor 411 is coupled to node 416.When the voltage of node 416 is positioned at logic low, PMOS transistor 411 is unlocked the voltage of node 415 to be promoted to the level of voltage source DVDD.The drain electrode of nmos pass transistor 412 is coupled to node 415, and grid is coupled to node 416.Nmos pass transistor 413 is coupled between the source electrode and ground voltage DVSS of nmos pass transistor 412, and the grid of nmos pass transistor 413 is coupled to low amplitude of oscillation clock signal C K.When low amplitude of oscillation clock signal C K is positioned at logic high, and the voltage of node 416 is positioned at logic high, and nmos pass transistor 412 and 413 is all opened with the level to ground voltage DVSS by the lower voltage of node 415.

In one embodiment, latch cicuit 408 comprises PMOS transistor 421, reverser 424, and two nmos pass transistors 422 and 423.Reverser 424 is coupled between node 425 and 426, oppositely outputs signal to node 426 from the reverse data-signal of node 425 to produce.PMOS transistor 421 is coupled between voltage source DVDD and node 425, and the grid of PMOS transistor 421 is coupled to node 426.When the voltage of node 426 is positioned at logic low, PMOS transistor 421 is opened, the voltage of node 425 is promoted to the level of voltage source DVDD.The drain electrode of nmos pass transistor 422 is coupled to node 425, and grid is coupled to node 426.Nmos pass transistor 423 is coupled between the source electrode and ground voltage DVSS of nmos pass transistor 422, and the grid of nmos pass transistor 423 is coupled to reverse low amplitude of oscillation clock signal C KB.When low amplitude of oscillation clock signal C KB is positioned at logic high, and the voltage of node 426 is positioned at logic high, and nmos pass transistor 422 and 423 is all opened with the level to ground voltage DVSS by the lower voltage of node 425.

When there being a new input signal D to be transfused to, reverse low amplitude of oscillation clock signal C KB can be positioned at logic high and low amplitude of oscillation clock signal C K can be positioned at logic low.Then, transfer gate circuit 402 will be passed to the node 415 of latch cicuit 404 from the data-signal of receiving node 409, nmos pass transistor 413 cuts off the feedback path of latch cicuit 404, and transfer gate circuit 406 is closed, and nmos pass transistor 423 keeps or set up the feedback path of latch cicuit 408.Then, latch cicuit 404 receives data-signal from node 415, and oppositely this data-signal to produce reverse data-signal to node 416.Because transfer gate circuit 406 is closed, therefore, latch cicuit 408 is by latch reverse data-signal on last stage, instead of reception is corresponding to the reverse data-signal of new input signal D.Therefore, the value of the reverse output signal of output node Q will equal the value of a upper input signal, instead of the value of new input signal D.

Next, reverse low amplitude of oscillation clock signal C KB can change into and be positioned at logic low, and low amplitude of oscillation clock signal C K can be positioned at logic high.Then, transfer gate circuit 402 is closed, nmos pass transistor 413 keeps or sets up the feedback path of latch cicuit 404, and transfer gate circuit 406 is passed to reverse data-signal the node 425 of latch cicuit 408 by node 416, and nmos pass transistor 423 cuts off the feedback path of latch cicuit 408.Then, reverse this reverse data-signal of latch cicuit 408 outputs signal to node 426 to produce.Then, reverser 403 is by the output signal from node 426 oppositely to produce the reverse output node Q that outputs signal to, and the value of the reverse output signal of output node Q this moment equals the value of new input signal D.

The circuit of conventional trigger device 200 as shown in Figure 1 only can run under the clock signal C K1 ' and CKB ' with normal amplitude of oscillation level.If the amplitude of oscillation level drops of clock signal C K1 ' and CKB ' is low to moderate low level, when clock signal CK1 ' and CKB ' vibration is when having low level peak value, the PMOS transistor 211 and 221 of transfer gate circuit 202 and 206 can not be fully closed, therefore, transfer gate circuit 202 and 206 can not normally move under low amplitude of oscillation clock signal C K1 and CKB.Similarly, if the amplitude of oscillation level drops of clock signal C K1 ' and CKB ' is low to moderate low level, when clock signal CK1 ' and CKB ' vibration is when having low level peak value, the PMOS transistor 215 and 225 of latch cicuit 204 and 208 can not be fully closed, therefore, latch cicuit 204 and 208 can not normally move under low amplitude of oscillation clock signal C K1 and CKB.Contrary, the circuit of trigger 400 as shown in Figure 3 can normally run under the clock signal C KB and CK with low amplitude of oscillation level.Because transfer gate circuit 402 and 406 only comprises nmos pass transistor 402 and 406, and do not comprise PMOS transistor, when low amplitude of oscillation clock signal C KB and CK vibration is when having low level peak value, nmos pass transistor 402 and 406 can be closed completely, therefore, transfer gate circuit 402 and 406 can normally move under low amplitude of oscillation clock signal C K and CKB.In addition, different from the latch cicuit 204 of conventional trigger device 200 and 208 is, because latch cicuit 404 and 408 of the present invention does not comprise the PMOS transistor of being controlled by low amplitude of oscillation clock signal C K and CKB, therefore, latch cicuit 404 and 408 can normally move according to low amplitude of oscillation clock signal C K and CKB.Therefore, trigger 400 provided by the present invention can normally move according to low amplitude of oscillation clock signal C K and CKB.

Please refer to Fig. 4, the circuit diagram of the trigger that can receive low amplitude of oscillation clock signal 410 that Fig. 4 is another embodiment of the present invention.Trigger 410 shown in Fig. 4 comprises the circuit element similar to the trigger 400 shown in Fig. 3.In trigger 410 and 400, similar circuit element has identical Reference numeral.The difference of the trigger 400 shown in the trigger 410 shown in Fig. 4 and Fig. 3 is latch cicuit 404 ' and 408 '.Latch cicuit 404 ' as shown in Figure 4 comprises two nmos pass transistors 412 ' and 413 ', wherein the grid of nmos pass transistor 412 ' is coupled to low amplitude of oscillation clock signal C K, instead of node 416, and the grid of nmos pass transistor 413 ' is coupled to node 416, instead of low amplitude of oscillation clock signal C K.But the latch cicuit 404 ' shown in Fig. 4 has similar function to the latch cicuit 404 shown in Fig. 3.Latch cicuit 408 ' as shown in Figure 4 comprises two nmos pass transistors 422 ' and 423 ', wherein, the grid of nmos pass transistor 422 ' is coupled to reverse low amplitude of oscillation clock signal C KB, instead of node 426, and the grid of nmos pass transistor 423 ' is coupled to node 426, instead of reverse low amplitude of oscillation clock signal C KB.But the latch cicuit 408 ' shown in Fig. 4 has similar function to the latch cicuit 408 shown in Fig. 3.

Please refer to Fig. 5 A, what Fig. 5 A was one embodiment of the invention comprises the circuit diagram that can accelerate the trigger 500 of the input circuit 540 of signal generation speed (signal generation speed).Low amplitude of oscillation clock signal C K vibrates and can be reversed device 531 oppositely to produce a reverse low amplitude of oscillation clock signal C KB, and reverser 533 is followed reverse low amplitude of oscillation clock signal C KB oppositely with clocking CK1.Similar to the trigger 400 shown in Fig. 3, trigger 500 is to be controlled by low amplitude of oscillation clock signal C K and CKB.Trigger 500 can comprise reverser 501,503,505, and 507, two transfer gate circuit 502 and 506, and two latch cicuits 504 and 508, wherein, PMOS transistor 511 and 521 in trigger 500, reverser 514 and 524 and node 525 and PMOS transistor 411 and 421 in trigger 400, reverser 414 and 424 and node 425 similar.In certain embodiments, reverser 501,503,505, and 507 can be omitted.Trigger 500 further comprises input circuit 540, and input circuit 540 is for enabling latch cicuit 508 to accelerate to produce output signal in node 526.Input circuit 540 is coupled between node 516 and node 526, and it comprises two nmos pass transistors 541 and 542.The grid of nmos pass transistor 541 is coupled to node 516, and drain electrode is coupled to node 526.Nmos pass transistor 542 is coupled between the source electrode and ground voltage DVSS of nmos pass transistor 541, and the grid of nmos pass transistor 542 is coupled to low amplitude of oscillation clock signal C K.In the time that the voltage of node 516 and low amplitude of oscillation clock signal C K is all positioned at logic high, nmos pass transistor 541 and 542 be unlocked with by the lower voltage of node 526 to ground voltage DVSS, output signal to node 526 thereby accelerate to produce.In certain embodiments, the position of nmos pass transistor 541 and 542 can be exchanged, and the grid of nmos pass transistor 541 is still coupled to node 516, and the grid of nmos pass transistor 542 is still coupled to low amplitude of oscillation clock signal C K.

Please refer to Fig. 5 B, what Fig. 5 B was another embodiment of the present invention comprises the circuit diagram that can accelerate the trigger 510 of the input circuit 540 ' of signal generation speed.Trigger 510 has the circuit structure similar with the trigger 500 shown in Fig. 5 A.In trigger 500 and trigger 510, similar circuit element has identical Reference numeral.The difference of trigger 510 and trigger 500 is that input circuit 540 ' is different from the input circuit 540 of Fig. 5 A, and wherein, input circuit 540 ' enables latch cicuit 508 and outputs signal to node 526 to accelerate to produce.Input circuit 540 ' is coupled between node 515 and node 526, and comprises PMOS transistor 541 ' and nmos pass transistor 542 '.The grid of PMOS transistor 541 ' is coupled to node 515, and source electrode is coupled to node 526.Nmos pass transistor 542 ' is coupled between the drain electrode and ground voltage DVSS of PMOS transistor 541 ', and the grid of nmos pass transistor 542 ' is coupled to low amplitude of oscillation clock signal C K.When the voltage of node 515 is positioned at logic low, and low amplitude of oscillation clock signal C K is positioned at logic high, PMOS transistor 541 ' and nmos pass transistor 542 ' be all unlocked with by the lower voltage of node 526 to ground voltage DVSS, output signal to node 526 thereby accelerate to produce.Therefore, the nmos pass transistor 541 of the input circuit 540 shown in Fig. 5 A can be substituted by the PMOS transistor 541 ' of the input circuit 540 ' shown in Fig. 5 B.In certain embodiments, transistor 541 ' and 542 ' position can exchange, and the grid of PMOS transistor 541 ' is still coupled to node 515, and the grid of nmos pass transistor 542 ' is still coupled to low amplitude of oscillation clock signal C K.

Please refer to Fig. 5 C, what Fig. 5 C was one embodiment of the invention comprises two circuit diagrams that can accelerate the trigger 520 of the input circuit 540 and 550 of signal generation speed.Trigger 520 has the circuit structure similar to the trigger 500 shown in Fig. 5 A.In trigger 500 and trigger 520, similar circuit element has identical Reference numeral.The difference of trigger 520 and trigger 500 is input circuit 550, and input circuit 550 enables latch cicuit 504 to accelerate producing reverse data-signal to node 516.Input circuit 550 is coupled between node 509 and node 516, and comprises two nmos pass transistors 551 and 552.The grid of nmos pass transistor 551 is coupled to node 509, and drain electrode is coupled to node 516.Nmos pass transistor 552 is coupled between the source electrode and ground voltage DVSS of nmos pass transistor 551, and the grid of nmos pass transistor 552 is coupled to reverse low amplitude of oscillation clock signal C KB.When voltage and the reverse low amplitude of oscillation clock signal C KB of node 509 are all positioned at logic high, nmos pass transistor 551 and 552 all open with by the lower voltage of node 516 to ground voltage DVSS, thereby accelerate to produce reverse data-signal to node 516.In certain embodiments, the position of nmos pass transistor 541 and 542 can exchange, and the grid of nmos pass transistor 541 is still coupled to node 516, and the grid of nmos pass transistor 542 is still coupled to low amplitude of oscillation clock signal C K.In certain embodiments, the position of nmos pass transistor 551 and 552 can exchange, and the grid of nmos pass transistor 551 is still coupled to node 509, and the grid of nmos pass transistor 552 is still coupled to reverse low amplitude of oscillation clock signal C KB.

Please refer to Fig. 5 D, what Fig. 5 D was another embodiment of the present invention comprise two can accelerate signal and produce the input circuit 540 of speed and the circuit diagram of 550 ' trigger 530.Trigger 530 has the circuit structure similar to the trigger 500 shown in Fig. 5 A.In trigger 500 and trigger 530, similar circuit element has identical Reference numeral.The difference of trigger 530 and trigger 500 is input circuit 550 ', and input circuit 550 ' enables latch cicuit 504 to accelerate producing reverse data-signal to node 516.Input circuit 550 ' is coupled between node 519 and node 516, and comprises PMOS transistor 551 ' and nmos pass transistor 552 '.The grid of PMOS transistor 551 ' is coupled to node 519, and source electrode is coupled to node 516.Nmos pass transistor 552 ' is coupled between the drain electrode and ground voltage DVSS of PMOS transistor 551 ', and the grid of nmos pass transistor 552 ' is coupled to reverse low amplitude of oscillation clock signal C KB.When the voltage of node 519 is positioned at logic low and reverse low amplitude of oscillation clock signal C KB is positioned at logic high, PMOS transistor 551 ' and nmos pass transistor 552 ' all open with by the lower voltage of node 516 to ground voltage DVSS, output signal to node 516 thereby accelerate to produce.Therefore, the nmos pass transistor 551 of the input circuit 550 shown in Fig. 5 C can be replaced by the PMOS transistor 551 ' of the input circuit 550 ' shown in Fig. 5 D.In certain embodiments, the position of nmos pass transistor 541 and 542 can exchange, and the grid of nmos pass transistor 541 is still coupled to node 516, and the grid of nmos pass transistor 542 is still coupled to low amplitude of oscillation clock signal C K.In certain embodiments, transistor 551 ' and 552 ' position can exchange, and the grid of PMOS transistor 551 ' is still coupled to node 519, and the grid of nmos pass transistor 552 ' still couples reverse low amplitude of oscillation clock signal C KB.

Fig. 5 E is the circuit diagram of the trigger that comprises two input circuits 560 of another embodiment of the present invention.Fig. 5 F is the circuit diagram of the trigger that comprises two input circuits 570 of another embodiment of the present invention.Except the input circuit 540 of trigger 520 is replaced by the input circuit 540 ' of Fig. 5 B, the trigger 560 shown in Fig. 5 E has the circuit structure similar to the trigger 520 shown in Fig. 5 C.Except the input circuit 540 of trigger 530 is replaced by the input circuit 540 ' of Fig. 5 B, the trigger 570 shown in Fig. 5 F has the circuit structure similar to the trigger 530 shown in Fig. 5 D.In certain embodiments, transistor 541 ' and 542 ' position can exchange, and the grid of PMOS transistor 541 ' is still coupled to node 515, and the grid of nmos pass transistor 542 ' is still coupled to low amplitude of oscillation clock signal C K.In certain embodiments, the position of the nmos pass transistor 551 and 552 in Fig. 5 E can exchange, and the grid of nmos pass transistor 551 is still coupled to node 509, and the grid of nmos pass transistor 552 is still coupled to reverse low amplitude of oscillation clock signal C KB.In certain embodiments, the transistor 551 ' in Fig. 5 F and 552 ' position can exchange, and the grid of PMOS transistor 551 ' is still coupled to node 519, and the grid of nmos pass transistor 552 ' is still coupled to reverse low amplitude of oscillation clock signal C KB.

Fig. 5 G is the circuit diagram of the trigger that comprises two input circuits 580 of another embodiment of the present invention.Fig. 5 H is the circuit diagram of the trigger that comprises two input circuits 590 of another embodiment of the present invention.Except the input circuit 550 ' and 540 ' of trigger 570 is replaced by respectively the input circuit 582 and 584 of Fig. 5 G, the trigger 580 shown in Fig. 5 G has the circuit structure similar to the trigger 570 shown in Fig. 5 F.Input circuit 582 comprises nmos pass transistor 586.Nmos pass transistor 586 is coupled between input node 519 and node 516, and the grid of nmos pass transistor 586 is coupled to reverse low amplitude of oscillation clock signal C KB.In the time that reverse low amplitude of oscillation clock signal C KB is positioned at logic high, nmos pass transistor 586 is unlocked to be coupled to node 519 and node 516, thereby accelerates the signal transmission between node 519 and 516.Input circuit 584 comprises nmos pass transistor 588.Nmos pass transistor 588 is coupled between node 515 and node 526, and the grid of nmos pass transistor 588 is coupled to low amplitude of oscillation clock signal C K.When low amplitude of oscillation clock signal C K is positioned at logic high, nmos pass transistor 588 is unlocked to be coupled to node 515 and node 526, thereby accelerates the signal transmission between node 515 and 526.Except the nmos pass transistor 586 and 588 of the input circuit 582 and 584 of the trigger 580 shown in Fig. 5 G is replaced by respectively the input circuit 582 ' and 584 ' PMOS transistor 586 ' and 588 ' of Fig. 5 H, the trigger 590 shown in Fig. 5 H has the circuit structure similar to the trigger 580 shown in Fig. 5 G.When low amplitude of oscillation clock signal C K is positioned at logic low, PMOS transistor 586 ' is unlocked to be coupled to node 519 and node 516, thereby accelerates the signal transmission between node 519 and 516.When reverse low amplitude of oscillation clock signal C KB is positioned at logic low, PMOS transistor 588 ' is unlocked to be coupled to node 515 and node 526, thereby accelerates the signal transmission between node 515 and 526.

In certain embodiments, the nmos pass transistor 412 ' and 413 ' that the nmos pass transistor 512 and 513 in the latch cicuit 504 shown in Fig. 5 A to Fig. 5 H can be replaced by the latch cicuit 404 ' shown in Fig. 4.And the nmos pass transistor 422 ' and 423 ' that the nmos pass transistor 522 and 523 in the latch cicuit 508 shown in Fig. 5 A to Fig. 5 H can be replaced by the latch cicuit 408 ' shown in Fig. 4.

Please refer to Fig. 6, the circuit diagram of the trigger 600 of the reception reset signal (reset bar signal) that Fig. 6 is another embodiment of the present invention.Trigger 600 has circuit structure and the circuit function similar to the trigger 580 shown in Fig. 5 G.Low amplitude of oscillation clock signal C K vibrates and can be reversed device 631 oppositely to produce a reverse low amplitude of oscillation clock signal C KB, and reverser 633 is followed reverse low amplitude of oscillation clock signal C KB oppositely with clocking CK1.In one embodiment, trigger 600 comprises: reverser 601,603,605, and 607, two transfer gate circuit 602 and 606, and two latch cicuits 604 and 608.In certain embodiments, reverser 601,603,605, and 607 can be omitted.In the time that reset signal RB is positioned at logic low, reset signal RB is used to the output voltage of output node Q to be reset to logic low-voltage.According to the present embodiment, transfer gate circuit 602 is nmos pass transistor, and it is coupled between receiving node 609 and node 615, has a grid that is coupled to reverse low amplitude of oscillation clock signal C KB.Transfer gate circuit 602 receives the data-signal from receiving node 609, and in the time that reverse low amplitude of oscillation clock signal C KB is positioned at logic high, will be passed to node 615 from the data-signal of receiving node 609.In the time that reverse low amplitude of oscillation clock signal C KB is positioned at logic high, transfer gate circuit 602 (nmos pass transistor) is unlocked to be passed to node 615 from the data-signal of receiving node 609.Latch cicuit 604 is coupled between node 615 and node 616, in the time that reset signal RB is positioned at logic high, receive from the data-signal of node 615, and by this data-signal oppositely to produce processed data-signal to node 616.According to the present embodiment, transfer gate circuit 606 is nmos pass transistor, be coupled between node 616 and node 625, there is the grid that is coupled to low amplitude of oscillation clock signal C K, and in the time that low amplitude of oscillation clock signal C K is positioned at logic high, the processed data-signal from node 616 is passed to node 625.When low amplitude of oscillation clock signal C K is positioned at logic high, transfer gate circuit 606 (nmos pass transistor) is unlocked that the processed data-signal from node 616 is passed to node 625.Latch cicuit 608 is coupled between node 625 and node 626, receive processed data-signal from node 625, and in the time that reset signal RB is positioned at logic high, processed data-signal is oppositely outputed signal to node 626 to produce one, and in the time that reset signal RB is positioned at logic low, produce a logic high voltage to node 626.In the time that reset signal RB is positioned at logic low, latch cicuit 608 produces a logic high voltage using the output signal on node 626, and reverser 603 by the logic high voltage on node 626 oppositely to produce a logic low-voltage to output node Q.

Latch cicuit 608 has the circuit structure similar with the combination of input circuit 584 to the latch cicuit 508 shown in Fig. 5 G.The difference of the combination of latch cicuit 608 and latch cicuit 508 and input circuit 584 is: latch cicuit 608 has and non-(NAND) door 624.NAND gate 624 is carried out NOT-AND operation to reset signal RB and from the processed data-signal of node 625, outputs signal to node 626 to produce one.Therefore, when reset signal, RB is positioned at logic low, and latch cicuit 608 produces a logic high voltage and exports node 626 to as output signal.

Latch cicuit 604 has the circuit structure similar with the combination of input circuit 582 to the latch cicuit 504 shown in Fig. 5 G.The difference of the combination of latch cicuit 604 and latch cicuit 504 and input circuit 582 is: latch cicuit 604 has or non-(NOR) door 614.NOR gate 614 is carried out NOR operation to reverse reset signal and from the data-signal of node 615, to produce processed data-signal to node 616.Therefore, when reset signal, RB is positioned at logic high, and NOR gate 614 can be used as a reverser and carrys out the oppositely data-signal from node 615, to produce processed data-signal to node 616.Another difference of the combination of latch cicuit 604 and latch cicuit 504 and input circuit 582 is: the nmos pass transistor 617 of latch cicuit 604 is coupled between the drain electrode of node 616 and nmos pass transistor 618.The grid of nmos pass transistor 617 is coupled to reset signal RB.When reset signal, RB is positioned at logic low, and nmos pass transistor 617 is closed to disconnect the data path from node 619 to node 616.

When reset signal, RB is positioned at logic high, and while having a new input signal D input, reverse low amplitude of oscillation clock signal C KB can be positioned at logic high, and low amplitude of oscillation clock signal C K can be positioned at logic low.Then, transfer gate circuit (nmos pass transistor) 602 is passed to data-signal the node 615 of latch cicuit 604 from receiving node 609, nmos pass transistor 613 cuts off the feedback path of latch cicuit 604, transfer gate circuit (nmos pass transistor) 606 is closed, and nmos pass transistor 623 keeps or set up the feedback path of latch cicuit 608.Then, latch cicuit 604 receives data-signal from node 615, and by this data-signal oppositely to produce reverse data-signal to node 616.Because transfer gate circuit 606 is closed, latch cicuit 608 is by latch reverse data-signal on last stage, instead of reception is corresponding to the reverse data-signal of new input signal D.Therefore, the value of the reverse output signal of output node Q will equal the value of a upper input signal, instead of the value of new input signal D.Next, reverse low amplitude of oscillation clock signal C KB can be changed to and be positioned at logic low and low amplitude of oscillation clock signal C K can be positioned at logic high.Then, transfer gate circuit 602 is closed, nmos pass transistor 613 keeps or sets up the feedback path of latch cicuit 604, transfer gate circuit 606 will be passed to the node 625 of latch cicuit 608 from the reverse data-signal of node 616, and nmos pass transistor 623 cuts off the feedback path of latch cicuit 608.The then reverse reverse data-signal of latch cicuit 608 outputs signal to node 626 to produce one.Reverser 603 then by the output signal of node 626 oppositely to produce reverse output node Q that outputs signal to, and the value of this reverse output signal of output node Q equals the value of new input signal D.When reset signal, RB is positioned at logic low, and latch cicuit 608 produces a logic high voltage to node 626, and then, the value of the signal on output node Q is reset to logic low.

In certain embodiments, the nmos pass transistor 612 and 613 of the latch cicuit 604 shown in Fig. 6 can be replaced by the nmos pass transistor 412 ' and 413 ' of the latch cicuit 404 ' shown in Fig. 4.And the nmos pass transistor 622 and 623 of the latch cicuit 608 shown in Fig. 6 can be replaced by the nmos pass transistor 422 ' and 423 ' of the latch cicuit 408 ' shown in Fig. 4.

Please refer to Fig. 7, the circuit diagram of the trigger 700 of the reception signalization (set bar signal) that Fig. 7 is another embodiment of the present invention.Trigger 700 has circuit structure and the circuit function similar to the trigger 580 shown in Fig. 5 G.Low amplitude of oscillation clock signal C K vibrates and can be reversed device 731 oppositely to produce a reverse low amplitude of oscillation clock signal C KB, and reverser 733 is followed reverse low amplitude of oscillation clock signal C KB oppositely with clocking CK1.In one embodiment, trigger 700 comprises reverser 701,703,705, and 707, two transfer gate circuit 702 and 706, and two latch cicuits 704 and 708.In certain embodiments, reverser 701,703,705, and 707 can be omitted.In the time that signalization SB is positioned at logic low, the output voltage that signalization SB is used to output node Q is set to logic high voltage.According to the present embodiment, transfer gate circuit 702 is nmos pass transistor, it is coupled between receiving node 709 and node 715, there is a grid that is coupled to reverse low amplitude of oscillation clock signal C KB, transfer gate circuit 702 receives the data-signal from receiving node 709, and in the time that reverse low amplitude of oscillation clock signal C KB is positioned at logic high, will be passed to node 715 from the data-signal of receiving node 709.In the time that reverse low amplitude of oscillation clock signal C KB is positioned at logic high, transfer gate circuit 702 (nmos pass transistor) is unlocked to be passed to node 715 from the data-signal of receiving node 709.Latch cicuit 704 is coupled between node 715 and node 716, in the time that signalization SB is positioned at logic high, receive from the data-signal of node 715, and by this data-signal oppositely to produce processed data-signal to node 716.And in the time that signalization SB is positioned at logic low, latch cicuit 704 produces a logic high voltage and transfers to node 716 as processed data-signal.According to the present embodiment, transfer gate circuit 706 is nmos pass transistor, be coupled between node 716 and node 725, there is the grid that is coupled to low amplitude of oscillation clock signal C K, and in the time that low amplitude of oscillation clock signal C K is positioned at logic high, the processed data-signal from node 716 is passed to node 725.In the time that low amplitude of oscillation clock signal C K is positioned at logic high, transfer gate circuit 706 (nmos pass transistor) is unlocked that the processed data-signal from node 716 is passed to node 725.Latch cicuit 708 is coupled between node 725 and node 726, receives processed data-signal from node 725, and in the time that signalization SB is positioned at logic high, processed data-signal is oppositely outputed signal to node 726 to produce one.In the time that signalization SB is positioned at logic low, latch cicuit 704 produces a logic high voltage to export node 716 to as processed data-signal, latch cicuit 708 produces a logic low-voltage to export node 726 to as output signal, and reverser 703 by the logic low-voltage on node 726 oppositely to produce a logic high voltage to output node Q.

Latch cicuit 704 has the circuit structure similar with the combination of input circuit 582 to the latch cicuit 504 shown in Fig. 5 G.The difference of the combination of latch cicuit 704 and latch cicuit 504 and input circuit 582 is: latch cicuit 704 has NAND gate 714.NAND gate 714 is carried out a NOT-AND operation to signalization SB and from the data-signal of node 715, to produce a processed data-signal to node 716.Therefore,, in the time that signalization SB is positioned at logic low, latch cicuit 704 produces a logic high voltage to export node 716 to as processed data-signal.Another difference of the combination of latch cicuit 704 and latch cicuit 504 and input circuit 582 is: the nmos pass transistor 717 of latch cicuit 704 is coupled between the drain electrode of node 716 and nmos pass transistor 718.The grid of nmos pass transistor 717 is coupled to signalization SB.In the time that signalization SB is positioned at logic low, nmos pass transistor 717 is closed to disconnect the data path from node 719 to node 716.

Latch cicuit 708 has the circuit structure similar with the combination of input circuit 584 to the latch cicuit 508 shown in Fig. 5 G.The difference of the combination of latch cicuit 708 and latch cicuit 508 and input circuit 584 is: latch cicuit 708 has NOR gate 724.NOR gate 724 is carried out NOR operation to reverse signalization and from the processed data-signal of node 725, outputs signal to node 726 to produce one.Therefore,, in the time that signalization SB is positioned at logic high, NOR gate 724 is carried out the oppositely processed data-signal from node 725 as a reverser, outputs signal to node 726 to produce.

When signalization, SB is positioned at logic high, and while having a new input signal D input, reverse low amplitude of oscillation clock signal C KB can be positioned at logic high, and low amplitude of oscillation clock signal C K can be positioned at logic low.Then, transfer gate circuit (nmos pass transistor) 702 is passed to data-signal the node 715 of latch cicuit 704 from receiving node 709, nmos pass transistor 713 cuts off the feedback path of latch cicuit 704, transfer gate circuit (nmos pass transistor) 706 is closed, and nmos pass transistor 723 keeps or set up the feedback path of latch cicuit 608.Then, latch cicuit 704 receives data-signal from node 715, and by this data-signal oppositely to produce reverse data-signal to node 716.Because transfer gate circuit 706 is closed, latch cicuit 708 is by latch reverse data-signal on last stage, instead of reception is corresponding to the reverse data-signal of new input signal D.Therefore, the value of the reverse output signal of output node Q will equal the value of a upper input signal, instead of the value of new input signal D.Next, reverse low amplitude of oscillation clock signal C KB can be changed to and be positioned at logic low and low amplitude of oscillation clock signal C K can be positioned at logic high.Then, transfer gate circuit 702 is closed, nmos pass transistor 713 keeps or sets up the feedback path of latch cicuit 704, transfer gate circuit 706 will be passed to the node 725 of latch cicuit 708 from the reverse data-signal of node 716, and nmos pass transistor 723 cuts off the feedback path of latch cicuit 708.The then reverse reverse data-signal of latch cicuit 708 outputs signal to node 726 to produce one.Reverser 703 then by the output signal of node 726 oppositely to produce reverse output node Q that outputs signal to, and the value of this reverse output signal of output node Q equals the value of new input signal D.When signalization, SB is positioned at logic low, and latch cicuit 708 produces a logic low-voltage to export node 726 to as output signal, and then, the value of the signal on output node Q is set to logic high.

In certain embodiments, the nmos pass transistor 712 and 713 of the latch cicuit 704 shown in Fig. 7 can be replaced by the nmos pass transistor 412 ' and 413 ' of the latch cicuit 404 ' shown in Fig. 4.And the nmos pass transistor 722 and 723 of the latch cicuit 708 shown in Fig. 7 can be replaced by the nmos pass transistor 422 ' and 423 ' of the latch cicuit 408 ' shown in Fig. 4.

Please refer to Fig. 8, the circuit diagram of the reception reset signal that Fig. 8 is another embodiment of the present invention and the trigger 800 of signalization.Low amplitude of oscillation clock signal C K vibrates and can be reversed device 831 oppositely to produce a reverse low amplitude of oscillation clock signal C KB, and reverser 833 is followed reverse low amplitude of oscillation clock signal C KB oppositely with clocking CK1.In one embodiment, trigger 800 comprises reverser 801,803,805 and 807, two transfer gate circuit 802 and 806, and two latch cicuits 804 and 808.In certain embodiments, reverser 801,803,805 and 807 can be omitted.In the time that reset signal RB is positioned at logic low, reset signal RB is used to the output voltage of output node Q to be reset to logic low-voltage.In the time that signalization SB is positioned at logic low, the output voltage that signalization SB is used to output node Q is set to logic high voltage.According to the present embodiment, transfer gate circuit 802 is nmos pass transistor, it is coupled between receiving node 809 and node 815, there is a grid that is coupled to reverse low amplitude of oscillation clock signal C KB, transfer gate circuit 802 receives the data-signal from receiving node 809, and in the time that reverse low amplitude of oscillation clock signal C KB is positioned at logic high, will be passed to node 815 from the data-signal of receiving node 809.In the time that reverse low amplitude of oscillation clock signal C KB is positioned at logic high, transfer gate circuit 802 (nmos pass transistor) is unlocked to be passed to node 815 from the data-signal of receiving node 809.The latch cicuit 804 of trigger 800 has circuit structure and the circuit function similar to trigger 700 latch cicuits 704 shown in Fig. 7.Latch cicuit 804 is coupled between node 815 and node 816, receive the data-signal from node 815, in the time that signalization SB is positioned at logic high, by this data-signal oppositely to produce processed data-signal to node 816, and in the time that signalization SB is positioned at logic low, produces a logic high voltage and export node 816 to as processed data-signal.According to the present embodiment, transfer gate circuit 806 is nmos pass transistor, it is coupled between receiving node 816 and node 825, there is a grid that is coupled to low amplitude of oscillation clock signal C K, in the time that low amplitude of oscillation clock signal C K is positioned at logic high, the processed data-signal from receiving node 816 is passed to node 825.In the time that low amplitude of oscillation clock signal C K is positioned at logic high, transfer gate circuit 806 (nmos pass transistor) is unlocked that the processed data-signal from node 816 is passed to node 825.The latch cicuit 808 of trigger 800 has circuit structure and the circuit function similar to the latch cicuit 608 of the trigger 600 shown in Fig. 6.Latch cicuit 808 is coupled between node 825 and node 826, receive processed data-signal from node 825, in the time that reset signal RB is positioned at logic high, processed data-signal is oppositely outputed signal to node 826 to produce one, and in the time that reset signal RB is positioned at logic low, produce a logic high voltage to export node 826 to as output signal.In the time that reset signal RB is positioned at logic low, latch cicuit 808 produces a logic high voltage to export node 826 to as output signal, and reverser 803 by the logic high voltage on node 826 oppositely to produce a logic low-voltage to output node Q.In the time that signalization SB is positioned at logic low, latch cicuit 804 produces a logic high voltage to export node 816 to as processed data-signal, and latch cicuit 808 then oppositely this processed data-signal export node 826 to produce a logic low-voltage to as output signal, reverser 803 by the logic low-voltage on node 826 oppositely to produce a logic high voltage to output node Q.

Latch cicuit 804 has the circuit structure similar to the latch cicuit 704 shown in Fig. 7.Latch cicuit 804 comprises NAND gate 814, and NAND gate 814 is coupled between node 815 and node 816.NAND gate 816 is carried out a NOT-AND operation to signalization SB and from the data-signal of node 815, to produce a processed data-signal to node 816.Therefore,, in the time that signalization SB is positioned at logic low, latch cicuit 804 produces a logic high voltage to export node 816 to as processed data-signal.Latch cicuit 808 has the circuit structure similar to the latch cicuit 608 shown in Fig. 6.Latch cicuit 808 comprises NAND gate 824.NAND gate 824 is carried out NOT-AND operation to reset signal RB and from the processed data-signal of node 825, outputs signal to node 826 to produce one.Therefore,, in the time that reset signal RB is positioned at logic low, latch cicuit 808 produces a logic high voltage and exports node 826 to as output signal.

When signalization SB and reset signal RB are all positioned at logic high, and while having a new input signal D input, reverse low amplitude of oscillation clock signal C KB can be positioned at logic high, and low amplitude of oscillation clock signal C K can be positioned at logic low.Then, transfer gate circuit (nmos pass transistor) 802 is passed to data-signal the node 815 of latch cicuit 804 from receiving node 809, nmos pass transistor 813 cuts off the feedback path of latch cicuit 804, transfer gate circuit (nmos pass transistor) 806 is closed, and nmos pass transistor 829 keeps or set up the feedback path of latch cicuit 808.Then, latch cicuit 804 receives data-signal from node 815, and by this data-signal oppositely to produce reverse data-signal to node 815.Because transfer gate circuit 806 is closed, latch cicuit 808 is by latch reverse data-signal on last stage, instead of reception is corresponding to the reverse data-signal of new input signal D.Therefore, the value of the reverse output signal of output node Q will equal the value of a upper input signal, instead of the value of new input signal D.Next, reverse low amplitude of oscillation clock signal C KB can be changed to and be positioned at logic low and low amplitude of oscillation clock signal C K can be positioned at logic high.Then, transfer gate circuit 802 is closed, nmos pass transistor 813 keeps or sets up the feedback path of latch cicuit 804, transfer gate circuit 806 will be passed to the node 825 of latch cicuit 808 from the reverse data-signal of node 816, and nmos pass transistor 829 cuts off the feedback path of latch cicuit 808.The then reverse reverse data-signal of latch cicuit 808 outputs signal to node 826 to produce one.Reverser 803 then by the output signal of node 826 oppositely to produce reverse output node Q that outputs signal to, and the value of this reverse output signal of output node Q equals the value of new input signal D.When reset signal, RB is positioned at logic low, and latch cicuit 808 produces a logic high voltage to node 826, and then, the value of the signal on output node Q is reset to logic low.When signalization, SB is positioned at logic low, reset signal RB is positioned at logic high, and when low amplitude of oscillation clock signal C K is positioned at logic high, latch cicuit 804 produces a logic high voltage and exports node 816 to as signal, transfer gate circuit 806 will be passed to the node 825 of latch cicuit 808 from the signal of node 816, then, reverse this signal of latch cicuit 808 to be to produce a logic low-voltage to node 826 using as output signal, and is logic high by value value of establishing of the signal on output node Q.

In certain embodiments, the nmos pass transistor 818 and 813 of the latch cicuit 804 shown in Fig. 8 can be substituted by the nmos pass transistor 412 ' of the latch cicuit 404 ' shown in Fig. 4 and 413 '.And the nmos pass transistor 828 and 829 of the latch cicuit 808 shown in Fig. 8 can be substituted by the nmos pass transistor 422 ' of the latch cicuit 408 ' shown in Fig. 4 and 423 '.

Although the present invention discloses as above with preferred embodiment; so it is not in order to limit the present invention, and any the technical staff in the technical field, in not departing from the scope of the present invention; can do some and change, the scope that therefore protection scope of the present invention should define with claim is as the criterion.

Claims

1. a trigger, receives low amplitude of oscillation clock signal, and wherein, described low amplitude of oscillation clock signal is reversed to obtain reverse low amplitude of oscillation clock signal, and described trigger comprises:

The first nmos pass transistor, be coupled between receiving node and first node, there is the grid that is coupled to described reverse low amplitude of oscillation clock signal, and in the time that described reverse low amplitude of oscillation clock signal is positioned at logic high, will be passed to described first node from the data-signal of described receiving node;

The first latch cicuit, is coupled between described first node and Section Point, by described data-signal oppositely to produce reverse data-signal to described Section Point;

The second nmos pass transistor, be coupled between described Section Point and the 3rd node, there is the grid that is coupled to described low amplitude of oscillation clock signal, and in the time that described low amplitude of oscillation clock signal is positioned at described logic high, will be passed to described the 3rd node from the described reverse data-signal of described Section Point; And

The second latch cicuit, is coupled between described the 3rd node and the 4th node, and described reverse data-signal is oppositely outputed signal to described the 4th node to produce;

Wherein, described trigger further comprises the 3rd reverser, described the 3rd reverser is coupled between input node and described receiving node, receive input signal from described input node, and by described input signal oppositely to produce described data-signal to described receiving node, wherein, described trigger further comprises:

The 11 nmos pass transistor, is coupled between described input node and described Section Point, has the grid that is coupled to described reverse low amplitude of oscillation clock signal; And

The tenth bi-NMOS transistor, is coupled between described first node and described the 4th node, has the grid that is coupled to described low amplitude of oscillation clock signal.

2. trigger according to claim 1, is characterized in that: described the first latch cicuit comprises:

The first reverser, is coupled between described first node and described Section Point, by described data-signal oppositely with data-signal reverse described in producing to described Section Point;

The one PMOS transistor, is coupled between voltage source and described first node, has the grid that is coupled to described Section Point;

The 3rd nmos pass transistor, has the drain electrode that is coupled to described first node, and has the grid that is coupled to described Section Point; And

The 4th nmos pass transistor, is coupled between the source electrode and ground voltage of described the 3rd nmos pass transistor, has the grid that is coupled to described low amplitude of oscillation clock signal.

3. trigger according to claim 1, is characterized in that: described the second latch cicuit comprises:

The second reverser, is coupled between described the 3rd node and described the 4th node, and described reverse data-signal is oppositely outputed signal to described the 4th node described in producing;

The 2nd PMOS transistor, is coupled between voltage source and described the 3rd node, has the grid that is coupled to described the 4th node;

The 5th nmos pass transistor, has the drain electrode that is coupled to described the 3rd node, and has the grid that is coupled to described the 4th node; And

The 6th nmos pass transistor, is coupled between the source electrode and ground voltage of described the 5th nmos pass transistor, has the grid that is coupled to described reverse low amplitude of oscillation clock signal.

4. trigger according to claim 1, is characterized in that: described the first latch cicuit comprises:

The 3rd nmos pass transistor, has the drain electrode that is coupled to described first node, and has the grid that is coupled to described low amplitude of oscillation clock signal; And

The 4th nmos pass transistor, is coupled between the source electrode and ground voltage of described the 3rd nmos pass transistor, has the grid that is coupled to described Section Point.

5. trigger according to claim 1, is characterized in that: described the second latch cicuit comprises:

The 5th nmos pass transistor, has the drain electrode that is coupled to described the 3rd node, and has the grid that is coupled to described reverse low amplitude of oscillation clock signal; And

The 6th nmos pass transistor, is coupled between the source electrode and ground voltage of described the 5th nmos pass transistor, has the grid that is coupled to described the 4th node.

6. trigger according to claim 1, is characterized in that: described trigger further comprises:

The 3rd reverser, is coupled between input node and described receiving node, receives input signal from described input node, and by described input signal oppositely to produce described data-signal to described receiving node;

The 4th reverser, is coupled between described the 4th node and output node, by described output signal oppositely to produce the reverse described output node that outputs signal to; And

The 5th reverser and the 6th reverser, coupled in series, between described the 4th node and reverse output node, will be passed to described reverse output node from the described output signal of described the 4th node.

7. a trigger, receives low amplitude of oscillation clock signal, and wherein, described low amplitude of oscillation clock signal is reversed to obtain reverse low amplitude of oscillation clock signal, and described trigger comprises:

Wherein, described trigger further comprises the 3rd reverser, described the 3rd reverser is coupled between input node and described receiving node, receive input signal from described input node, and by described input signal oppositely to produce described data-signal to described receiving node, wherein said trigger further comprises:

The 5th PMOS transistor, is coupled between described input node and described Section Point, has the grid that is coupled to described low amplitude of oscillation clock signal; And

The 6th PMOS transistor, is coupled between described first node and described the 4th node, has the grid that is coupled to described reverse low amplitude of oscillation clock signal.

8. a trigger, receives low amplitude of oscillation clock signal, and wherein, described low amplitude of oscillation clock signal is reversed to obtain reverse low amplitude of oscillation clock signal, and described trigger comprises:

The first nmos pass transistor, be coupled between receiving node and first node, there is the grid that is coupled to described reverse low amplitude of oscillation clock signal, receive data-signal from described receiving node, and in the time that described reverse low amplitude of oscillation clock signal is positioned at logic high, the described data-signal from described receiving node is passed to described first node;

The first latch cicuit, is coupled between described first node and Section Point, in the time that reset signal is positioned at described logic high, by described data-signal oppositely to produce processed data-signal to described Section Point;

The second nmos pass transistor, be coupled between described Section Point and the 3rd node, there is the grid that is coupled to described low amplitude of oscillation clock signal, in the time that described low amplitude of oscillation clock signal is positioned at described logic high, described the 3rd node will be passed to from the described processed data-signal of described Section Point; And

The second latch cicuit, be coupled between described the 3rd node and the 4th node, in the time that described reset signal is positioned at described logic high, described processed data-signal is oppositely outputed signal to described the 4th node to produce, and in the time that described reset signal is positioned at logic low, produce logic high voltage to export described the 4th node to as described output signal;

Wherein, described reset signal is reversed to obtain reverse reset signal, and described trigger further comprises the first reverser, described the first reverser is coupled between input node and described receiving node, receive input signal from described input node, and oppositely to produce described data-signal to described receiving node, and described the first latch cicuit comprises by described input signal:

OR-NOT circuit, is coupled between described first node and described Section Point, and described reverse reset signal and described data-signal are carried out to NOR operation, to produce described processed data-signal to described Section Point;

The 3rd nmos pass transistor, has the drain electrode that is coupled to described first node, and has the grid that is coupled to described Section Point;

The 4th nmos pass transistor, is coupled between the source electrode and ground voltage of described the 3rd nmos pass transistor, has the grid that is coupled to described low amplitude of oscillation clock signal;

The 5th nmos pass transistor, has the drain electrode that is coupled to described Section Point, and has the grid that is coupled to described reset signal; And

The 6th nmos pass transistor, is coupled between the source electrode and described input node of described the 5th nmos pass transistor, has the grid that is coupled to described reverse low amplitude of oscillation clock signal.

9. trigger according to claim 8, is characterized in that: described the second latch cicuit comprises:

NAND gate circuit, is coupled between described the 3rd node and described the 4th node, and described reset signal and described processed data-signal are carried out to NOT-AND operation, described in producing, outputs signal to described the 4th node;

The 7th nmos pass transistor, has the drain electrode that is coupled to described the 3rd node, and has the grid that is coupled to described the 4th node;

The 8th nmos pass transistor, is coupled between the source electrode and ground voltage of described the 7th nmos pass transistor, has the grid that is coupled to described reverse low amplitude of oscillation clock signal; And

The 9th nmos pass transistor, is coupled between described the 4th node and described first node, has the grid that is coupled to described low amplitude of oscillation clock signal.

10. trigger according to claim 8, is characterized in that: described trigger further comprises:

The first reverser, is coupled between input node and described receiving node, receives input signal from described input node, and by described input signal oppositely to produce described data-signal to described receiving node;

The second reverser, is coupled between described the 4th node and output node, by the described output signal from described the 4th node oppositely to produce the reverse described output node that outputs signal to; And

The 3rd reverser and the 4th reverser, coupled in series, between described the 4th node and reverse output node, will be passed to described reverse output node from the described output signal of described the 4th node.

11. 1 kinds of triggers, receive low amplitude of oscillation clock signal, and wherein, described low amplitude of oscillation clock signal is reversed to obtain reverse low amplitude of oscillation clock signal, and described trigger comprises:

The first latch cicuit, is coupled between described first node and Section Point, in the time that signalization is positioned at described logic high, by described data-signal oppositely to produce processed data-signal to described Section Point;

The second nmos pass transistor, be coupled between described Section Point and the 3rd node, there is the grid that is coupled to described low amplitude of oscillation clock signal, and in the time that described low amplitude of oscillation clock signal is positioned at described logic high, described the 3rd node will be passed to from the described processed data-signal of described Section Point; And

The second latch cicuit, is coupled between described the 3rd node and the 4th node, in the time that described signalization is positioned at described logic low, produces logic low-voltage and exports described the 4th node to as output signal;

Wherein, described trigger further comprises the first reverser, described the first reverser is coupled between input node and described receiving node, receive input signal from described input node, and oppositely to produce described data-signal to described receiving node, and described the first latch cicuit comprises by described input signal:

NAND gate circuit, is coupled between described first node and described Section Point, and described signalization and described data-signal are carried out to NOT-AND operation, to produce described processed data-signal to described Section Point;

The 5th nmos pass transistor, has the drain electrode that is coupled to described Section Point, and has the grid that is coupled to described signalization; And

12. triggers according to claim 11, is characterized in that: described signalization is reversed to obtain reverse signalization, and described the second latch cicuit comprises:

OR-NOT circuit, is coupled between described the 3rd node and described the 4th node, and described reverse signalization and described processed data-signal are carried out to NOR operation, described in producing, outputs signal to described the 4th node;

13. triggers according to claim 11, is characterized in that: described trigger further comprises:

14. 1 kinds of triggers, receive low amplitude of oscillation clock signal, and wherein, described low amplitude of oscillation clock signal is reversed to obtain reverse low amplitude of oscillation clock signal, and described trigger comprises:

The first latch cicuit, be coupled between described first node and Section Point, in the time that signalization is positioned at described logic high, by described data-signal oppositely to produce processed data-signal to described Section Point, and in the time that described signalization is positioned at logic low, produce logic high voltage to export described Section Point to as described processed data-signal;

The second latch cicuit, be coupled between described the 3rd node and the 4th node, in the time that reset signal is positioned at described logic high, described processed data-signal is oppositely outputed signal to described the 4th node to produce, and in the time that described reset signal is positioned at described logic low, produce logic high voltage using the described output signal as described the 4th node;

The one PMOS transistor, is coupled between voltage source and described first node, has the grid that is coupled to described reset signal;

The 2nd PMOS transistor, is coupled between described voltage source and described first node, has the grid that is coupled to described Section Point;

The 3rd nmos pass transistor, has the drain electrode that is coupled to described first node, and has the grid that is coupled to described reset signal;

The 4th nmos pass transistor, has the drain electrode of the source electrode that is coupled to described the 3rd nmos pass transistor, and has the grid that is coupled to described Section Point;

The 5th nmos pass transistor, is coupled between the source electrode and ground voltage of described the 4th nmos pass transistor, has the grid that is coupled to described low amplitude of oscillation clock signal;

The 6th nmos pass transistor, has the drain electrode that is coupled to described Section Point, and has the grid that is coupled to described reset signal;

The 7th nmos pass transistor, has the drain electrode of the source electrode that is coupled to described the 6th nmos pass transistor, and has the grid that is coupled to described signalization; And

The 8th nmos pass transistor, is coupled between the source electrode and described input node of described the 7th nmos pass transistor, has the grid that is coupled to described reverse low amplitude of oscillation clock signal.

15. triggers according to claim 14, is characterized in that: described the second latch cicuit comprises:

The 3rd PMOS transistor, is coupled between voltage source and described the 3rd node, has the grid that is coupled to described signalization;

The 4th PMOS transistor, is coupled between described voltage source and described the 3rd node, has the grid that is coupled to described the 4th node;

The 9th nmos pass transistor, has the drain electrode that is coupled to described the 3rd node, and has the grid that is coupled to described signalization;

The tenth nmos pass transistor, has the drain electrode of the source electrode that is coupled to described the 9th nmos pass transistor, and has the grid that is coupled to described the 4th node;

The 11 nmos pass transistor, is coupled between the source electrode and ground voltage of described the tenth nmos pass transistor, has the grid that is coupled to described reverse low amplitude of oscillation clock signal; And

The tenth bi-NMOS transistor, is coupled between described the 4th node and described first node, has the grid that is coupled to described low amplitude of oscillation clock signal.

16. triggers according to claim 14, is characterized in that: described trigger further comprises: