WO2019184395A1

WO2019184395A1 - Flip-flop and integrated circuit

Info

Publication number: WO2019184395A1
Application number: PCT/CN2018/116241
Authority: WO
Inventors: 季秉武; 赵坦夫; 周云明; 樊敏; 李志彦; 王云鹏
Original assignee: 华为技术有限公司
Priority date: 2018-03-27
Filing date: 2018-11-19
Publication date: 2019-10-03
Also published as: CN110311659A; CN110311659B

Abstract

A flip-flop (700) and an integrated circuit, wherein same are used to reduce the probability of the occurrence of the phenomenon of metastability of a flip-flop. The flip-flop (700) comprises: a first latch (701), a second latch (702), a delay unit (703), a detection unit (704), a switching unit (705) and a third latch (706), wherein the delay unit (703) is used to delay a first clock signal and then output a second clock signal; the first latch (701) is used to latch or output a data signal according to the second clock signal; the latch (702) is used to latch or output the data signal according to the first clock signal; the detection unit (704) is used to detect whether the first latch (701) or the second latch (702) is in a metastable state, and output a control signal to the switching unit (705) based on a detection result; the switching unit (705) is used to choose, according to the control signal, to output an output signal of the first latch (701) or an output signal of the second latch (702); and the third latch (706) is used to latch or output an output signal of the switching unit (705).

Description

Trigger and integrated circuit

The present application claims priority to Chinese Patent Application No. 201, 810, 026, 036, filed on March 27, 2018, the entire disclosure of which is hereby incorporated by reference. .

Technical field

The present application relates to the field of electronic technologies, and in particular, to a flip-flop and an integrated circuit.

Background technique

A flip-flop is an information storage device with a memory function and is a basic logic unit constituting a plurality of sequential circuits.

Figure 1 shows a D type flip-flop (DFF). Where din represents the input data signal, clk represents the input clock signal, dout represents the output signal, and rst represents the reset signal. The D flip-flop shown in Figure 1 is a rising edge triggered D flip-flop. The rising edge of the clock signal triggers the level state of the D flip-flop latch input signal and then outputs the latched level through the Q pin. .

In the prior art, for the D flip-flop shown in FIG. 1, a time window is defined near the rising edge of the clock signal, and in principle, the data signal din input in the time window should not be level-inverted. If the level flip occurs in the din window during this time window, some nodes in the D flip-flop may not be stable in the logic 0 or logic 1 level state, resulting in the output signal dout after the rising edge of the clock signal. It is in an indeterminate state for a period of time, that is, metastable state. The time during which the output signal dout is in an indeterminate state is referred to as a resolution time. After the decision time, the output signal dot will be randomly stabilized at 0 or 1.

Illustratively, as shown in FIG. 2, it is a timing diagram of input and output signals of a D flip-flop. Wherein, the input data signal din is level-inverted within a defined time window, and the output signal dout is in an intermediate level state between logic 0 and logic 1 for a period of time (Tmet), and finally stabilizes at logic 1.

When the D flip-flop appears metastable state, the output signal is finally randomly stabilized at logic 0 or logic 1, which causes a logical misjudgment of the output signal. In addition, the indeterminate state of the output signal during the decision time will also cause the next-stage circuit to produce metastable state, which affects the normal operation of the entire system.

Therefore, the trigger provided by the prior art may exhibit a metastable state, which leads to a logic misjudgment and a problem that the system cannot work normally.

Summary of the invention

The embodiment of the present application provides a flip-flop and an integrated circuit for reducing the probability of a metastable phenomenon of a trigger, preventing a logical misjudgment of the output signal of the trigger, and affecting normal operation of the system.

In a first aspect, an embodiment of the present application provides a trigger for latching and outputting an input data signal under control of a first clock signal, the trigger including: a first latch, a second lock a buffer, a delay unit, a detection unit, a switching unit, and a third latch. among them,

And a delay unit, configured to delay and output the second clock signal after delaying the first clock signal by a preset time.

The clock signal input end of the first latch is coupled to the delay unit to receive the second clock signal; the first latch is configured to latch or output the data signal according to the second clock signal.

The second latch is configured to latch or output the data signal according to the first clock signal.

The detecting unit is configured to detect whether the first latch or the second latch is in a metastable state, and send a control signal to the switching unit based on the detection result.

The switching unit is configured to select an output signal of the first latch or an output signal of the second latch according to the control signal.

The data input end of the third latch is connected to the output end of the switching unit for latching or outputting the output signal of the switching unit according to the first clock signal.

The switching unit can be implemented by a data selector having two input signals.

In the above solution, since there is a phase difference between the second clock signal used by the first latch and the first clock signal used by the second latch, the time at which the data signal input in the flip-flop is level-reversed If it is in the time window of the first clock signal (ie, the second latch is in metastable state), it is usually not in the time window of the second clock signal (ie, the first latch is not in metastable state) ). Similarly, when the data signal input in the flip-flop is level-inverted, if it is in the time window of the second clock signal (ie, the first latch is in metastable state), it is usually not in the first clock signal. Within the time window (ie the second latch is not in metastable state). Therefore, the first latch and the second latch are not simultaneously metastable.

In the flip-flop provided in the first aspect, when the detecting unit detects that the first latch is in a metastable state, the switching unit may select to output an output signal of the second latch according to the control signal; When the two latches are in metastability, the switching unit can select to output an output signal of the first latch according to the control signal. Therefore, by using the flip-flop provided by the first aspect, the signal output to the input end of the third latch can be in a stable state, so that the output signal of the flip-flop is in a stable state, and the probability of a metastable phenomenon of the flip-flop is reduced. In order to avoid the logic output of the trigger output signal, affecting the normal operation of the system.

The preset time may be set as follows: the preset time is greater than a sum of a setup time and a hold time of the first latch, and is smaller than a signal period of the first clock signal.

In the case where the preset time is set as above, since the phase difference between the first clock signal and the second clock signal is greater than the time window of the first clock signal (ie, the sum of the setup time and the hold time), and is smaller than the first clock signal Half of the signal period, and thus the time at which the data signal input by the flip-flop is level-flip cannot be simultaneously within the time window of the first clock signal and the time window of the second clock signal. That is to say, the first latch and the second latch are not simultaneously metastable, and the switching unit can certainly select when outputting the output signal of the first latch and the output signal of the second latch. Select a stable signal and output. Therefore, in the case where the preset time is set as above, the probability that the trigger exhibits a metastable state can be further reduced.

In addition, the preset time is shorter than the signal period of the first clock signal, so that the delay of the second clock signal compared to the first clock signal can be made smaller (less than the signal period of the first clock signal). That is, when the second latch generates a metastable state and the switching unit selects the output signal of the first latch, the delay time of the output signal of the first latch compared to the output signal of the second latch Smaller, so that the output signal delay time of the entire flip-flop is smaller, and the delay time is smaller than the signal period of the first clock signal.

In a possible design, when the switching unit selectively outputs the output signal of the first latch or the output signal of the second latch according to the control signal, the switching unit may be implemented as follows: the switching unit determines the first in the detecting unit When the latch is in metastable state, the output signal of the second latch is selected to be output; or, the switching unit selects to output the output signal of the first latch when the detecting unit determines that the second latch is in metastability.

With the above solution, the signal output from the switching unit to the input end of the third latch can be in a stable state, so that the output signal of the flip-flop is in a stable state, and the probability of the metastable phenomenon of the flip-flop is reduced.

As previously mentioned, the detection unit is operative to detect if the first or second latch is in a metastable state. Specifically, the detecting unit can have two specific implementations when detecting whether the first latch or the second latch is in a metastable state. The following two implementations are introduced separately.

First implementation

In a possible design, the detecting unit is configured to detect whether the first latch or the second latch is in a metastable state, specifically, the detecting unit detects the first latch or the second latch Check if the node is metastable.

In a first implementation, the detecting unit detects whether one of the first latch and the second latch is metastable. The control signal also only indicates if a particular latch is in a metastable state.

When the switching unit selectively outputs the output signal of the first latch or the output signal of the second latch, the switching unit may select: outputting the output signal of the other latch when the currently detected latch is in metastability The output signal of the currently detected latch is selected to be output when the currently detected latch is not in metastability.

In one possible design, the detecting unit may include a first inverter, a second inverter, and a first exclusive OR gate circuit. among them,

The first inverter is connected to the detecting node for outputting a low level when the voltage of the detecting node is greater than or equal to the first threshold, and outputting a high level when the voltage of the detecting node is lower than the first threshold.

a second inverter connected to the detecting node, configured to output a low level when the voltage of the detecting node is greater than or equal to the second threshold, and output a high level when the voltage of the detecting node is lower than the second threshold, the second threshold Less than the first threshold.

a first XOR gate circuit coupled to the first inverter and the second inverter for performing an exclusive OR operation on an output signal of the first inverter and an output signal of the second inverter, and The result of the operation is output as a control signal to the switching unit.

With the above scheme, when the latch in which the detecting node is located is in metastable state, the first XOR gate circuit outputs a high level; when the latch in which the detecting node is located is not in metastability, the first XOR gate circuit The output is low. Therefore, the level state of the control signal output by the detecting unit can represent whether the latch in which the detecting node is located is metastable, so that the switching unit can selectively output the output signal of the first latch according to the control signal or The output signal of the second latch.

In the flip-flop provided in the first aspect, the structure of the first latch can have the following two forms:

The first

The first latch includes a first clocked inverter, a second clocked inverter, and a third inverter; an input of the first clocked inverter inputs a data signal, and the first clocked inverter The output end is connected as a detecting node to the detecting unit, and is connected to the input end of the third inverter; the signal outputted by the output end of the third inverter is used as an output signal of the first latch; the second clocked inverter The input end is connected to the output end of the third inverter, and the output end of the second clocked inverter is connected to the output end of the first clocked inverter; wherein the first clocked inverter and the second clock The control inverter is alternately turned on under the second clock signal.

When the first latch adopts the above structure, if the first latch is in metastable state, the switching unit selects and outputs the output signal of the second latch. When the decision time of the first latch ends, the first latch will eventually stabilize at logic 0 or logic 1 randomly. At this time, the detecting unit detects that the first latch is not in metastable state, the switching unit will The output signal of the first latch is selected to be output according to a control signal output from the detecting unit. That is, the second latch outputs a signal to the third latch instead of the first latch when the first latch is in metastability, and the second latch when the first latch returns to steady state. The device does not work.

Second

The first latch includes a first clocked inverter, a second clocked inverter, and a third inverter; an input of the first clocked inverter inputs a data signal, and the first clocked inverter The output end is connected as a detecting node to the detecting unit, and is connected to the input end of the third inverter; the signal outputted by the output end of the third inverter is used as an output signal of the first latch; the second clocked inverter The input end is connected as the feedback end of the first latch to the output end of the switching unit, and the output end of the second clocked inverter is connected to the output end of the first clocked inverter; wherein, the first clocked reverse The phase comparator and the second clocked inverter are alternately turned on under the second clock signal.

With the above scheme, since the feedback terminal can feed back the stable level to the detecting node, the second structure is adopted, and the metastability of the detecting node can be detected in a shorter time than the first structure of the first latch. After being eliminated, the switching unit can switch after the metastable state is removed, and select the output signal of the output first latch.

In the flip-flop provided in the first aspect, the structure of the second latch can have the following two forms:

The first

The second latch includes a third clocked inverter, a fourth clocked inverter, and a fourth inverter; the input of the third clocked inverter inputs a data signal, and the third clocked inverter The output end is connected as a detecting node to the detecting unit, and is connected to the input end of the fourth inverter; the signal outputted by the output end of the fourth inverter is used as an output signal of the second latch; the fourth clocked inverter The input end is connected to the output end of the fourth inverter, and the output end of the fourth clocked inverter is connected to the output end of the third clocked inverter; wherein the third clocked inverter and the fourth clock The control inverter is alternately turned on under the first clock signal.

With the above scheme, if the second latch is in metastable state, the switching unit selects and outputs the output signal of the first latch. When the decision time of the second latch ends, the second latch will eventually stabilize at logic 0 or logic 1 randomly. At this time, the detecting unit detects that the second latch is not in metastable state, the switching unit will The output signal of the second latch is outputted according to the detection result of the detecting unit. That is, the first latch outputs a signal to the third latch instead of the second latch when the second latch is in metastability, and the first latch when the second latch returns to steady state. The device does not work.

Second

The second latch includes a third clocked inverter, a fourth clocked inverter, and a fourth inverter; the input of the third clocked inverter inputs a data signal, and the third clocked inverter The output end is connected as a detecting node to the detecting unit, and is connected to the input end of the fourth inverter; the signal outputted by the output end of the fourth inverter is used as an output signal of the second latch; the fourth clocked inverter The input end is connected as the feedback end of the second latch to the output end of the switching unit, and the output end of the fourth clocked inverter is connected to the output end of the third clocked inverter; wherein, the third clocked reverse The phase comparator and the fourth clocked inverter are alternately turned on under the first clock signal.

With the above scheme, since the feedback terminal can feed back the stable level to the detecting node, the second structure is adopted, and the metastability of the detecting node can be detected in a shorter time than the first structure of the second latch. After being eliminated, the switching unit can switch after the metastable state is removed, and select the output signal of the output second latch.

The above is an introduction to the first implementation of detecting whether the first latch or the second latch is in metastable state. The second implementation is described below.

Second implementation

In a possible design, when the detecting unit detects whether the first latch or the second latch is in metastability, the detecting unit is configured to: detect whether the first detecting node in the first latch is in Metastable, and detecting whether the second detected node in the second latch is in metastable state.

With the second implementation, the detecting unit detects whether the first latch and the second latch are in a metastable state. The control signal indicates whether the first latch is in a metastable condition and whether the second latch is in a metastable state.

When the switching unit selectively outputs the output signal of the first latch or the output signal of the second latch, the switching unit may select to output the output signal of the second latch when the first latch is in metastability, Afterwards, the output signal of the second latch is selected and outputted until the control signal indicates that the second latch is in metastable state, and the output signal of the first latch is selected to be output; likewise, the second latch is at In the metastable state, the output signal of the first latch is selected, and then the output signal of the first latch is selected until the control signal indicates that the first latch is in metastable state, and the second latch is selected for output. Output signal of the device.

It is not difficult to see that the second implementation manner has more nodes to be detected by the detecting unit than the first implementation manner, but the switching unit selects and outputs the output signal of the first latch or the output signal of the second latch. When it is, the number of switching signals is reduced.

In a possible implementation, the detecting unit includes a first detecting circuit and a second detecting circuit. The first detecting circuit is configured to detect whether the first detecting node is in a metastable state, and send the first to the switching unit based on the detection result. a second detection circuit is configured to detect whether the second detection node is in a metastable state, and send a second control signal to the switching unit based on the detection result; wherein the control signal includes the first control signal and the second control signal.

In the above scheme, the first control signal is used to indicate whether the first latch is in a metastable state, and the second control signal is used to indicate whether the second latch is in a metastable state.

In a possible implementation, the first detecting circuit includes: a first inverter connected to the first detecting node, configured to output a low level when the voltage of the first detecting node is greater than or equal to the first threshold, and Outputting a high level when the voltage of the first detecting node is lower than the first threshold; and connecting the second inverter to the first detecting node, and outputting the low power when the voltage of the first detecting node is greater than or equal to the second threshold Leveling, and outputting a high level when the voltage of the first detecting node is lower than the second threshold, the second threshold is less than the first threshold; the first XOR gate circuit is connected to the first inverter and the second inverter, And performing an exclusive OR operation on the output signal of the first inverter and the output signal of the second inverter, and outputting the result of the exclusive OR operation as a first control signal to the switching unit;

The second detecting circuit includes: a third inverter connected to the second detecting node, configured to output a low level when the voltage of the second detecting node is greater than or equal to the third threshold, and a voltage lower than the second detecting node a third threshold is outputting a high level; a fourth inverter is coupled to the second detecting node for outputting a low level when the voltage of the second detecting node is greater than or equal to a fourth threshold, and at the second detecting node When the voltage is lower than the fourth threshold, the high level is output, and the fourth threshold is smaller than the third threshold; the second exclusive OR circuit is connected to the third inverter and the fourth inverter, and is used for the third inverter The output signal and the output signal of the fourth inverter are XORed, and the result of the exclusive OR operation is output as a second control signal to the switching unit.

With the above solution, since the second threshold is smaller than the first threshold, the first XOR gate circuit outputs a high level when the first latch is in a metastable state; when the first latch is not in a metastable state, The first XOR gate outputs a low level. Therefore, the level state of the first control signal output by the first detecting circuit can be used to indicate whether the first latch is in a metastable state; likewise, since the fourth threshold is less than the third threshold, when the second latch is in At metastability, the second XOR gate outputs a high level; when the second latch is not in a metastable state, the second XOR gate outputs a low level. Therefore, the level state of the second control signal output by the second detecting circuit can indicate whether the second latch is in metastable state. The switching unit may selectively output an output signal of the first latch or an output signal of the second latch according to the first control signal and the second control signal.

In a second aspect, an embodiment of the present application provides an integrated circuit comprising the flip-flop provided in the above first aspect and any possible implementation manner thereof.

DRAWINGS

1 is a schematic diagram of a D flip-flop provided by the prior art;

2 is a timing diagram of input and output signals of a D flip-flop provided by the prior art;

FIG. 3 is a schematic diagram of an internal structure of a D flip-flop according to an embodiment of the present disclosure;

4 is a schematic structural diagram of a trigger system according to an embodiment of the present application;

FIG. 5 is a timing diagram of input and output signals of a trigger system according to an embodiment of the present disclosure;

6 is a timing diagram of input and output signals of another trigger system according to an embodiment of the present disclosure;

FIG. 7 is a schematic structural diagram of a first type of trigger provided by an embodiment of the present application;

FIG. 8 is a schematic structural diagram of a second type of trigger provided by an embodiment of the present application;

FIG. 9 is a schematic structural diagram of a third trigger provided by an embodiment of the present application;

FIG. 10 is a schematic structural diagram of a fourth trigger provided by an embodiment of the present application;

FIG. 11 is a schematic structural diagram of a fifth trigger provided by an embodiment of the present application;

FIG. 12 is a schematic structural diagram of a sixth trigger provided by an embodiment of the present application;

FIG. 13 is a schematic structural diagram of a seventh trigger provided by an embodiment of the present application;

FIG. 14 is a schematic structural diagram of an eighth trigger provided by an embodiment of the present application.

detailed description

Typically, a D flip-flop can consist of a low pass latch and a high pass latch, as shown in FIG. In Figure 3, the low-pass latch contains two clocked inverters (ie, first clocked inverter I1 and second clocked inverter I2) and one inverter (I3), high-pass latch The controller includes two clocked inverters (a third clocked inverter I4 and a fourth clocked inverter I5) and an inverter (I6). Among them, I3 and I6 are always in the on state, I1 and I5 are turned on when the clock signal is low, and I2 and I4 are turned on when the clock signal is high.

The flip-flop works as follows: When the input clock signal is low, the low-pass latch transfers the logic value of input D to node A and then to node B. At this time, I2 and I4 are turned off, and the data latched on the rising edge of the previous clock signal is held on the node C of the high-pass latch, and the data is transmitted to the output terminal Q of the flip-flop. When the input clock signal goes high, I1 and I5 are turned off, I2 and I4 are turned on, I2 and I3 of the low-pass latch are latched, and the high-pass latch transfers the logic value of input B to node C. The node C data is updated and then transmitted to the node Q, that is, the process of transferring the logical value of the input terminal D to the output terminal Q of the flip-flop.

As can be seen from the above principle, the D flip-flop shown in FIG. 3 is a rising edge triggered D flip-flop, that is, the rising edge of the clock signal triggers the level state of the data signal input by the flip-flop latch, and then passes through the Q tube. The level at which the foot output is acquired.

It should be noted that, in the flip-flop shown in FIG. 3, when the input clock signal is low level, the logic value of the input terminal D can be transmitted to the node B through the cooperation of I1, I2, and I3, so I1 is The latches consisting of I2 and I3 are called low-pass latches. When the input clock signal goes high, the logic value of input B can be transferred to node Q through the cooperation of I4, I5 and I6. Therefore, the latch composed of I4, I5 and I6 is called high-pass latch. Device.

The low-pass latch transmits the signal when the clock signal is low, by configuring the turn-on characteristics of I1 and I2. Similarly, the high-pass latch transmits the signal when the clock signal is high, by configuring I4. And the conduction characteristics of I5 are realized. In Figure 3, I1 and I5 are configured as clocked inverters that are turned on at a high level, and I2 and I4 are configured as clocked inverters that are turned on at a low level.

Then, it is not difficult to imagine that if the conduction characteristics of I1 and I2 are different from those of Figure 3 (for example, I1 is configured as a low-level clocked inverter, I2 is configured to be high-level. Clocked inverter), the latches composed of I1, I2 and I3 can be high-pass latches; if the conduction characteristics of I4 and I5 are different from those of Figure 3 (for example, I4 is configured as a high-level The clocked inverter is configured to configure I5 as a low-level clocked inverter. The latches of I4, I5, and I6 can be low-pass latches. At this time, the falling edge triggered D flip-flop can be realized by I1, I2, I3, I4, I5 and I6, and its working principle is similar to that of the rising edge triggered D flip-flop, and will not be described here.

As described in the background art, for the D flip-flop shown in FIG. 3, a time window is defined near the rising edge of the clock signal, and if the data signal din input on the time window is level-inverted, it may result in Some nodes in the D flip-flop cannot be stabilized at the logic 0 or logic 1 level state, resulting in a meta-stable phenomenon of the D flip-flop.

The time window may be composed of a setup time before the rising edge (ie, Ts in FIG. 2) and a hold time after the rising edge (ie, Th in FIG. 2). That is to say, in the Ts time before the rising edge of the clock signal and the Th time after the rising edge comes, the data signal din input in principle is not allowed to be level-inverted. If the data signal din is level-over at any time in Ts or Th, the trigger will appear metastable.

To reduce the probability of a metastable phenomenon in a flip-flop, multiple D flip-flops can be cascaded. As shown in FIG. 4, it is a trigger system that avoids metastable phenomena by cascading three D flip-flops. In this system, if the first-stage D flip-flop appears metastable, since the output of the first-stage D flip-flop will eventually stabilize at logic 0 or logic 1, then the second-level D flip-flop or the third-level D-trigger The receiver eliminates metastability after receiving a stable logic level.

Illustratively, the input and output timing diagram of the trigger system can be as shown in FIG. In FIG. 5, since the input data signal of the first-stage D flip-flop is level-inverted during the time window of the rising edge of the first clock signal, the first-stage D flip-flop exhibits a metastable state. After the decision time of the first stage D flip-flop, the first stage D flip-flop settles to logic 1 before the rising edge of the second clock signal. Since the input signal of the second stage D flip-flop does not level flip during the time window of the rising edge of the second clock signal, the metastable state can be eliminated in the second stage D flip-flop.

Illustratively, the input and output timing diagram of the trigger system can be as shown in FIG. 6. In Fig. 6, since the input data signal of the first stage D flip-flop is level-inverted during the time window of the rising edge of the first clock signal, the first-stage D flip-flop exhibits a metastable state. The first stage D flip-flop is still in the decision time when the rising edge of the second clock signal arrives, so the first stage D flip-flop is still metastable when the rising edge of the second clock signal arrives, and the second stage D flip-flop remains There is a metastable state. After the decision time of the second stage D flip-flop, the output of the second stage D flip-flop settles to logic 1 before the rising edge of the third clock signal. Since the input signal of the third-stage D flip-flop does not level flip during the time window of the rising edge of the third clock signal, the metastable state can be eliminated in the third-stage D flip-flop.

To eliminate the metastable state of the flip-flop by using the above-mentioned flip-flop cascade, multiple flip-flops need to be cascaded, and finally the output of the last-stage D flip-flop is used as the system output. Due to the greater number of cascaded D flip-flops, the lower the probability of metastable phenomena in the system, therefore, in order to reduce the probability of occurrence of metastability, cascaded multi-level (eg, three or five) D-triggering is required. At this time, since the input signal of the system can be latched and output through the multi-level D flip-flop, the system output will delay several clock signal cycles with respect to the system input, which affects the performance of the system. Especially when multiple systems interact, if the signal delay of each system is large, it will seriously affect the performance of multi-system interaction.

Therefore, the embodiment of the present application provides a flip-flop and an integrated circuit, which are used to reduce the probability of a metastable phenomenon of a trigger, avoid logical misjudgment of the trigger output signal, and affect the normal operation of the system.

In order to make the objects, technical solutions and advantages of the present application more clear, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

It should be noted that the plurality of parts referred to in the embodiments of the present application refer to two or more. In addition, it should be understood that in the description of the embodiments of the present application, the terms "first", "second" and the like are used only to distinguish the purpose of description, and are not to be understood as indicating or suggesting relative importance, nor understanding. Indicated or implied order.

FIG. 7 is a schematic structural diagram of a flip-flop according to an embodiment of the present application, for latching and outputting an input data signal under control of a first clock signal. The flip-flop 700 includes a first latch 701, a second latch 702, a delay unit 703, a detecting unit 704, a switching unit 705, and a third latch 706. among them,

The delay unit 703 is configured to delay and output the second clock signal after delaying the first clock signal by a preset time.

The clock signal input end of the first latch 701 is connected to the delay unit 703 to receive the second clock signal; the first latch 701 is configured to input the data signal to the data input end of the flip-flop 700 according to the second clock signal. Perform latching or output.

The second latch 702 is configured to latch or output a data signal input to the data input terminal of the flip-flop 700 according to the first clock signal.

The detecting unit 704 is configured to detect whether the first latch 701 or the second latch 702 is in a metastable state, and transmit a control signal to the switching unit 705 based on the detection result.

The two input ends of the switching unit 705 are respectively connected to the output end of the first latch 701 and the output end of the second latch 702, and the switching unit 705 is configured to selectively output the output of the first latch 701 according to the control signal. The signal or the output signal of the second latch 702.

The data input end of the third latch 706 is coupled to the output of the switching unit 705 for latching or outputting the output signal of the switching unit 705 according to the first clock signal.

It should be noted that, in the embodiment of the present application, the detecting unit 704 detects whether the first latch 701 or the second latch 702 is in a metastable state, and may have two specific meanings: Whether one of the first latch 701 or the second latch 702 is in a metastable state is detected; second, the detecting unit 704 simultaneously applies the first latch 701 and the second latch 702. Whether the two latches are in a metastable state is detected. In the flip-flop 700 shown in FIG. 7, it is shown that the detecting unit 704 detects only whether the first latch 701 is in a metastable state, or the detecting unit 704 detects only whether the second latch 702 is in a metastable state. The situation (indicated by the dotted line). In actual implementation, the detecting unit 704 can also detect whether the first latch 701 is in a metastable state and whether the second latch 702 is in a metastable state.

It should be noted that, in the embodiment of the present application, the conduction characteristics of the first latch 701 and the second latch 702 are the same, and the conduction characteristics of the third latch 706 and the first latch 701 (ie, The conduction characteristics of the second latch 702 are reversed.

Illustratively, if the first latch 701 transmits a signal when the clock signal is high, the second latch 702 also transmits a signal when the clock signal is high, and the third latch 706 is low at the clock signal. The signal is transmitted at level; that is, the first latch 701 and the second latch 702 are high pass latches and the third latch 706 is a low pass latch.

Illustratively, if the first latch 701 transmits a signal when the clock signal is low, the second latch 702 also transmits a signal when the clock signal is low, and the third latch 706 is high at the clock signal. The signal is transmitted at the level; that is, the first latch 701 and the second latch 702 are low pass latches, and the third latch 706 is a high pass latch.

As mentioned earlier, when a metastable state occurs, some nodes in the flip-flop cannot settle to the logic 0 or logic 1 level state, but lie between the intermediate level state between logic 0 and logic 1.

Illustratively, if the time at which the input data signal is level-inverted is within the time window of the first clock signal, the second latch 702 may exhibit a metastable state, and some of the second latch 702 The node cannot be stable at the logic 0 or logic 1 level state. If the time at which the input data signal is level-inverted is within the time window of the second clock signal, the first latch 701 may exhibit a metastable state, and some nodes in the first latch 701 cannot be stabilized. The level state of logic 0 or logic 1.

Therefore, when detecting that some nodes of the first latch 701 are in an intermediate level state between logic 0 and logic 1, the detecting unit 704 may determine that the first latch 701 is in a metastable state; the detecting unit 704 Upon detecting that some of the nodes of the second latch 702 are in an intermediate level state between logic 0 and logic 1, then it may be determined that the second latch 702 is in a metastable state.

In the flip-flop 700 shown in FIG. 7, the clock signal used by the second latch 702 is the first clock signal of the input flip-flop 700, and the clock signal used by the first latch 701 is the first clock signal. The second clock signal obtained after the delay unit 703 is delayed. Since there is a phase difference between the first clock signal and the second clock signal, it is not difficult to see that the time at which the data signal input in the flip-flop 700 is level-reversed is within the time window of the first clock signal (ie, the second lock) 702 is in metastable state and is typically not within the time window of the second clock signal (ie, first latch 701 is not in metastable state). Similarly, the time at which the data signal input in the flip-flop 700 is level-inverted is normally not in the first time if it is within the time window of the second clock signal (ie, the first latch 701 is in metastable state). Within the time window of the clock signal (ie, the second latch 702 is not in metastable state).

That is, the first latch 701 and the second latch 702 are typically not simultaneously metastable.

Then, in the embodiment of the present application, whether the first latch 701 or the second latch 702 is meta-stable can be detected by the detecting unit 704, and the first latch 701 is detected to be metastable. At this time, the switching unit 705 selects and outputs the output signal of the second latch 702; when detecting that the second latch 702 is in the metastable state, the switching unit 705 selects and outputs the output signal of the first latch 701.

In the embodiment of the present application, optionally, the switching unit 705 can be implemented by a data selector.

By the above operation, the signal output to the input terminal of the third latch 706 can be made to be in a steady state, so that the output signal of the flip-flop 700 is in a steady state, reducing the probability that the flip-flop 700 exhibits a metastable state.

In particular, the preset time delayed by the delay unit 703 may be greater than the sum of the setup time and the hold time of the first latch 701 and less than the signal period of the first clock signal.

In the case where the preset time is set as above, since the phase difference between the first clock signal and the second clock signal is greater than the time window of the first clock signal (ie, the sum of the setup time and the hold time), and is smaller than the first clock signal Half of the signal period, and thus the time at which the data signal input by the flip-flop 700 is level-flip cannot be simultaneously within the time window of the first clock signal and the time window of the second clock signal. That is, the first latch 701 and the second latch 702 are unlikely to be metastable at the same time, and the switching unit 704 is selectively outputting the output signal of the first latch 701 and the output of the second latch 702. When the signal is selected, it is possible to select a stable signal and output it. Therefore, in the case where the preset time is set as above, the probability that the flip-flop 700 exhibits a metastable state can be further reduced.

Further, the preset time is smaller than the signal period of the first clock signal, that is, the delay of the second clock signal compared to the first clock signal can be made smaller (less than the signal period of the first clock signal). That is, when the second latch 702 is metastable and the switching unit 705 selects the output signal of the first latch 701, the output signal of the first latch 701 is compared with that of the second latch 702. The delay time of the output signal is small, such that the output signal delay time of the entire flip-flop 700 is small, which is less than the signal period of the first clock signal. Therefore, with this arrangement, the delay time of the output signal can be reduced as compared with the scheme shown in FIG.

It should be noted that, in the embodiment of the present application, by setting the preset time to be greater than the sum of the setup time and the hold time of the first clock signal and less than the signal period of the first clock signal, the trigger 700 may be further stabilized. The probability of a state phenomenon. However, in actual implementation, the preset time may also be smaller than the sum of the setup time and the hold time of the first clock signal. Under this setting, the probability of the metastable phenomenon of the flip-flop 700 may also be reduced. There are two reasons for this:

1. The value of the time window (sum of settling time and hold time) of the first clock signal and the time window of the second clock signal (sum of settling time and hold time) is usually small. In the case that the preset time is smaller than the time window of the first clock signal, if the time at which the data signal is level-inverted is just in the time window of the first clock signal, the time may not be in the time window of the second clock signal. That is, when the meta-stabilization phenomenon occurs in the second latch 702 employing the first clock signal, the first latch 701 employing the second clock signal may not have a metastable state. That is to say, in the case that the preset time is smaller than the time window of the first clock signal, the trigger 700 provided by the embodiment of the present application also reduces the probability of the metastable phenomenon of the trigger.

Second, the occurrence of the metastable phenomenon is a probability event. If the time at which the data signal is level-inverted is within the time window of the first clock signal, the second latch 702 may have a metastable state, but Metastable phenomena do not necessarily occur. Similarly, if the time at which the data signal is level-inverted is within the time window of the second clock signal, the first latch 701 may have a metastable state, but metastable state does not necessarily occur. In the case that the preset time is smaller than the time window of the first clock signal, even if the time at which the data signal is level-inverted is within the time window of the first clock signal and within the time window of the second clock signal, the first latch The probability that the metastable phenomenon occurs simultaneously with the second latch 702 and the second latch 702 is also less than the probability that a metastable phenomenon occurs when only the first latch 701 or the second latch 702 is set in the flip-flop. That is, since the first latch 701 and the second latch 702 that can switch the selection are provided in the flip-flop 700 provided by the embodiment of the present application, the preset time is smaller than the time window of the first clock signal. The probability of a metastable state of the flip-flop 700 is also reduced.

As previously described, the detection unit 704 is configured to detect whether the first latch 701 or the second latch 702 is in a metastable state. Specifically, when the detecting unit 704 detects whether the first latch 701 or the second latch 702 is in metastability, there are two specific implementations. The following two implementations are introduced separately.

First implementation

In the first implementation, when detecting whether the first latch 701 or the second latch 702 is in metastability, the detecting unit 704 can be implemented as follows: the detecting unit 702 detects the first latch 701 or Whether the detected node in the second latch 702 is in metastability.

The detection node may be any one of the first latches 701 or any of the second latches 702. If the detecting node is a node in the first latch 701, the detecting unit 704 is configured to detect whether the first latch 701 is in metastable state; if the detecting node is a node in the second latch 702, the detecting unit 704 is used to detect whether the second latch 702 is in metastable state.

That is, in the first implementation, the detecting unit 704 detects whether one of the first latch 701 and the second latch 702 is in a metastable state. The control signal also only indicates if a particular latch is in a metastable state.

In the first implementation, when the switching unit 705 selects to output the output signal of the first latch 701 or the output signal of the second latch 702, the switching unit 705 may select: the currently detected latch is in a metastable state. The output signal of the other latch is selected to be output; the output signal of the currently detected latch is selected to be output when the currently detected latch is not metastable.

Specifically, when the switching unit 705 selects the output signal of the first latch 701 or the output signal of the second latch 702 according to the control signal, the switching unit 705 can be specifically implemented as follows:

1. If the detecting unit 704 is configured to detect whether the first latch 701 is meta-stable, the switching unit 705 selects and outputs the second latch 702 when the detecting unit 704 detects that the first latch 701 is meta-stable. The output signal; the switching unit 705 selects and outputs the output signal of the first latch 701 when the detecting unit 704 detects that the first latch 701 is not in the metastable state.

2. If the detecting unit 704 is configured to detect whether the second latch 702 is metastable, the switching unit 705 selects and outputs the first latch 701 when the detecting unit 704 detects that the second latch 702 is metastable. The output signal; the switching unit 705 selects to output the output signal of the second latch 702 when the detecting unit 704 detects that the second latch 702 is not in metastability.

That is, any one of the first latch 701 and the second latch 702 can be used as a master latch and the other latch as a secondary latch. When the master latch is in metastability, the switching unit 705 temporarily selects the output signal of the secondary latch; once the master latch returns to steady state, the switching unit 705 selects the output signal of the master latch for output.

Specifically, in the first implementation, the detecting unit 704 may include a first inverter, a second inverter, and a first exclusive OR gate circuit. among them,

a first XOR gate circuit coupled to the first inverter and the second inverter for performing an exclusive OR operation on an output signal of the first inverter and an output signal of the second inverter, and The result of the operation is output to the switching unit 705 as a control signal.

As previously mentioned, the detection node can be any of the first latches 701 or any of the second latches 702. The detection node is in metastable state, that is, the latch representing the detection node is in a metastable state.

Illustratively, when the detecting node is a node in the first latch 701, the structure of the flip-flop 700 can be as shown in FIG.

In the flip-flop 700 shown in FIG. 8, the detecting unit 704 works as follows:

When the detection node is in metastability, the detection node will be in an intermediate level state between logic 0 and logic 1. Since the first threshold of the first inverter is greater than the second threshold of the second inverter, when the level state of the detecting node changes to a value range smaller than the first threshold and greater than the second threshold, the first inverter The output is high, the second inverter outputs a low level, and the first XOR gate outputs a high level.

When the detection node is not in metastability, the detection node is stable at a high level or a low level. If the detecting node is stable at a high level, the first inverter and the second inverter both output a low level, and the first XOR gate circuit outputs a low level; if the detecting node is stable at a low level, the first Both the inverter and the second inverter output a high level, and the first XOR gate outputs a low level.

Through the analysis of the above working principle, it can be known that when the detecting node is in metastable state, the first XOR gate circuit outputs a high level; when the detecting node is not in the metastable state, the first XOR gate circuit outputs a low level. Therefore, the level state of the control signal outputted by the detecting unit 704 can indicate whether the first latch 701 is in a metastable state, so that the switching unit 705 can selectively output under the control of the control signal output by the detecting unit 704. The output signal of the first latch 701 or the output signal of the second latch 702. For example, if the control signal outputted by the detecting unit 704 to the switching unit 705 is at a high level, the switching unit 705 may determine that the first latch 701 is in a metastable state, and at this time, the switching unit may select to output the second latch 702. Outputting a signal to avoid transferring the metastable state to the third latch 706 of the next stage; if the control signal outputted by the detecting unit 704 to the switching unit 705 is a low level, the switching unit 705 may determine the first latch 701 Not in the metastable state, the switching unit 705 can select to output the output signal of the first latch 701.

It should be noted that the above description of the structure of the detecting unit 704 is merely an example. In actual implementation, the detecting unit 704 is not limited to the above structure. For example, the first inverter and the second inverter can also be implemented by two voltage comparators having different threshold values. For another example, in the detecting unit 704, the first XOR gate circuit can also be implemented by the same OR gate circuit. When implemented by the same OR gate circuit, the switching unit 705 determines whether to output the output signal of the first latch 701 or the output signal of the second latch 702 according to the control signal outputted by the detecting unit 704, and adopts an exclusive OR gate circuit. The judgment logic at the time of implementation is reversed, and the specific implementation manner will not be described here.

In the first implementation, when the detecting node is a node in the first latch 701, the first latch 701 may have two structural components.

The first

The first latch 701 may include a first clocked inverter, a second clocked inverter, and a third inverter. Wherein, the input end of the first clocked inverter inputs a data signal, and the output end of the first clocked inverter is connected as a detecting node to the detecting unit 704, and is connected to the input end of the third inverter; The signal outputted from the output of the phase comparator serves as the output signal of the first latch 701; the input of the second clocked inverter is connected to the output of the third inverter, and the output of the second clocked inverter Connected to the output of the first clocked inverter. Furthermore, the first clocked inverter and the second clocked inverter are alternately turned on under the second clock signal.

When the first latch 701 adopts the first structure, the structure of the flip-flop 700 can be as shown in FIG.

Wherein, the first clocked inverter and the second clocked inverter are alternately turned on, and can be set by: the first clocked inverter triggers conduction on the rising edge of the second clock signal, and the second clock is controlled The inverter triggers the conduction on the falling edge of the second clock signal; or the first clocked inverter triggers the conduction on the falling edge of the second clock signal, and the second clocked inverter rises in the second clock signal The edge is turned on.

When the first latch 701 adopts the above structure, if the first latch 701 is in metastable state, the switching unit 705 selects and outputs the output signal of the second latch 702. When the decision time of the first latch 701 ends, the first latch 701 eventually randomly stabilizes at logic 0 or logic 1, and at this time, the detecting unit 704 detects that the first latch 701 is not in metastable state. Then, the switching unit 705 selects and outputs the output signal of the first latch 701 according to the control signal output by the detecting unit 704.

That is, the second latch 702 outputs a signal to the third latch 706 instead of the first latch 701 when the first latch 701 is in the metastable state, when the first latch 701 returns to the steady state. Then the second latch 702 does not function.

Second

The first latch 701 includes a first clocked inverter, a second clocked inverter, and a third inverter; wherein the input end of the first clocked inverter inputs a data signal, and the first clocked reverse The output end of the phase detector is connected as a detecting node to the detecting unit 704 and is connected to the input end of the third inverter; the signal outputted from the output end of the third inverter is used as an output signal of the first latch 701; The input end of the clocked inverter is connected as the feedback end of the first latch 701 to the output of the switching unit 705, and the output of the second clocked inverter is connected to the output of the first clocked inverter. Furthermore, the first clocked inverter and the second clocked inverter are alternately turned on under the second clock signal.

When the first latch 701 adopts the second structure, the structure of the flip-flop 700 can be as shown in FIG.

When the first latch 701 adopts the configuration shown in FIG. 10, if the first latch 701 is in metastable state, the switching unit 705 selects and outputs the output signal of the second latch 702. At this time, the switching unit 705 outputs a stable signal. Since the output end of the switching unit 705 is connected to the feedback end of the first latch 701 (ie, the input end of the second clocked inverter), and the output end of the second clocked inverter is connected to the detecting node, The second clocked inverter can feed back the stable level of the output of the switching unit 705 to the detecting node, thereby eliminating the metastability of the detecting node. At this time, the detecting unit 704 detects that the detecting node is not in metastability (ie, the first latch 701 is not in metastable state), so that the control switching unit 705 selects and outputs the output signal of the first latch 701.

When the first latch 701 adopts the second structure, since the feedback terminal can feed back the stable level to the detecting node, the metastable state of the detecting node is detected compared with the scheme in which the first latch 701 adopts the first structure. Can be eliminated in a shorter time, the switching unit 705 can select to output the output signal of the first latch 701 after the metastable cancellation.

The above is an introduction to the structure of the first latch 701 in the case where the detecting unit 704 detects whether the first latch 701 is meta-stable. In addition, in this case, the structure of the second latch 702 can refer to the structure of the first latch 701 in FIG. 9, and details are not described herein again.

In the first implementation, when the detection node is a node in the second latch 702, the second latch 702 may have two structural components.

The first

The second latch 702 includes a third clocked inverter, a fourth clocked inverter, and a fourth inverter. Wherein, the input end of the third clocked inverter inputs a data signal, and the output end of the third clocked inverter is connected as a detecting node to the detecting unit 704, and is connected to the input end of the fourth inverter; The signal outputted from the output of the phase comparator serves as the output signal of the second latch 702; the input of the fourth clocked inverter is connected to the output of the fourth inverter, and the output of the fourth clocked inverter Connected to the output of the third clocked inverter. In addition, the third clocked inverter and the fourth clocked inverter are alternately turned on under the first clock signal.

When the second latch 702 adopts the first structure, the structure of the flip-flop 700 can be as shown in FIG.

Wherein, the third clocked inverter and the fourth clocked inverter are alternately turned on, and can be set as follows: the third clocked inverter triggers conduction on the rising edge of the first clock signal, and the fourth clock control The inverter triggers the conduction on the falling edge of the first clock signal; or the third clocked inverter triggers the conduction on the falling edge of the first clock signal, and the fourth clocked inverter rises in the first clock signal The edge is turned on.

When the second latch 702 adopts the above structure, if the second latch 702 is in metastable state, the switching unit 705 selects and outputs the output signal of the first latch 701. When the decision time of the second latch 702 ends, the second latch 702 will eventually stabilize at logic 0 or logic 1 at random. At this time, the detecting unit 704 detects that the second latch 702 is not in the metastable state. Then, the switching unit 705 selects and outputs the output signal of the second latch 702 according to the control signal output by the detecting unit 704.

That is, the first latch 701 outputs a signal to the third latch 706 instead of the second latch 702 when the second latch 702 is in metastability, when the second latch 702 returns to steady state. Then the first latch 701 does not function.

Second

The second latch 702 includes a third clocked inverter, a fourth clocked inverter, and a fourth inverter. Wherein, the input end of the third clocked inverter inputs a data signal, and the output end of the third clocked inverter is connected as a detecting node to the detecting unit 704, and is connected to the input end of the fourth inverter; The signal outputted from the output of the phase converter is used as the output signal of the second latch 702; the input end of the fourth clocked inverter is connected as the feedback end of the second latch 702 to the output of the switching unit 705, fourth The output of the clocked inverter is connected to the output of the third clocked inverter. In addition, the third clocked inverter and the fourth clocked inverter are alternately turned on under the first clock signal.

When the second latch 702 adopts the second structure, the structure of the flip-flop 700 can be as shown in FIG.

When the first latch 701 adopts the configuration shown in FIG. 12, if the second latch 702 is in metastable state, the switching unit 705 selects and outputs the output signal of the first latch 701. At this time, the switching unit 705 outputs a stable signal. Since the output end of the switching unit 705 is connected to the feedback end of the second latch 702 (ie, the input end of the fourth clocked inverter), and the output end of the fourth clocked inverter is connected to the detecting node, The four-clocked inverter can feed back the stable level of the output of the switching unit 705 to the detecting node, thereby eliminating the metastability of the detecting node. At this time, the detecting unit 704 detects that the detecting node is not in metastability (ie, the second latch 702 is not in metastable state), so that the control switching unit 705 selects and outputs the output signal of the second latch 702.

When the second latch 702 adopts the second structure, since the feedback terminal can feed back the stable level to the detecting node, the metastable state of the detecting node is detected compared with the scheme in which the second latch 702 adopts the first structure. Can be eliminated in a shorter time, the switching unit 705 can select to output the output signal of the second latch 702 after the metastable cancellation.

The above is an introduction to the structure of the second latch 702 in the case where the detecting unit 704 detects whether the second latch 702 is meta-stable. In addition, in this case, the structure of the first latch 701 can refer to the structure of the second latch 702 in FIG. 11 , and details are not described herein again.

The above is an introduction to the first implementation in which the detecting unit 704 detects whether the first latch 701 or the second latch 702 is metastable. The second implementation is described below.

Second implementation

In a second implementation manner, when detecting whether the first latch or the second latch is in a metastable state, the detecting unit may be implemented by: detecting, by the detecting unit, the first detecting node in the first latch Whether it is in metastability and detecting whether the second detection node in the second latch is in metastable state.

That is, the detecting unit 704 detects whether the first latch 701 and the second latch 702 are in a metastable state. The control signal indicates whether the first latch 701 is in a metastable state and whether the second latch 702 is in a metastable state.

With the second implementation, when the switching unit 705 selects the output signal of the first latch 701 or the output signal of the second latch 702 according to the control signal, the switching unit 705 can be specifically implemented as follows: the switching unit 705 is detecting When unit 704 detects that first latch 701 is in metastability, it selects to output an output signal of second latch 702. Thereafter, the switching unit 705 selects and outputs the output signal of the second latch 702 until the detecting unit 704 detects that the second latch 702 is in metastability, and the switching unit 705 selects to output the output signal of the first latch 701. . Thereafter, the switching unit 705 always selects the output signal of the first latch 701 until the detecting unit 704 detects that the first latch 701 is metastable, and the switching unit 705 selects the output signal of the second latch 702. .

That is to say, the switching unit 705 determines only the state of the latch corresponding to the current output signal when the output signal is selected. That is, when the latch corresponding to the current output signal is in a steady state, the switching unit 705 selects to output the current output signal regardless of the state of the other latch; only the latch corresponding to the current output signal is in the sub-state At steady state, the switching unit 705 selects to output the output signal of the other latch.

It is not difficult to see that the second implementation is more than the first implementation, the number of nodes that the detection unit 704 needs to detect is increased, but the switching unit 705 is selectively outputting the output signal of the first latch 701 or the second latch. When the output signal of 702 is reduced, the number of times of switching signals is reduced.

Specifically, in the second implementation manner, the detecting unit 704 may include a first detecting circuit and a second detecting circuit; the first detecting circuit is configured to detect whether the first detecting node is in metastable state, and based on the detection result to the switching unit 705 is configured to send a first control signal, where the second detecting circuit is configured to detect whether the second detecting node is in a metastable state, and send a second control signal to the switching unit 705 according to the detection result; wherein the control signal includes the first control signal and the second control signal.

The first detecting node may be any one of the first latches 701, and the second detecting node may be any one of the second latches 702. The first control signal is used to indicate whether the first latch 701 is in a metastable state, and the second control signal is used to indicate whether the second latch 702 is in a metastable state.

When the detecting unit 704 adopts the above structure, the structure of the flip-flop 700 can be as shown in FIG.

The first detecting circuit may include: a first inverter connected to the first detecting node, configured to output a low level when the voltage of the first detecting node is greater than or equal to the first threshold, and at the first detecting node And outputting a high level when the voltage is lower than the first threshold; the second inverter is connected to the first detecting node, and is configured to output a low level when the voltage of the first detecting node is greater than or equal to the second threshold, and at the first When the voltage of the detecting node is lower than the second threshold, the high level is output, and the second threshold is smaller than the first threshold; the first XOR gate circuit is connected to the first inverter and the second inverter for the first The output signal of the phase converter and the output signal of the second inverter are XORed, and the result of the exclusive OR operation is output as a first control signal to the switching unit.

The second detecting circuit may include: a third inverter connected to the second detecting node, configured to output a low level when the voltage of the second detecting node is greater than or equal to the third threshold, and at the second detecting node Outputting a high level when the voltage is lower than the third threshold; and a fourth inverter connected to the second detecting node, configured to output a low level when the voltage of the second detecting node is greater than or equal to the fourth threshold, and in the second When the voltage of the detecting node is lower than the fourth threshold, the high level is output, and the fourth threshold is smaller than the third threshold; the second exclusive OR circuit is connected with the third inverter and the fourth inverter for the third reverse The output signal of the phase converter and the output signal of the fourth inverter are XORed, and the result of the exclusive OR operation is output as a second control signal to the switching unit.

When the first detecting circuit and the second detecting circuit adopt the above structure, the working principle of the detecting unit 704 is as follows:

If the first detecting node is in a metastable state, when the level state of the first detecting node changes to a value range smaller than the first threshold and greater than the second threshold, the first inverter outputs a high level, and the second inverting The device outputs a low level, and the first XOR gate outputs a high level. When the first detecting node is not in the metastable state, the first detecting node is stable at a high level or a low level, and the first XOR gate circuit outputs a low level.

If the second detecting node is in a metastable state, when the level state of the second detecting node changes to a value range smaller than the third threshold and greater than the fourth threshold, the third inverter outputs a high level, and the fourth inverting The device outputs a low level, and the second XOR gate outputs a high level. When the second detecting node is not in the metastable state, the second detecting node is stable at a high level or a low level, and the second exclusive OR circuit outputs a low level.

Therefore, the first control signal outputted by the detecting unit 704 can be used to indicate whether the first latch 701 is in metastable state, and the second control signal outputted by the detecting unit 704 can indicate whether the second latch 702 is in metastable state. Thereby, the switching unit 705 can selectively output the output signal of the first latch 701 or the output signal of the second latch 702 under the control of the first control signal and the second control signal output by the detecting unit 704.

For example, if the first control signal outputted by the detecting unit 704 to the switching unit 705 is at a high level, the first latch 701 is in a metastable state, and at this time, the switching unit may select to output an output signal of the second latch 702. Avoid transferring the metastable state to the third latch 706 of the next stage; after that, the switching unit always selects and outputs the output signal of the second latch 702 until the second control signal goes high, at this time, The second latch 702 is in a metastable state, and the switching unit selects to output the output signal of the first latch 701.

It should be noted that the above description of the structure of the detecting unit 704 is merely an example. In actual implementation, the detecting unit 704 is not limited to the above structure. For example, the first inverter and the second inverter can also be implemented by two voltage comparators having different threshold values. For another example, the first XOR gate circuit can also be implemented by the same OR gate circuit. When the same OR circuit is used, the switching unit 705 determines the output signal of the first latch 701 or the output signal of the second latch 702, which is opposite to the judgment logic when the XOR gate circuit is implemented. Implementations are not described here.

It should be noted that, in the second implementation manner, the structure of the first latch 701 and the structure of the second latch 702 can refer to related descriptions in the first implementation manner, and details are not described herein again.

In summary, in the flip-flop 700 provided by the embodiment of the present application, since the second clock signal used by the first latch 701 and the first clock signal used by the second latch 702 have a phase difference, then The time at which the data signal input to the flip-flop 700 is level-inverted is normally not in the second clock signal if it is within the time window of the first clock signal (ie, the second latch 702 is metastable). Within the time window (ie, the first latch 701 is not in metastability). Similarly, the time at which the data signal input in the flip-flop 700 is level-inverted is normally not in the first time if it is within the time window of the second clock signal (ie, the first latch 701 is in metastable state). Within the time window of the clock signal (ie, the second latch 702 is not in metastable state). Therefore, the first latch 701 and the second latch 702 are not simultaneously metastable.

In the flip-flop 700, when the detecting unit 704 detects that the first latch 701 is meta-stable, the switching unit 705 can select the output signal of the second latch 702 according to the control signal; the detecting unit 704 detects the first When the two latches 702 are in metastability, the switching unit 705 can select to output an output signal of the first latch 701 according to the control signal. Therefore, with the flip-flop 700 provided by the embodiment of the present application, the signal output to the input end of the third latch 706 can be in a stable state, so that the output signal of the flip-flop 700 is in a stable state, and the trigger 700 is reduced. The probability of steady state phenomenon, thus avoiding the logic misjudgment of the output signal of the trigger and affecting the normal operation of the system.

In addition, in the embodiment of the present application, the output signal of the flip-flop 700 can be stabilized by the structure inside the flip-flop 700, and the delay of the system output caused by the scheme of eliminating the metastable state by using the flip-flop cascade manner is avoided. , improved system performance. In the multi-system interaction process, if the trigger 700 provided by the embodiment of the present application is used in multiple systems, the output delay of each system can be reduced, thereby improving the performance of multi-system interaction.

Based on the above embodiment, a trigger is also provided in the present application, which can be regarded as a specific example of the trigger 700. Referring to FIG. 14, the flip-flop includes a master latch, a sub-latch L, a delay unit, and a latch H.

The clock signal used by the master latch is a clock signal obtained by delaying the delay unit, and the clock signal used by the slave latch is an undelayed clock signal clk. In the master latch, in addition to two clocked inverters for implementing data latching and an inverter (two clocked inverters and one inverter can form the first of the flip-flops 700) In addition to the latch 701 or the second latch 702), a high threshold inverter, a low threshold inverter, an exclusive OR gate circuit, and a data selector are included. The inputs of the high threshold inverter and the low threshold inverter are both connected to point A.

Wherein, a combination of a high threshold inverter, a low threshold inverter, and an exclusive OR gate circuit can be regarded as one specific example of the detecting unit 704 in the flip flop 700; the data selector can be regarded as the switching unit 705 in the flip flop 700 A specific example of this; the latch H can be considered as a specific example of the third latch 706 in the flip-flop 700.

The trigger shown in Figure 14 works as follows:

When the master latch is metastable, the A node cannot settle to the logic 0 or logic 1 level state, but is at the intermediate level between logic 0 and logic 1. The high threshold inverter determines that point A is low when the intermediate level state of point A is collected, so the high threshold inverter inverts the low level and outputs a high level; the low threshold inverter collects the A When the middle level state of the point is judged, the point A is high, so the low threshold inverter inverts the high level and outputs the low level. The XOR gate circuit outputs a high level after XORing the high level of the high threshold inverter output and the low level of the low threshold inverter output. After receiving the high level of the XOR gate output, the data selector switches the output signal to the sub-latch, that is, outputs the output signal of the sub-latch to the latch H. Since the master latch and the sub-latch use different clock signals, point A is in metastable state, point B is not metastable, therefore, the data selector outputs a signal to latch H (sub latch) The output signal of the device is a stable signal.

In the master latch, the level state of point C is fed back to point A through a clocked inverter. Since point C is in a steady state, the level state of point C is fed back to point A, which causes point A to change from metastable to steady state. At this time, the outputs of the high threshold inverter and the low threshold inverter are identical (that is, both are high level, or both are low level), and the XOR gate circuit outputs a low level. After receiving the low level of the XOR gate output, the data selector switches the output signal to the master latch, that is, outputs the output signal of the master latch to the latch H.

That is, the sub-latch temporarily outputs a signal to the latch H instead of the master latch when the master latch is in metastability, and selects the output master latch after the meta-stable of the master latch is removed. Output signal of the device.

It should be noted that the trigger shown in FIG. 14 can be regarded as a specific example of the trigger 700 shown in FIG. 7. The implementation manner not described in detail in the trigger shown in FIG. 14 can be seen in the trigger shown in FIG. A related description in the device 700.

In summary, the embodiment of the present application provides a trigger. By using the trigger provided by the embodiment of the present application, the probability of a metastable phenomenon of the trigger can be reduced, and the output signal of the trigger can be prevented from being logically misjudged and affecting the normal operation of the system.

It should be noted that in the embodiment of the present application, the switching unit, the detecting unit, the delay unit, and the latch are presented in a modular manner, which is a functional division manner, but in actual products, these are Two or more of the modules may be integrated into one module, and the protection scope of the embodiment of the present application should not be limited by the division manner.

The flip-flop provided by the embodiment of the invention can be used in an integrated circuit of various devices, in particular, an interaction circuit between high and low frequency modules, such as an interface circuit of a CPU core and a peripheral device. Of course, since the flip-flop provided by the embodiment of the present invention can reduce the probability of occurrence of metastability, it can also be widely applied as a basic device to other integrated circuit solutions.

It will be apparent to those skilled in the art that various modifications and changes can be made in the present application without departing from the spirit and scope of the application. Thus, it is intended that the present invention cover the modifications and variations of the present invention.

Claims

A flip-flop for latching and outputting an input data signal under control of a first clock signal, comprising: a first latch, a second latch, a delay unit, a detecting unit, Switching unit and third latch;

The delay unit is configured to delay and output the second clock signal after delaying the first clock signal by a preset time;

a clock signal input end of the first latch is coupled to the delay unit to receive the second clock signal; the first latch is configured to perform the data signal according to the second clock signal Latch or output;

The second latch is configured to latch or output the data signal according to the first clock signal;

The detecting unit is configured to detect whether the first latch or the second latch is in a metastable state, and send a control signal to the switching unit based on the detection result;

The switching unit is configured to select to output an output signal of the first latch or an output signal of the second latch according to the control signal;

The data input end of the third latch is connected to the output end of the switching unit, and is configured to latch or output the output signal of the switching unit according to the first clock signal.
The flip-flop according to claim 1, wherein said switching unit selectively selects an output signal of said first latch or an output signal of said second latch according to said control signal Specifically used for:

The switching unit selects to output an output signal of the second latch when the detecting unit determines that the first latch is in a metastable state; or

The switching unit selects to output an output signal of the first latch when the detecting unit determines that the second latch is in a metastable state.
The flip-flop according to claim 1 or 2, wherein the preset time is greater than a sum of a setup time and a hold time of the first latch and less than a signal period of the first clock signal.
The flip-flop according to any one of claims 1 to 3, wherein the detecting unit is specifically configured to detect whether the first latch or the second latch is in a metastable state, :

The detecting unit detects whether the detecting node in the first latch or the second latch is in a metastable state.
The trigger of claim 4, wherein the detecting unit comprises:

a first inverter connected to the detecting node, configured to output a low level when a voltage of the detecting node is greater than or equal to a first threshold, and a high output when a voltage of the detecting node is lower than a first threshold Level

a second inverter connected to the detecting node, configured to output a low level when a voltage of the detecting node is greater than or equal to a second threshold, and output high when a voltage of the detecting node is lower than a second threshold Level, the second threshold is less than the first threshold;

a first XOR gate circuit coupled to the first inverter and the second inverter for performing an output signal of the first inverter and an output signal of the second inverter An exclusive OR operation, and outputting the result of the exclusive OR operation as the control signal to the switching unit.
The flip-flop according to claim 4 or 5, wherein the first latch comprises a first clocked inverter, a second clocked inverter, and a third inverter;

The input end of the first clocked inverter inputs the data signal, and the output end of the first clocked inverter is connected to the detecting unit as the detecting node, and is in reverse with the third The input end of the third inverter is outputted as an output signal of the first latch; the input end of the second clocked inverter is opposite to the third inversion The output of the second clocked inverter is connected to the output of the first clocked inverter;

The first clocked inverter and the second clocked inverter are alternately turned on under the second clock signal.
The flip-flop according to claim 4 or 5, wherein the first latch comprises a first clocked inverter, a second clocked inverter, and a third inverter;

The input end of the first clocked inverter inputs the data signal, and the output end of the first clocked inverter is connected to the detecting unit as the detecting node, and is in reverse with the third An input of the third inverter is output as a signal of the first latch; an input of the second clocked inverter is used as the first latch a feedback end of the device is connected to an output end of the switching unit, and an output end of the second clocked inverter is connected to an output end of the first clocked inverter;

The first clocked inverter and the second clocked inverter are alternately turned on under the second clock signal.
The flip-flop according to any one of claims 4 to 7, wherein the second latch comprises a third clocked inverter, a fourth clocked inverter and a fourth inverter;

An input end of the third clocked inverter inputs the data signal, and an output end of the third clocked inverter is connected to the detecting unit as the detecting node, and is connected to the fourth inversion The input of the fourth inverter is connected to the output of the second inverter as an output signal of the second latch; the input of the fourth clocked inverter and the fourth inverting The output of the fourth clocked inverter is connected to the output of the third clocked inverter;

The third clocked inverter and the fourth clocked inverter are alternately turned on under the first clock signal.
The flip-flop according to any one of claims 4 to 7, wherein the second latch comprises a third clocked inverter, a fourth clocked inverter and a fourth inverter;

An input end of the third clocked inverter inputs the data signal, and an output end of the third clocked inverter is connected to the detecting unit as the detecting node, and is connected to the fourth inversion An input of the fourth inverter is output as a signal of the second latch; an input of the fourth clocked inverter serves as the second latch a feedback end of the device is connected to an output end of the switching unit, and an output end of the fourth clocked inverter is connected to an output end of the third clocked inverter;

The third clocked inverter and the fourth clocked inverter are alternately turned on under the first clock signal.
The flip-flop according to any one of claims 1 to 3, wherein the detecting unit is specifically configured to detect whether the first latch or the second latch is in a metastable state, :

The detecting unit detects whether the first detecting node in the first latch is metastable, and detects whether the second detecting node in the second latch is in metastable state.
The flip-flop according to claim 10, wherein said detecting unit comprises a first detecting circuit and a second detecting circuit; said first detecting circuit is configured to detect whether said first detecting node is in metastable state, And sending a first control signal to the switching unit based on the detection result; the second detecting circuit is configured to detect whether the second detecting node is in a metastable state, and send a second control signal to the switching unit based on the detection result. ;

The control signal includes the first control signal and the second control signal.
The flip-flop according to claim 11, wherein said first detecting circuit comprises:

a first inverter connected to the first detecting node, configured to output a low level when a voltage of the first detecting node is greater than or equal to a first threshold, and a voltage lower than a voltage at the first detecting node Outputting a high level at the first threshold;

a second inverter connected to the first detecting node, configured to output a low level when a voltage of the first detecting node is greater than or equal to a second threshold, and a voltage lower than a voltage at the first detecting node a second threshold is outputting a high level, and the second threshold is less than the first threshold;

a first XOR gate circuit coupled to the first inverter and the second inverter for performing an output signal of the first inverter and an output signal of the second inverter XOR operation, and outputting the result of the exclusive OR operation as the first control signal to the switching unit;

The second detection circuit includes:

a third inverter connected to the second detecting node, configured to output a low level when a voltage of the second detecting node is greater than or equal to a third threshold, and a voltage lower than a voltage of the second detecting node The third threshold outputs a high level;

a fourth inverter connected to the second detecting node, configured to output a low level when a voltage of the second detecting node is greater than or equal to a fourth threshold, and a voltage lower than a voltage of the second detecting node a fourth threshold is outputting a high level, and the fourth threshold is less than the third threshold;

a second exclusive OR gate circuit coupled to the third inverter and the fourth inverter for performing an output signal of the third inverter and an output signal of the fourth inverter An exclusive OR operation, and outputting the result of the exclusive OR operation as the second control signal to the switching unit.
An integrated circuit, comprising the flip-flop according to any one of claims 1 to 12.