CN101431320A - High-stability D trigger structure - Google Patents
High-stability D trigger structure Download PDFInfo
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- CN101431320A CN101431320A CNA2007100479961A CN200710047996A CN101431320A CN 101431320 A CN101431320 A CN 101431320A CN A2007100479961 A CNA2007100479961 A CN A2007100479961A CN 200710047996 A CN200710047996 A CN 200710047996A CN 101431320 A CN101431320 A CN 101431320A
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Abstract
The invention provides the structure of a high-stability D trigger. The D trigger comprises two trigger units which are connected in series with each other and have the same structure; and each trigger unit comprises a transmission gate, a feedback transmission circuit and a phase inverter. Furthermore, the D trigger comprises a level bias circuit connected in parallel with the feedback transmission circuit; and the level bias circuit consists of two NMOS transistors or two PMOS transistors connected in series and has the advantages of simple structure and high universality. By the level bias circuit, metastable levels of the D trigger can be reduced or raised, thereby causing the output potential of the trigger unit of the D trigger to rapidly move to the logic high potential or the logic low potential, and eliminating the metastable state of the D trigger. Therefore, the occurrence probability of the metastable state of the D trigger is greatly reduced, and the stability of the D trigger is improved.
Description
Technical field
The present invention relates to the d type flip flop design field, relate in particular to the high-stability D trigger structure that can reduce the metastable state probability.
Background technology
For digital circuit, the entire circuit system should be operated in stable status.The d type flip flop unit is a sequential logical circuit circuit unit commonly used in the digital circuit.For sequential logical circuit, the stability of circuit unit work directly affects the stable of whole system.Therefore, the design of d type flip flop unit must be satisfied the certain time sequence restriction, so that whole digital timing circuit is operated in stable state.That is to say,, just can guarantee that the output signal of sequential logical circuit is determined under the situation that input signal is determined if the sequential restriction is satisfied in the design of d type flip flop; If d type flip flop does not meet the sequential restriction, then the signal of the inner first order trigger element of d type flip flop may be in metastable state, it is 0 that the final output signal of d type flip flop may postpone, perhaps be 1, such output signal might cause the delay of signal transmission, directly causes data to be made mistakes in the process of transmission or makes digital timing circuit lose efficacy.
The internal structure of typical case's d type flip flop comprises two structure identical triggering unit 7 and 8 as shown in Figure 1, and trigger element 7 is called first order trigger element, and trigger element 8 is called second level trigger element.A, B are trigger element 7 input and output nodes; C, D are respectively the input and output node of trigger element 8,11,21,31,41 connect same clock signal (CK) respectively, 12,22,32,42 connect same inversion clock control signal (CKN) respectively, inversion clock control signal (CKN) is two anti-phase clock signals with clock signal (CK), 3 connect the d type flip flop input signal, and 4 is the output signal of d type flip flop.Wherein trigger element feedback circuit 61 and 62 all is made up of a feedback transmission door and a feedback inverter, and just the clock control signal of two feedback circuits is anti-phase.Feedback circuit 61 or 62 functions that realize also can adopt other form circuit of identical function to substitute, for example as Fig. 2 or feedback transmission circuit feedback transmission circuit shown in Figure 3 by feedback inverter 2, PMOS pipe 1 and NMOS pipe 0 are formed, the grid 20 of pipe 1 connects clock control signal or inversion clock signal, manages 0 grid 21 and connects inversion clock signal or clock signal.During the trigger element that is positioned at according to the feedback transmission circuit, grid 20 and 21 connects corresponding clock signals.Vin is the feedback transmission circuit input end, and Vout is the feedback transmission circuit output end.
There are two important sequential restrictions the d type flip flop unit in the application of sequential logical circuit, as shown in Figure 4: settling time (setup) T
sWith retention time T
h(hold).Be defined as settling time from d type flip flop input signal (D
In) be stabilized to clock signal (Clk) trigger along between minimum interval T
sThe clock signal of also just saying d type flip flop triggers in for the previous period, and the input signal of d type flip flop must be stable.Retention time is defined as from clock signal and triggers along the minimum interval T stablizing to the d type flip flop input signal
hThat is to say that clock signal triggered in the back a period of time on edge, the input signal of d type flip flop is stable.Trigger along within the certain hour of front and back in clock signal, input signal is to keep stable, is referred to as foundation-retention time T during this period of time
S-hIf input signal is at T
S-hVariation took place in the time, and metastable state will inevitably produce.The signal of the inner first order trigger element output of d type flip flop this moment is neither logical one, neither logical zero, but the value of state that mediates after after a while, might go back up to high level, also might be reduced to low level.
All there is the metastable state problem in the d type flip flop of this type.The way that tradition reduces the metastable state occurrence probability has by two d type flip flops of connecting and reduces the metastable state occurrence probability, it is the concrete feature of metastable state that reflects at test that another kind of way is also arranged, design some special logical circuits and reduce the metastable state occurrence probability, this method is more effective than the method for series connection d type flip flop, but this method lacks generality, and makes design go up more complicated.
Summary of the invention
The object of the present invention is to provide a kind of high-stability D trigger structure, can effectively reduce d type flip flop and the metastable state probability occur, improve the stability of d type flip flop work.
To achieve the above object, high-stability D trigger structure provided by the invention, d type flip flop is in series by the trigger element of two same structures, each trigger element includes a transmission gate, an inverter, a feedback transmission circuit, transmission gate and feedback transmission circuit all are connected with clock control signal, it is characterized in that, it also comprises: the level biasing circuit, described level biasing circuit is in parallel with the feedback transmission circuit, is used to reduce or the metastable state output level of the described trigger element that raises.The feedback transmission circuit is made up of a feedback transmission door and a feedback inverter, or the feedback transmission circuit is by a feedback inverter, a PMOS pipe and a NMOS pipe composition.Inverter and feedback inverter all are CMOS type inverters, comprise the load pipe of PMOS and the input pipe of NMOS.
When biasing circuit is used to reduce the metastable state output level of trigger element, described biasing circuit by two mutually the NMOS pipe of series connection form.Two NMOS pipes include three ends: drain terminal, source end and grid, and the drain terminal of one of them NMOS pipe is connected with the output of feedback transmission circuit, and grid links to each other with the input of feedback transmission circuit, and the source end links to each other with another NMOS pipe drain terminal; The source end ground connection of another pipe, grid connects described delay clock signals.The clock signal of the relative transmission gate of this delay clock signals has the delay of Preset Time.
When biasing circuit be used to the to raise metastable state output level of trigger element, described biasing circuit by two mutually series connection PMOS pipe form.Two PMOS pipes include three ends: drain terminal, source end and grid, and the drain terminal of one of them PMOS pipe is connected with the output of feedback transmission circuit, and grid links to each other with the input of feedback transmission circuit, and the source end links to each other with the drain terminal of another PMOS pipe; Another PMOS source termination power, grid connects delay clock signals.The clock signal of the relative transmission gate of this delay clock signals has the delay of Preset Time.
High-stability D trigger structure of the present invention, when metastable state appears in d type flip flop, can reduce or rising d type flip flop metastable state level by level biasing circuit simple in structure and that universality is good, thereby make the output potential of trigger element in the d type flip flop be partial to logic high potential or logic low potential rapidly, eliminate d type flip flop metastable state state this moment, largely reduce the metastable probability that occurs of d type flip flop, thereby can improve the stability of d type flip flop.
Description of drawings
High-stability D trigger structure of the present invention is provided by following examples and accompanying drawing.
Fig. 1 is typical d type flip flop internal structure schematic diagram.
Fig. 2 is the another kind of structural representation of feedback transmission circuit.
Fig. 3 is the another kind of structural representation of feedback transmission circuit.
Fig. 4 is d type flip flop sequential restriction schematic diagram.
Fig. 5 falls level biasing circuit schematic diagram for the trigger element increase.
Fig. 6 is for falling level biasing circuit schematic diagram in parallel with feedback inverter.
Fig. 7 rises level biasing circuit schematic diagram for trigger element increases.
Fig. 8 is for rising level biasing circuit schematic diagram in parallel with feedback inverter.
Embodiment
Below with reference to accompanying drawing high stable d type flip flop of the present invention is described in further detail.
As shown in Figure 1, d type flip flop comprises two structure identical triggering unit 7 and 8, and A, B and C, D are respectively the input and output node of two trigger elements.High-stability D trigger structure provided by the invention can be adjusted the metastable state output level of d type flip flop trigger element 7 or 8.Feedback transmission circuit 61 is identical with feedback circuit 62 structures, and just feedback transmission circuit 61 and 62 clock control signals are anti-phase.Present invention is described to consist of example with feedback transmission door of feedback transmission circuit and feedback inverter.
At first on trigger element 7, to increase the level biasing circuit that is used to reduce trigger element metastable state output level.As shown in Figure 5, falling the level biasing circuit with increase on trigger element 7 is example, and TG1 is a transmission gate, and feedback transmission circuit 61 is made up of feedback transmission door TG2 and feedback inverter 9, and inverter 10 outputs are the B node, and input is the A node.TG1 has two clock signal control ends 11 and 12, and TG2 is the feedback transmission door, and TG2 also has clock signal control end 21 and 22.11 and 21 inputs connect clock signal (CK), 12 and 22 input termination inversion clock signals (CKN).CK and CKN are two anti-phase clock signals.Feedback inverter 9 and inverter 10 all are CMOS inverter type.This CMOS type inverter is to be the load pipe with PMOS, and NMOS is an input pipe.The level biasing circuit 16 that falls that increases is connected with the B point with the A point of trigger element 7 respectively, and is in parallel with feedback transmission circuit 61.It is in parallel with feedback inverter 9 to fall level biasing circuit 16.
Fall level biasing circuit 16 and mainly be made up of two NMOS pipe NM1 and NM2, and NM1 connects mutually with NM2, NM1 and NM2 all have three ends: drain terminal, source end, grid.The source end of NM1 links to each other with the drain terminal of NM2, the source end ground connection of NM2, and the grid of NM1 meets the input B of feedback transmission circuit 61, and the drain terminal of NM1 connects the output of feedback transmission circuit 61, and the grid of NM2 connects delay clock signals 14.The clock signal that the relative transmission gate TG1 of this delay clock signals is connected with TG2 has the delay of Preset Time.The through and off of falling level biasing circuit 16 are limited by delay clock signals.
When this trigger element 7 received external data, clock signal input terminal 11 and 21 was a low level among Fig. 5, and inversion clock signal input part 12 and 22 is a high level, and feedback transmission door TG2 closes.By suitable control, can receive data so that the through and off of falling level biasing circuit 17 that increased all do not influence trigger element to the rising and falling edges of delay clock signals.
When trigger element 7 transmission data, clock signal input terminal 11 and 21 is a high level, and clock signal input terminal 12 and 22 is a low level, feedback transmission door TG2 conducting, and it is in parallel with feedback inverter 9 to fall level biasing circuit 16.If trigger element 7 satisfies the sequential restriction of settling time and retention time, the through and off of falling the level biasing circuit all do not influence transfer of data.Yet when trigger element 7 did not satisfy the sequential restriction of settling time and retention time, metastable state will appear in trigger element 7, falls the level biasing circuit by the delay clock signal conducting.Level biasing circuit 16 and feedback inverter 9 detailed signal in parallel is fallen as seeing also Fig. 6.Because NM1 is in parallel with NMOS input pipe in the feedback inverter 9 with NM2, the input pipe size change that causes feedback inverter 9 can reduce the metastable state level that the B of trigger element 7 is ordered greatly thus.Simultaneously because the amplification of feedback inverter, the A level point can descend, and the B level point can rise, thus make the B level point depart from this moment the metastable state level by a larger margin, thereby can make the output potential of trigger element 7 return to logic high at faster speed.Described delayed clock relative time clock signal 1 has Preset Time to postpone, and this Preset Time postpones and can adjust according to the d type flip flop operating rate, guaranteeing at trigger element when metastable state occurring, but falls the conducting of level biasing circuit.
Be example with the level biasing circuit that on trigger element, increases the trigger element metastable state level that is used to raise again.As shown in Figure 7, be example to rise the level biasing circuit in trigger element 8 increases, TG3 is a transmission gate, and feedback transmission circuit 62 is made up of feedback transmission door TG4 and feedback inverter 17, and inverter 18 input nodes are C, and output node is D.TG3 has two clock signal control ends 31 and 32, TG4 is the feedback transmission door, have two clock signal control ends 41 and 42, in 31 and 41 control termination clock signals (CK) and the trigger element 7 11 and 21 to connect clock signal identical, 32 and 42 connect in inversion clock signal (CKN) and the trigger element 7 12 and 22, and to connect clock signal identical.Feedback inverter 17 and inverter 18 all are CMOS type inverters.C and D are the input and output nodes of trigger element 8, increase to rise level biasing circuit 15 in parallel with feedback transmission circuit 62.Rise level biasing circuit 15 and be made up of two PMOS pipe PM1 and PM2, and PM1 connects mutually with PM2, PM1 and PM2 all have three ends: drain terminal, source end, grid.The PM2 drain terminal is connected with the output D of feedback transmission circuit 62, and the grid of PM2 links to each other with the input D of feedback transmission circuit 62, and the source end of PM2 links to each other with the drain terminal of PM1, the source termination power of PM2, and the grid of PM2 connects delay clock signals 19.The through and off that rise level biasing circuit 15 are limited by delay clock signals.
When this trigger element 8 received data, clock signal input terminal 11,21 was a low level among Fig. 7, and inversion clock signal input part 12,22 is a high level, and feedback transmission door TG4 closes.By the control to the rising and falling edges of delay clock signals, the through and off that rise level biasing circuit 15 all do not influence trigger element and receive data.
When trigger element 8 transmission data, clock signal input terminal 31,41 is a start signal, and clock signal input terminal 32,42 is a shutdown signal, feedback transmission door TG4 conducting, and it is in parallel with feedback inverter 17 to rise the level biasing circuit.If trigger element 8 satisfies the sequential restriction of settling time and retention time, the through and off of falling the level biasing circuit all do not influence transfer of data.Yet when trigger element 8 did not satisfy the sequential restriction of settling time and retention time, metastable state will appear in trigger element 8.Rise the level biasing circuit by the delay clock signal conducting.Rise level biasing circuit 15 and feedback inverter 17 detailed signal in parallel as seeing also Fig. 8.Because PM1 is in parallel with PMOS load pipe in the feedback inverter 17 with PM2, cause the input pipe size of feedback inverter 17 to become big, the metastable state level that the D of the trigger element 8 that can raise is thus ordered.Simultaneously because the amplification of feedback inverter 17, the C level point can rise, and the D level point can descend, thus make the D level point depart from this moment the metastable state level by a larger margin, thereby can make the output potential of trigger element 8 return to logic low at faster speed.Described delay clock signals 19 relative time clock signals have Preset Time to postpone.
The level biasing circuit falls when trigger element 7 adds, when trigger element 8 added rising level biasing circuit simultaneously, delay clock signal 14 and delay clock signal 19 can adopt the relative time clock signal to have the Preset Time inhibit signal can effectively get rid of the metastable state that this moment, d type flip flop occurred.
The structure of high-stability D trigger can only will be fallen the level biasing circuit and will be added on trigger element 7 or the trigger element 8; Or only will rise the level biasing circuit and be added on trigger element 7 or 8; Or trigger element 7 adds and falls the level biasing circuit, and trigger element 8 adds rising level biasing circuit simultaneously; Or trigger element 7 adds rising level biasing circuit, and trigger element 8 adds and falls the level biasing circuit simultaneously; Or trigger element 7 adds rising level biasing circuit simultaneously and falls the level biasing circuit; Or trigger element 8 adds simultaneously and falls level biasing circuit and rise the level biasing circuit, or two trigger elements all add and fall the level biasing circuit; Or two trigger elements all add and rise the level biasing circuit; Or a trigger element adds a plurality of biasing circuits etc., finds out that more than level biasing circuit and trigger element can have multiple combination, more than multiple combination all in protection scope of the present invention.
More than these combinations need it should be noted that can not make rise the level biasing circuit to the rising adjustment of trigger element metastable state level with fall of the decline adjustment of level biasing circuit and offset trigger element metastable state level, the effect of probability occurs otherwise can not play reduction d type flip flop metastable state, thereby can not improve the stability of d type flip flop.
Equally, if the feedback transmission circuit 61 in the d type flip flop trigger element or 62 adopts as Fig. 2 or structure shown in Figure 3 by feedback inverter, PMOS pipe and a NMOS pipe composition describedly fall or rise that the level biasing circuit can be used to reduce equally or the metastable state output level of rising trigger element.
Claims (9)
1, a kind of high-stability D trigger structure, described d type flip flop is in series by the trigger element of two same structures, each trigger element includes a transmission gate, an inverter, a feedback transmission circuit, transmission gate and feedback transmission circuit all are connected with clock control signal, it is characterized in that, it also comprises: the level biasing circuit, described level biasing circuit is in parallel with the feedback transmission circuit, is used to reduce or the metastable state output level of the described trigger element that raises.
2, d type flip flop structure as claimed in claim 1 is characterized in that: described feedback transmission circuit is made up of a feedback transmission door and a feedback inverter.
3, d type flip flop structure as claimed in claim 1 is characterized in that: described feedback transmission circuit is by a feedback inverter, and a PMOS manages and NMOS pipe composition.
4, as claim 2 or 3 described d type flip flop structures, it is characterized in that: described inverter and described feedback inverter all are CMOS type inverters, comprise the load pipe of PMOS and the input pipe of NMOS.
5, d type flip flop structure as claimed in claim 1 is characterized in that: when described biasing circuit is used to reduce described trigger element metastable state level, described biasing circuit by two mutually the NMOS pipe of series connection form.
6, d type flip flop structure as claimed in claim 5, it is characterized in that: described two NMOS pipes include three ends: drain terminal, source end and grid, the drain terminal of one of them NMOS pipe is connected with the output of feedback transmission circuit, grid links to each other with the input of feedback transmission circuit, and the source end links to each other with another NMOS pipe drain terminal; The source end ground connection of another pipe, grid connects delay clock signals.
7, d type flip flop structure as claimed in claim 1 is characterized in that: when described biasing circuit was used to raise trigger element metastable state level, described biasing circuit was made up of two PMOS pipes of connecting mutually.
8, d type flip flop structure as claimed in claim 7, it is characterized in that: described two PMOS pipes include three ends: drain terminal, source end and grid, the drain terminal of one of them PMOS pipe is connected with the output of feedback transmission circuit, grid links to each other with the input of feedback transmission circuit, and the source end links to each other with the drain terminal of another PMOS pipe; Another PMOS source termination power, grid connects delay clock signals.
9, as claim 6 or 8 described d type flip flop structures, it is characterized in that: the clock signal of the relative transmission gate of described delay clock signals has the delay of Preset Time.
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| CN2007100479961A CN101431320B (en) | 2007-11-08 | 2007-11-08 | High-stability D trigger structure |
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| CN2007100479961A CN101431320B (en) | 2007-11-08 | 2007-11-08 | High-stability D trigger structure |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106160731A (en) * | 2015-03-27 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | Drive circuit |
| CN107483304A (en) * | 2016-06-07 | 2017-12-15 | 中芯国际集成电路制造(上海)有限公司 | A kind of bus structures |
| CN107733421A (en) * | 2016-11-18 | 2018-02-23 | 上海兆芯集成电路有限公司 | For the data synchronizing unit for being latched the asynchronous data signal relevant with clock signal |
| CN108540110A (en) * | 2017-03-01 | 2018-09-14 | 中芯国际集成电路制造(上海)有限公司 | D type flip flop |
| WO2019184395A1 (en) * | 2018-03-27 | 2019-10-03 | 华为技术有限公司 | Flip-flop and integrated circuit |
| WO2020113537A1 (en) * | 2018-12-07 | 2020-06-11 | 华为技术有限公司 | D flip-flop capable of preventing metastability |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0516230B1 (en) * | 1991-05-31 | 1999-08-04 | Koninklijke Philips Electronics N.V. | Electronic flip-flop circuit, and integrated circuit comprising the flip-flop circuit |
| US5444404A (en) * | 1994-03-03 | 1995-08-22 | Vlsi Technology, Inc. | Scan flip-flop with power saving feature |
| CN100492907C (en) * | 2005-06-15 | 2009-05-27 | 清华大学 | Master-slave type falling edge D trigger adopting sensitive amplifier structure |
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106160731A (en) * | 2015-03-27 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | Drive circuit |
| CN106160731B (en) * | 2015-03-27 | 2019-06-04 | 中芯国际集成电路制造(上海)有限公司 | Driving circuit |
| CN107483304A (en) * | 2016-06-07 | 2017-12-15 | 中芯国际集成电路制造(上海)有限公司 | A kind of bus structures |
| CN107483304B (en) * | 2016-06-07 | 2020-10-30 | 中芯国际集成电路制造(上海)有限公司 | Bus structure |
| CN107733421A (en) * | 2016-11-18 | 2018-02-23 | 上海兆芯集成电路有限公司 | For the data synchronizing unit for being latched the asynchronous data signal relevant with clock signal |
| CN107733421B (en) * | 2016-11-18 | 2019-02-26 | 上海兆芯集成电路有限公司 | Data synchronizing unit for latching asynchronous data signal related with clock signal |
| CN108540110A (en) * | 2017-03-01 | 2018-09-14 | 中芯国际集成电路制造(上海)有限公司 | D type flip flop |
| WO2019184395A1 (en) * | 2018-03-27 | 2019-10-03 | 华为技术有限公司 | Flip-flop and integrated circuit |
| CN110311659A (en) * | 2018-03-27 | 2019-10-08 | 华为技术有限公司 | A kind of trigger and integrated circuit |
| WO2020113537A1 (en) * | 2018-12-07 | 2020-06-11 | 华为技术有限公司 | D flip-flop capable of preventing metastability |
| CN112997406A (en) * | 2018-12-07 | 2021-06-18 | 华为技术有限公司 | D flip-flop for preventing metastable state |
| CN112997406B (en) * | 2018-12-07 | 2024-03-26 | 华为技术有限公司 | D trigger for preventing metastable state from happening |
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