CN107483304B

CN107483304B - Bus structure

Info

Publication number: CN107483304B
Application number: CN201610398644.XA
Authority: CN
Inventors: 丁艳; 方伟
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2016-06-07
Filing date: 2016-06-07
Publication date: 2020-10-30
Anticipated expiration: 2036-06-07
Also published as: CN107483304A

Abstract

The present invention provides a bus structure comprising: a bus transmission line for transmitting a transmission signal thereon; a signal optimizing section connected in parallel with the bus transmission line for optimizing the transmission signal on the bus transmission line. Due to the addition of the signal optimization component, the bus structure can obviously improve the transmission characteristic of the bus, and can further improve the plasticity of the circuit, namely the circuit can widen the fan-in limit, meet the requirement of the circuit on multiple fan-in, and save part of area.

Description

Bus structure

Technical Field

The invention relates to the field of integrated circuits, in particular to a bus structure.

Background

In an integrated circuit of a nano-scale process, when a signal is transmitted by using a bus, the transmission characteristic of the bus is worse as the fan-in of the bus increases. Meanwhile, as the number of fan-ins increases, it is difficult to improve the problem by adjusting the width-to-length ratio (W/L) of the driving channel, and thus the number of fan-ins also increases.

Taking a 40nm process as an example, it can be known from simulation by using a tri-state bus building circuit that when the fan-in reaches a certain degree, the transmission Time (Transition Time) and the voltage amplitude of the output signal have large deviations.

Therefore, there is a need for a new bus structure to solve the above-mentioned problems.

Disclosure of Invention

In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

In order to overcome the problems existing at present, the invention provides a novel bus structure in one aspect, which comprises:

a bus transmission line for transmitting a transmission signal thereon;

a signal optimizing section connected in parallel with the bus transmission line for optimizing the transmission signal on the bus transmission line.

According to one embodiment of the invention, further comprising at least one signal driving component connected between the bus transmission line and the functional component.

Illustratively, the signal driving means comprises a tri-state gate circuit.

According to one embodiment of the invention, the tri-state gate circuit comprises a signal input terminal, a chip selection signal input terminal and a signal output terminal, wherein the chip selection signal input terminal is used for controlling the functional component to be gated or in a high-resistance state; the signal input is used for receiving an input signal from the functional component; the signal output end is used for outputting transmission signals.

Further, at least one first preset transmission point and at least one second preset transmission point pair are arranged on the bus transmission line, the signal optimization component comprises at least one signal optimization unit corresponding to the first preset transmission point and the second preset transmission point pair, and the signal optimization unit is connected between the first preset transmission point and the second preset transmission point.

According to still another embodiment of the present invention, the signal optimizing unit includes: the rising edge signal optimization unit is used for triggering the rising edge of the transmission signal and optimizing the transmission signal; and/or the falling edge signal optimization unit is used for triggering the falling edge of the transmission signal and performing optimization processing on the transmission signal.

Further, the rising edge signal optimizing unit includes: first time delay structure, first sampling structure and first PMOS pipe and second PMOS pipe, wherein, first time delay structure is connected first sampling structure with between the grid of first PMOS pipe, first sampling structure is connected first time delay structure with between the grid of second PMOS pipe, the drain electrode power connection of first PMOS pipe, the source electrode of first PMOS pipe is connected to the drain electrode of second PMOS pipe, the source electrode of second PMOS pipe connects the load.

Further, the falling edge signal optimization unit includes: the second delay structure is connected between the second sampling structure and the grid electrode of the first NMOS tube, the second sampling structure is connected between the second delay structure and the grid electrode of the second NMOS tube, the drain electrode of the first NMOS tube is grounded, the source electrode of the first NMOS tube is connected to the drain electrode of the second NMOS tube, and the source electrode of the second NMOS tube is connected to a load.

Illustratively, the first delay structure includes an even number of inverters.

Illustratively, the second delay structure includes an even number of inverters.

According to another embodiment of the present invention, the signal optimizing means includes: a plurality of signal optimization units that are sequentially enabled in order.

The bus structure of the invention can obviously improve the transmission characteristic of the bus, and can further improve the plasticity of the circuit, namely the circuit can widen the fan-in limit, meet the requirement of the circuit on multiple fan-in and save partial area.

Drawings

The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

In the drawings:

FIG. 1 is a diagram of a bus transmission line according to the present invention;

FIG. 2 is a block diagram of a bus architecture according to the present invention;

FIG. 3 is a schematic diagram of a tri-state bus architecture according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of the Train Driver structure shown in FIG. 3, according to an embodiment of the present invention;

fig. 5 is a waveform diagram of simulation results according to an embodiment of the present invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.

It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relationship terms such as "under …", "under …", "below", "under …", "above …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.

Fig. 1 shows a bus transmission line diagram according to the invention. As shown in fig. 1, the bus structure of the present invention includes a bus transmission line for transmitting a transmission signal thereon, and a signal optimization unit connected in parallel with the bus transmission line for optimizing the transmission signal on the bus transmission line to obtain an optimized output signal.

Fig. 2 shows a block diagram of a bus structure according to the invention. As shown in fig. 2, the bus structure includes a bus transmission line, a signal driving part, a signal optimizing part, and a functional part. The specific working process is as follows: the signal driving part receives an input signal from a user and controls whether to transmit the signal from the functional part to the bus transmission line, and the signal transmitted to the bus transmission line is optimized by the signal optimizing part to obtain an optimized output signal.

Embodiments of the invention will now be described in detail with reference to specific embodiments and the accompanying drawings.

According to embodiments of the present invention, a novel tri-state bus architecture is provided.

As shown in fig. 3, the tri-state bus structure of the present invention comprises: bus transmission line 100, tri-state gate 200 and signal optimization block 300.

The bus transmission line 100, a group of common signal lines for connecting a plurality of functional units or a plurality of devices, may be divided into a data bus, an address bus, and a control bus for transmitting data, data addresses, and control signals, respectively.

A tri-state gate 200 is used to provide the power drive. Since there are many devices connected to the bus, in order to avoid collision, at most only one output is active at a high level or a low level at any time, and the rest outputs are all in a high impedance state, so that tri-state gate circuit 200 is needed for tri-state control.

Illustratively, the tri-state gate circuit 200 includes a signal input terminal a, a chip select signal input terminal EN, and a signal output terminal L. The chip selection signal input end EN is used for controlling a certain functional component or device to be enabled or in a high-impedance state, and when the chip selection signal input end EN is invalid, the tri-state gate circuit 200 is in the high-impedance state, which is equivalent to an off state, that is, the functional component or device is not connected to the bus; when the chip select signal input EN is active, a functional component or device is enabled, and tri-state gate circuit 200 is in a normal high and low state, and the functional component or device can input a high and low input signal through signal input a. The signal output end L is used for outputting low and high level transmission signals.

The signal optimization unit 300 is connected in parallel with the bus transmission line 100 and is configured to optimize the transmission signal on the bus transmission line 100 to obtain an optimized transmission signal. In practice, the signal optimization component 300 can reduce the delay of Transition Time and the attenuation of the voltage amplitude, thereby improving the transmission characteristics of the bus and widening the limitation of fan-in.

As shown in fig. 3, in an embodiment of the present invention, the signal optimization part 300 may include a signal optimization unit of one or more chain Driver (Train Driver) structures, and each Train Driver structure may be connected in parallel to a preset position of the bus transmission line 100.

The present invention is explained in detail below by taking as an example that the signal optimizing section includes one signal optimizing unit and a plurality of signal optimizing units, respectively.

For example, when the signal optimization component includes one signal optimization unit, a pair of a first preset transmission point and a second preset transmission point is arranged on the bus transmission line, where the first preset transmission point may be a starting end of the bus transmission line, and the second preset transmission point may be a terminating end of the bus transmission line; alternatively, the first and second predetermined transmission points may be any point on the bus transmission line. In other words, this signal optimization unit can be connected in parallel to the entire transmission line or to a part of the entire transmission line, wherein this signal optimization unit is connected between the first predetermined transmission point and the second predetermined transmission point, in whatever way it is connected in parallel. In practice, the positions of the first preset transmission point and the second preset transmission point may be determined according to the size of the load to be driven, and the like.

Illustratively, each signal optimization unit may include: a rising edge signal optimization unit and a falling edge signal optimization unit. For example, each signal optimization unit may also include only a rising edge signal optimization unit or a falling edge signal optimization unit.

Specifically, the rising edge signal optimization unit may be configured to trigger a rising edge of the transmission signal and perform optimization processing on the transmission signal, that is, in this manner, in one transmission signal, the rising edge signal optimization unit performs the transmission signal optimization function only when the rising edge occurs; similarly, the falling edge signal optimization unit may be configured to be triggered at the falling edge of the transmission signal and perform optimization processing on the transmission signal.

In this way, when each signal optimization unit includes the rising edge signal optimization unit and the falling edge signal optimization unit, in the output signal output by the tri-state gate circuit, i.e., the transmission signal, the rising edge signal optimization unit performs the optimization function when the rising edge comes, and the falling edge signal optimization unit performs the optimization function when the falling edge comes, i.e., in the output signal output by the tri-state gate circuit, i.e., the transmission signal optimization function can be performed twice per cycle.

When each signal optimization unit only comprises the rising edge signal optimization unit, in the output signal output by the tri-state gate circuit, namely the transmission signal, the rising edge signal optimization unit executes the optimization function only when the rising edge comes, and the signal optimization unit does not execute the optimization function when the falling edge comes. When each signal optimization unit only comprises the falling edge signal optimization unit, the falling edge signal optimization unit executes an optimization function in an output signal output by the three-state gate circuit, namely a transmission signal, only when a falling edge comes, the signal optimization unit does not execute the optimization function when a rising edge comes, namely, when each signal optimization unit only comprises the rising edge signal optimization unit or the falling edge signal optimization unit, the transmission signal optimization function is executed only once in each period in the output signal output by the three-state gate circuit, namely the transmission signal.

In implementation, as shown in fig. 4, the signal optimization unit may include both a rising edge signal optimization unit 502 and a falling edge signal optimization unit 504.

Further, the rising edge signal optimization unit 502 may include: the delay circuit comprises a first delay structure D1, a first sampling structure D2, a first PMOS tube PMOS1 and a second PMOS tube PMOS2, wherein the first delay structure D1 is connected between the first sampling structure D2 and the grid electrode of the first PMOS tube PMOS1, the first sampling structure D2 is connected between the first delay structure D1 and the grid electrode of the second PMOS tube PMOS2, the drain electrode of the first PMOS tube PMOS1 is connected with a power supply VCC, the source electrode of the first PMOS tube PMOS1 is connected to the drain electrode of the second PMOS tube PMOS2, and the source electrode of the second PMOS tube PMOS2 is loaded.

Further, the falling edge signal optimization unit 504 may include: the second delay structure D3, the second sampling structure D4, the first NMOS1 and the second NMOS2, the second delay structure D3 is connected between the second sampling structure D4 and the gate of the first NMOS1, the second sampling structure D4 is connected between the second delay structure D3 and the gate of the second NMOS2, the drain of the first NMOS1 is connected to the power VCC, i.e., grounded, the source of the first NMOS1 is connected to the drain of the second NMOS2, and the source of the second NMOS2 is connected to the load.

It should be noted that both the first sampling structure D2 and the second sampling structure D4 may include only one inverter, so that fast inversion of signals can be achieved.

For example, in the embodiment of the present invention, the first delay structure D1 may include an even number of inverters, and similarly, the second delay structure D3 may also include an even number of inverters, so that it is ensured that the input signal and the output signal of the first delay structure D1 are in-phase signals. In particular, the number of inverters in the first delay structure D1 and the number of inverters in the second delay structure D3 may be determined according to a specific optimization level.

For another example, when the signal optimization unit includes a plurality of signal optimization units, it includes two signal optimization units as an example: wherein the signal optimization component comprises: the bus transmission line is provided with two pairs of first preset transmission points and second preset transmission points, the first signal optimization unit is connected between the first pair of the first preset transmission points and the second preset transmission points, and the second signal optimization unit is connected between the second pair of the first preset transmission points and the second preset transmission points. It should be noted that the setting rules of each pair of the first preset transmission point and the second preset transmission point are the same, and are not described herein again.

It should be noted that, in the embodiment of the present invention, when the signal optimization unit includes a plurality of signal optimization units, the plurality of signal optimization units may be sequentially enabled in sequence, for example, may be sequentially enabled according to actual positions of the respective signal optimization units connected in parallel on the bus transmission line.

In implementation, in order to improve the performance of the output signal, a signal optimization unit with a TrainDriver structure can be added step by step according to needs. The number of stages to be added and the size or partial structure of the Train Driver structure are determined according to the specific situation of the specific driven load, and each stage of Train Driver is enabled in sequence, so that the performance of an output signal is improved.

A Train Driver structure is added in a bus structure step by step, the transmission characteristic of the bus is improved step by step, and the specific working process is as follows: firstly, adding a first-stage Train Driver, wherein the Train Driver is used as a load at the beginning to cause a certain delay, but as the Train Driver is triggered, a signal is inverted, so that the Train Driver is changed from a load action to a drive action, a transmission signal is driven, and partial performance of an output signal is improved; then, if the driving effect of the first-stage Train Driver structure is limited, a second-stage Train Driver structure needs to be added to drive the transmission signal and improve the performance of the output signal. Thus, the effect of improving the performance of the transmission signal stage by stage can be achieved. The number of inverters in the Train Driver structure can be adjusted according to the size of the driven load, that is, the number of inverters in the chain of inverters in the Train Driver structure is not fixed and can be changed according to the output requirement.

It should be noted that, in the embodiment of the present invention, if the area waste factor is not considered, the above TrainDriver structure can be applied to most circuits, is not limited to a certain process level, and is more effective for the low nanometer process. In addition, the present invention is not limited to SRAM circuits, but also to other circuit signals having such requirements.

It should be noted that although the tri-state bus architecture is described in detail in the embodiments of the present invention, it should be understood by those skilled in the art that the present invention is not intended to be limited to a tri-state bus architecture, but rather that the present invention is applicable to most similar bus architectures or other related bus architectures.

As can be seen from simulation test analysis performed by taking a 40nm process as an example, due to the addition of the Train Driver structure, although a little delay is added before the Train Driver structure is triggered, once the Train Driver structure is triggered, the Train Driver structure is converted into a driving unit, so that the output waveform is obviously improved, and the performance of an output signal is obviously improved. As shown in fig. 5, the original transmission signal has a waveform 1, and after adding the Train Driver structure, the simulation result is changed to a waveform 2, and it is obvious that the transmission signal is improved significantly. From the simulation results, the Train Driver structure can significantly improve the transmission characteristics of the bus, and can widen the limitation of the fan-in.

Therefore, due to the addition of the signal optimization component, the bus structure can obviously improve the transmission characteristic of the bus, and can further improve the plasticity of the circuit, namely the circuit can widen the fan-in limit, thereby meeting the requirement of the circuit on multiple fan-in and saving partial area.

The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. A bus structure, comprising:

a bus transmission line for transmitting a transmission signal thereon;

a signal optimizing unit connected in parallel to the bus transmission line for optimizing the transmission signal on the bus transmission line;

the signal optimization component comprises at least one signal optimization unit, the signal optimization unit comprises a rising edge signal optimization unit and/or a falling edge signal optimization unit, the rising edge signal optimization unit is used for being triggered at the rising edge of the transmission signal and optimizing the transmission signal, and the falling edge signal optimization unit is used for being triggered at the falling edge of the transmission signal and optimizing the transmission signal;

wherein the rising edge signal optimizing unit includes: a first delay structure, a first sampling structure, a first PMOS tube and a second PMOS tube, wherein,

the first time delay structure is connected between the first sampling structure and the grid of the first PMOS tube, the first sampling structure is connected between the first time delay structure and the grid of the second PMOS tube, the drain electrode of the first PMOS tube is connected with the power supply, the source electrode of the first PMOS tube is connected with the drain electrode of the second PMOS tube, and the source electrode of the second PMOS tube is connected with the load.

2. The bus structure of claim 1 further comprising at least one signal driving component connected between the bus transmission line and a functional component.

3. A bus structure as claimed in claim 2, characterized in that the signal driving means comprise a tri-state gate.

4. The bus structure of claim 3 wherein the tri-state gate circuit comprises a signal input, a chip select signal input, and a signal output, wherein,

the chip selection signal input end is used for controlling the functional component to be gated or in a high-impedance state;

the signal input is used for receiving an input signal from the functional component;

the signal output end is used for outputting transmission signals.

5. The bus structure according to claim 1, wherein at least one pair of a first predetermined transmission point and a second predetermined transmission point is disposed on the bus transmission line, and wherein the signal optimization unit is connected between the first predetermined transmission point and the second predetermined transmission point.

6. The bus structure of claim 1, wherein the falling edge signal optimization unit comprises: a second delay structure, a second sampling structure, and a first NMOS transistor and a second NMOS transistor,

the second time delay structure is connected between the second sampling structure and the grid electrode of the first NMOS tube, the second sampling structure is connected between the second time delay structure and the grid electrode of the second NMOS tube, the drain electrode of the first NMOS tube is grounded, the source electrode of the first NMOS tube is connected to the drain electrode of the second NMOS tube, and the source electrode of the second NMOS tube is connected with a load.

7. The bus structure of claim 1 wherein the first delay structure comprises an even number of inverters.

8. The bus structure of claim 6 wherein the second delay structure comprises an even number of inverters.

9. The bus structure of claim 1, wherein the signal optimization component comprises: a plurality of signal optimization units that are sequentially enabled in order.