CN107483304A - A kind of bus structures - Google Patents
A kind of bus structures Download PDFInfo
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- CN107483304A CN107483304A CN201610398644.XA CN201610398644A CN107483304A CN 107483304 A CN107483304 A CN 107483304A CN 201610398644 A CN201610398644 A CN 201610398644A CN 107483304 A CN107483304 A CN 107483304A
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- signal
- bus
- bus structures
- pmos
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
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Abstract
The present invention provides a kind of bus structures, including：Bus transfer circuit, for transmitting transmission signal thereon；Signal optimization component, it is connected in parallel with the bus transfer circuit, for optimizing the transmission signal on the bus transfer circuit.Due to the addition of signal optimization component, the bus structures of the present invention can be obviously improved the transmission characteristic of bus, while and can enough further lifts the plasticity of circuit, i.e. circuit can widen the limitation of fan-in, reach demand of the circuit to more fan-ins, and area can be saved.
Description
Technical field
The present invention relates to integrated circuit fields, in particular to a kind of bus structures.
Background technology
In the integrated circuit of nanoscaled process, when using bus transfer signal, with bus
Fan-in increase, the transmission characteristic of bus is poorer.Simultaneously with the increase of fan-in, it is difficult to
Improve the problem, therefore the number of fan-in by adjusting driving channel width-over-length ratio (W/L)
It is difficult to increase.
By taking 40nm techniques as an example, built using tristate bus line knowable to circuit emulated, work as fan
When entering to reach to a certain degree, the transmission time (Transition Time) and voltage of output signal
Larger deviation can all occur in amplitude.
Therefore, it is necessary to a kind of new bus structures are proposed, to solve existing technical problem.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will be specific real
Apply and be further described in mode part.The Summary of the present invention is not meant to
Attempt to limit the key feature and essential features of technical scheme claimed, less
Mean to attempt the protection domain for determining technical scheme claimed.
In order to overcome the problem of presently, there are, one aspect of the present invention provides a kind of new total knot
Structure, including：
Bus transfer circuit, for transmitting transmission signal thereon；
Signal optimization component, it is connected in parallel with the bus transfer circuit, described for optimizing
The transmission signal on bus transfer circuit.
According to one embodiment of present invention, the bus transfer circuit and work(are connected in addition to
At least one signal driving part between energy part.
Illustratively, the signal driving part includes tri-state gate circuit.
According to one embodiment of present invention, the tri-state gate circuit includes signal input part, piece
Signal input part and signal output part are selected, wherein, the chip selection signal input is used to control institute
Functional part is stated to be strobed or in high-impedance state；The signal input part is used to receive from described
The input signal of functional part；The signal output part is used to export transmission signal.
Further, at least one first Preset Transfer point is provided with the bus transfer circuit
With the second Preset Transfer point pair, the signal optimization component includes and the first Preset Transfer point
Unit is optimized to corresponding at least one signal with the second Preset Transfer point, wherein the signal
Optimization unit is connected between the first Preset Transfer point and the second Preset Transfer point.
According to still another embodiment of the invention, the signal optimization unit includes：Rising edge signal
Optimize unit, be triggered for the rising edge in transmission signal, and transmission signal is optimized
Processing；And/or trailing edge signal optimization unit, it is triggered for the trailing edge in transmission signal,
And processing is optimized to transmission signal.
Further, the rising edge signal optimization unit includes：First time-delay structure, first
Sampling structure and the first PMOS and the second PMOS, wherein, the first delay knot
Structure is connected between first sampling structure and the grid of first PMOS, described
First sampling structure is connected to first time-delay structure and the grid of second PMOS
Between, the drain electrode of first PMOS connects power supply, the source electrode of first PMOS
The drain electrode of second PMOS is connected to, the source electrode of second PMOS connects load.
Further, the trailing edge signal optimization unit includes：Second time-delay structure, second
Sampling structure and the first NMOS tube and the second NMOS tube, wherein, the second delay knot
Structure is connected between second sampling structure and the grid of first NMOS tube, described
Second sampling structure is connected to second time-delay structure and the grid of second NMOS tube
Between, the grounded drain of first NMOS tube, the source electrode of first NMOS tube connects
The drain electrode of second NMOS tube is connected to, the source electrode of second NMOS tube connects load.
Illustratively, first time-delay structure includes even number of inverters.
Illustratively, second time-delay structure includes even number of inverters.
According to another embodiment of the invention, the signal optimization component includes：Multiple signals
Optimize unit, the multiple signal optimization unit enables successively in order.
The bus structures of the present invention can be obviously improved the transmission characteristic of bus, while and can is enough entered
One step lifts the plasticity of circuit, i.e. circuit can widen the limitation of fan-in, reach circuit to more
The demand of fan-in, and area can be saved.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.It is attached
Embodiments of the invention and its description are shown in figure, for explaining the principle of the present invention.
In accompanying drawing：
Fig. 1 is the bus transfer circuit figure according to the present invention；
Fig. 2 is the bus structures block diagram according to the present invention；
Fig. 3 is the schematic diagram of tristate bus line structure according to an embodiment of the invention；
Fig. 4 is showing for Train Driver structures shown in Fig. 3 according to an embodiment of the invention
It is intended to；
Fig. 5 is the oscillogram of simulation result according to an embodiment of the invention.
Embodiment
In the following description, a large amount of concrete details are given to provide to the present invention more
Thoroughly understand.It is it is, however, obvious to a person skilled in the art that of the invention
It can be carried out without one or more of these details.In other examples, in order to keep away
Exempt to obscure with the present invention, be not described for some technical characteristics well known in the art.
It should be appreciated that the present invention can be implemented in different forms, and it is not construed as office
It is limited to embodiments presented herein.On the contrary, providing these embodiments disclosure will be made thoroughly and complete
Entirely, those skilled in the art be will fully convey the scope of the invention to and.In the accompanying drawings,
For clarity, the size and relative size in Ceng He areas may be exaggerated.It is identical attached from beginning to end
Icon note represents identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to "
Or when " being coupled to " other elements or layer, its can directly on other elements or layer, with
It is adjacent, be connected or coupled to other elements or layer, or there may be element or layer between two parties.
On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " being directly connected to "
Or when " being directly coupled to " other elements or layer, then element or layer between two parties is not present.Should
Understand, although can be used term first, second, third, etc. describe various elements, part,
Area, floor and/or part, these elements, part, area, floor and/or part should not be by these
Term limits.These terms be used merely to distinguish an element, part, area, floor or part with
Another element, part, area, floor or part.Therefore, do not depart from present invention teach that under,
First element discussed below, part, area, floor or part be represented by the second element, part,
Area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... it
Under ", " ... on ", " above " etc., herein can for convenience description and by use from
And an element shown in figure or feature and other elements or the relation of feature are described.Should be bright
In vain, in addition to the orientation shown in figure, spatial relationship term be intended to also including the use of and operation
In device different orientation.For example, if the device upset in accompanying drawing, then, is described as
" below other elements " or " under it " or " under it " element or feature will be orientated
For other elements or feature " on ".Therefore, exemplary term " ... below " and " ...
Under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other
Orientation) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as this hair
Bright limitation.Herein in use, " one " of singulative, "one" and " described/should "
It is also intended to include plural form, unless context is expressly noted that other mode.It is also to be understood that art
Language " composition " and/or " comprising ", when in this specification in use, determine the feature,
Integer, step, operation, the presence of element and/or part, but be not excluded for it is one or more its
Its feature, integer, step, operation, the presence or addition of element, part and/or group.
Herein in use, term "and/or" includes any and all combination of related Listed Items.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description
Suddenly, to explain technical scheme proposed by the present invention.Presently preferred embodiments of the present invention is described in detail
It is as follows, but in addition to these detailed descriptions, the present invention can also have other embodiment.
Fig. 1 shows the bus transfer circuit figure according to the present invention.It is as shown in figure 1, of the invention
Bus structures include bus transfer circuit and signal optimization component, wherein, the bus transfer
Circuit is used to transmit transmission signal thereon, the signal optimization component and the bus transmission line
Road is connected in parallel, for optimizing the transmission signal on the bus transfer circuit, to obtain
Output signal after optimization.
Fig. 2 shows the bus structures block diagram according to the present invention.As shown in Fig. 2 the bus
Structure includes bus transfer circuit, signal driving part, signal optimization component and functional part.
Its specific work process is as follows：Signal driving part receives the input signal from user, and
Control whether the signal from the functional part being transferred to bus transfer circuit, be transferred to described
The signal on bus transfer circuit is defeated after being optimized after the optimization of signal optimization component
Go out signal.
Now, embodiments of the invention are discussed in detail in specific embodiments and the drawings.
According to an embodiment of the invention, there is provided a kind of new tristate bus line structure.
As shown in figure 3, the tristate bus line structure of the present invention includes：Bus transfer circuit 100,
Tri-state gate circuit 200 and signal optimization component 300.
Bus transfer circuit 100, one group for connecting multiple functional parts or multiple devices are public
Signal wire altogether, can be divided into data/address bus, address bus and controlling bus, be respectively intended to pass
Transmission of data, data address and control signal.
Tri-state gate circuit 200, for providing power drive.Due to the equipment that is connected in bus very
More, to avoid conflicting, at most only an output is high level or low level at any time
Significant level, remaining output are entirely high-impedance state, are entered so needing to use tri-state gate circuit 200
Row tri-state control.
Illustratively, the tri-state gate circuit 200 includes signal input part A, chip selection signal inputs
Hold EN and signal output part L.Wherein, chip selection signal input EN is used to control some work(
Can part or device be strobed or in high-impedance state, when chip selection signal input EN is invalid,
Tri-state gate circuit 200 is in high-impedance state, equivalent to off-state, the i.e. functional part or device
It is not connected in bus；When chip selection signal input EN is effective, some functional part or dress
Put and be strobed, tri-state gate circuit 200 is in normal high and low level state, the functional part
Or device can input the input signal of high and low level by signal input part A.Signal is defeated
Go out to hold L to be used to export low, high level transmission signal.
Signal optimization component 300 is in parallel with bus transfer circuit 100, for optimizing bus transfer
Transmission signal on circuit 100, with the transmission signal after being optimized.When implementing, signal
Optimization component 300 can cause Transition Time delay to reduce, and cause voltage amplitude
The decay of value weakens, and so as to improve the transmission characteristic of bus, while can widen the limitation of fan-in.
As shown in figure 3, in an embodiment of the present invention, signal optimization component 300 can include
The signal optimization unit of one or more chain driver (Train Driver) structures, each Train
Driver structures can be connected in parallel to the predeterminated position of bus transfer circuit 100.
A signal optimization unit is included with signal optimization component individually below and multiple signals are excellent
The present invention is elaborated exemplified by change unit.
For example, when signal optimization component includes a signal optimization unit, bus transfer circuit
On be provided with a pair of first Preset Transfer points and the second Preset Transfer point, wherein, first default passes
Defeated point can be the initiating terminal of bus transfer circuit, and the second Preset Transfer point can be bus transfer
The clearing end of circuit；Or first and second Preset Transfer point can be on bus transfer circuit
Any point.In other words, this signal optimization unit can be in parallel with whole transmission line road, or
Person and the part lines in parallel on whole transmission line road, wherein, it is no matter in parallel in which way, this
Individual signal optimization unit is all connected between the first Preset Transfer point and the second Preset Transfer point.
During implementation, size for the load that can be driven as needed etc. determines the first Preset Transfer point and the
The position of 2 Preset Transfer points.
Illustratively, each signal optimization unit may each comprise：Rising edge signal optimize unit and
Trailing edge signal optimizes unit.Illustratively, each signal optimization unit can also only include rising
Optimize unit or trailing edge signal optimization unit along signal.
Specifically, rising edge signal optimization unit can be used for being touched in the rising edge of transmission signal
Hair, and processing is optimized to transmission signal, that is, in this manner, in a transmission
In signal, only when rising edge occurs, rising edge signal optimization unit just performs transmission signal
Optimize function；Similarly, trailing edge signal optimization unit can be used for the trailing edge in transmission signal
It is triggered, and processing is optimized to transmission signal.
So, when each signal optimization unit includes rising edge signal optimization unit and trailing edge
Signal optimize unit when, tri-state gate circuit output output signal, i.e., in transmission signal,
When rising edge arrives, rising edge signal optimization unit performs optimization function, when trailing edge arrives,
Trailing edge signal optimization unit performs optimization function, that is, in the output of tri-state gate circuit output
In signal, i.e. transmission signal, each cycle can perform the function of transmission signal optimization twice.
When each signal optimization unit only includes rising edge signal optimization unit, in triple gate
In the output signal of circuit output, i.e. transmission signal, only when rising edge arrives, rising edge
Signal optimization unit performs optimization function, and when trailing edge arrives, signal optimization unit is not held
Row optimization function.When each signal optimization unit only includes trailing edge signal optimization unit,
Tri-state gate circuit output output signal, i.e., in transmission signal, only when trailing edge arrives,
Trailing edge signal optimization unit performs optimization function, when rising edge arrives, signal optimization unit
Optimization function is not performed, that is, when each signal optimization unit is excellent only including rising edge signal
Change unit or trailing edge signal optimization unit when, tri-state gate circuit output output signal, i.e.,
In transmission signal, each cycle is only performed once transmission signal optimization function.
When implementing, optimize as shown in figure 4, signal optimization unit can include rising edge signal
Both unit 502 and trailing edge signal optimization unit 504.
Further, rising edge signal optimization unit 502 can include：First time-delay structure
D1, the first sampling structure D2 and the first PMOS PMOS1 and the second PMOS
PMOS2, wherein, the first time-delay structure D1 is connected to the first sampling structure D2 and first
Between PMOS PMOS1 grid, the first sampling structure D2 is connected to the first delay knot
Between structure D1 and the second PMOS PMOS2 grid, the first PMOS PMOS1
Drain electrode meet power supply VCC, the first PMOS PMOS1 source electrode is connected to the 2nd PMOS
Pipe PMOS2 drain electrode, the second PMOS PMOS2 source load.
Further, trailing edge signal optimization unit 504 can include：Second time-delay structure
D3, the second sampling structure D4 and the first NMOS tube NMOS1 and the second NMOS tube
NMOS2, the second time-delay structure D3 is connected to the second sampling structure D4 and the first NMOS
Between pipe NMOS1 grid, the second sampling structure D4 is connected to the second time-delay structure D3
And second NMOS tube NMOS2 grid between, the first NMOS tube NMOS1 leakage
Pole meets power supply VCC, namely ground connection, and the first NMOS tube NMOS1 source electrode is connected to the
Two NMOS tube NMOS2 drain electrode, the second NMOS tube NMOS2 source electrode connect load.
It should be noted that the first sampling structure D2 and the second sampling structure D4 can be only
Only include a phase inverter, in this manner it is achieved that the quick upset of signal.
Illustratively, in embodiments of the present invention, the first time-delay structure D1 can include even number
Phase inverter, similarly, the second time-delay structure D3 can also include even number of inverters, so,
It can ensure that the first time-delay structure D1 input signal and output signal are in-phase signal.Specifically
Ground, it is anti-in the number and the second time-delay structure D3 of the phase inverter in the first time-delay structure D1
The number of phase device can be determined according to specific optimization rank.
For another example when signal optimization component includes multiple signals optimization unit, include two with it
Exemplified by individual signal optimization unit：Wherein, signal optimization component includes：First signal optimizes unit
Optimize unit with secondary signal, be provided with bus transfer circuit two pair of first Preset Transfer point and
Second Preset Transfer point, the first signal optimization unit be connected to first pair of first Preset Transfer point and
Between second Preset Transfer point, and secondary signal optimization unit is connected to second pair first and preset
Between transfer point and the second Preset Transfer point.It is it should be noted that each to the first Preset Transfer point
With the setting rule all same of the second Preset Transfer point, will not be repeated here.
It should be noted that in an embodiment of the present invention, signal optimization component includes multiple letters
During number optimization unit, multiple signals optimization units can enable successively in order, for example, can be with
The physical location being connected in parallel on according to each signal optimization unit on bus transfer circuit enables successively.
, can be as needed in order to reach the purpose for the performance for improving output signal when implementing
The signal optimization unit of Train Driver structures is added step by step.Wherein, the series added with
And the size or part-structure of Train Driver structures, it is required to basis and is specifically driven
The concrete condition of load determine that every grade of Train Driver is enabled successively, Jin Ergai
The performance of kind output signal.
Add Train Driver structures step by step in bus structures, improve the transmission of bus step by step
Characteristic, the specific course of work are as follows：First, first order Train Driver are added, are started
When, Train Driver can cause a certain degree of delay by as load, but with Train
Driver is triggered, and signal will be overturn, and Train Driver is changed into from load effect
Driving effect, so as to drive transmission signal, improve the partial properties of output signal；Then, such as
The driving effect of fruit first order Train Driver structures is limited, then needs to add the second level again
Train Driver structures, similarly drive transmission signal, and improve the performance of output signal.This
Sample, the effect for the performance for improving transmission signal step by step one by one can be reached.Wherein, Train
The number of phase inverter in Driver structures, it can be adjusted according to the size of institute's driving load,
That is, the number of phase inverter is not in chain of inverters in Train Driver structures in this kind of structure
It is changeless, but change can be required according to output.
It should be noted that in embodiments of the present invention, discounting for the factor for wasting area,
Above-mentioned Train Driver structures go in most of circuits, are not limited to a certain technique
Level, it is more efficient for low nanometer technology.In addition, the present invention is applicable not only to SRAM
Circuit, being equally applicable to other has the circuit signal of this demand, is not limited thereto.
Although still need to it is noted that illustrating tristate bus line knot in embodiments of the invention
Structure, it is understood by one skilled in the art that being not intended to limit the invention to tristate bus line knot
Structure, but the present invention is applied to most of similar bus structures or other associated bus lines knots
Structure.
Carry out emulation testing analysis by taking 40nm process as an example to understand, total knot of the invention
Structure, due to the addition of Train Driver structures, although being triggered it in Train Driver structures
Before, fraction of delay can be increased, but be once triggered, Train Driver structures will turn
It is changed into driver element so that output waveform can be obviously improved, so that the performance of output signal
It is obviously improved.As shown in figure 5, the waveform of script transmission signal is 1, in addition Train Driver
After structure, simulation result is changed into waveform 2, it is clear that transmission signal is obviously improved.Pass through
Simulation result understands that Train Driver structures can be obviously improved the transmission characteristic of bus, together
When can widen the limitation of fan-in.
It follows that due to the addition of signal optimization component, bus structures of the invention can be with bright
The aobvious transmission characteristic for improving bus, while and can enough further lifts the plasticity of circuit, i.e., it is electric
Road can widen the limitation of fan-in, reach demand of the circuit to more fan-ins, and can save portion
Facet is accumulated.
The present invention is illustrated by above-described embodiment, but it is to be understood that, it is above-mentioned
The purpose that embodiment is only intended to illustrate and illustrated, and be not intended to limit the invention to described
Scope of embodiments in.In addition it will be appreciated by persons skilled in the art that not office of the invention
It is limited to above-described embodiment, more kinds of modifications can also be made according to the teachings of the present invention and repaiied
Change, these variants and modifications are all fallen within scope of the present invention.The present invention's
Protection domain is defined by the appended claims and its equivalent scope.
Claims (11)
- A kind of 1. bus structures, it is characterised in that including：Bus transfer circuit, for transmitting transmission signal thereon；Signal optimization component, it is connected in parallel with the bus transfer circuit, described for optimizing The transmission signal on bus transfer circuit.
- 2. bus structures as claimed in claim 1, it is characterised in that also include being connected to At least one signal driving part between the bus transfer circuit and functional part.
- 3. bus structures as claimed in claim 2, it is characterised in that the signal driving Part includes tri-state gate circuit.
- 4. bus structures as claimed in claim 3, it is characterised in that the triple gate electricity Road includes signal input part, chip selection signal input and signal output part, wherein,The chip selection signal input is used to control the functional part to be strobed or in high resistant State；The signal input part is used to receive the input signal from the functional part；The signal output part is used to export transmission signal.
- 5. bus structures as claimed in claim 1, it is characterised in that the bus transfer At least one first Preset Transfer point and the second Preset Transfer point pair, the letter are provided with circuit Number optimization component is included with the first Preset Transfer point and the second Preset Transfer point to corresponding At least one signal optimization unit, wherein to be connected to described first pre- for signal optimization unit If between transfer point and the second Preset Transfer point.
- 6. bus structures as claimed in claim 5, it is characterised in that the signal optimization Unit includes：Rising edge signal optimizes unit, is triggered for the rising edge in transmission signal, and to passing Defeated signal optimizes processing；And/orTrailing edge signal optimizes unit, is triggered for the trailing edge in transmission signal, and to passing Defeated signal optimizes processing.
- 7. bus structures as claimed in claim 6, it is characterised in that the rising edge letter Number optimization unit include：First time-delay structure, the first sampling structure and the first PMOS and Second PMOS, wherein,First time-delay structure is connected to first sampling structure and the first PMOS Between the grid of pipe, first sampling structure is connected to first time-delay structure and described Between the grid of two PMOSs, the drain electrode of first PMOS connects power supply, and described The source electrode of one PMOS is connected to the drain electrode of second PMOS, the 2nd PMOS The source electrode of pipe connects load.
- 8. bus structures as claimed in claim 6, it is characterised in that the trailing edge letter Number optimization unit include：Second time-delay structure, the second sampling structure and the first NMOS tube and Second NMOS tube, wherein,Second time-delay structure is connected to second sampling structure and the first NMOS Between the grid of pipe, second sampling structure is connected to second time-delay structure and described Between the grid of two NMOS tubes, the grounded drain of first NMOS tube, described first The source electrode of NMOS tube is connected to the drain electrode of second NMOS tube, the 2nd NMOS The source electrode of pipe connects load.
- 9. bus structures as claimed in claim 7, it is characterised in that first delay Structure includes even number of inverters.
- 10. bus structures as claimed in claim 8, it is characterised in that second delay Structure includes even number of inverters.
- 11. bus structures as claimed in claim 1, it is characterised in that the signal optimization Part includes：Multiple signals optimize unit, and the multiple signal optimization unit makes successively in order Energy.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610398644.XA CN107483304B (en) | 2016-06-07 | 2016-06-07 | Bus structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610398644.XA CN107483304B (en) | 2016-06-07 | 2016-06-07 | Bus structure |
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| Publication Number | Publication Date |
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| CN107483304A true CN107483304A (en) | 2017-12-15 |
| CN107483304B CN107483304B (en) | 2020-10-30 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1363890A (en) * | 2001-01-12 | 2002-08-14 | 李大年 | Simultaneous converting sampler for multiple channels |
| CN1503146A (en) * | 2002-11-25 | 2004-06-09 | 杭州士兰微电子股份有限公司 | Method of pins multiplexing based on PCI bus |
| CN101431320A (en) * | 2007-11-08 | 2009-05-13 | 中芯国际集成电路制造(上海)有限公司 | High-stability D trigger structure |
| CN101626334A (en) * | 2009-08-10 | 2010-01-13 | 中兴通讯股份有限公司 | Method and device for controlling communication bus |
| US8531895B2 (en) * | 2011-05-11 | 2013-09-10 | Hynix Semiconductor Inc. | Current control circuit |
-
2016
- 2016-06-07 CN CN201610398644.XA patent/CN107483304B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1363890A (en) * | 2001-01-12 | 2002-08-14 | 李大年 | Simultaneous converting sampler for multiple channels |
| CN1503146A (en) * | 2002-11-25 | 2004-06-09 | 杭州士兰微电子股份有限公司 | Method of pins multiplexing based on PCI bus |
| CN101431320A (en) * | 2007-11-08 | 2009-05-13 | 中芯国际集成电路制造(上海)有限公司 | High-stability D trigger structure |
| CN101626334A (en) * | 2009-08-10 | 2010-01-13 | 中兴通讯股份有限公司 | Method and device for controlling communication bus |
| US8531895B2 (en) * | 2011-05-11 | 2013-09-10 | Hynix Semiconductor Inc. | Current control circuit |
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| Publication number | Publication date |
|---|---|
| CN107483304B (en) | 2020-10-30 |
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