CN112997406B

CN112997406B - D trigger for preventing metastable state from happening

Info

Publication number: CN112997406B
Application number: CN201880099343.4A
Authority: CN
Inventors: 季秉武; 周云明; 李文魁; 赵坦夫; 王云鹏
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2018-12-07
Filing date: 2018-12-07
Publication date: 2024-03-26
Anticipated expiration: 2038-12-07
Also published as: CN112997406A; WO2020113537A1

Abstract

The application discloses prevent D flip-flop of metastable state, including potential control circuit (100), and first inverter (10), first latch unit (20), second inverter (30) and second latch unit (40) that couple gradually, wherein potential control circuit (100) are used for when the level of input (A) and output (B) of first latch unit (20) is the same, control input (A) and output (B) of first latch unit (20) to low level and high level respectively, or control to high level and low level respectively. When the level states of the input end (A) and the output end (B) of the first latch unit (20) are the same, the input end (A) and the output end (B) of the first latch unit (20) can be forcedly pulled to different levels by the potential control circuit (100), so that the same stiff state of the input end (A) and the output end (B) of the first latch unit (20) is broken, and metastable state is avoided.

Description

D trigger for preventing metastable state from happening

Technical Field

The present disclosure relates to the field of digital circuits, and more particularly, to a D flip-flop and a system for preventing metastable states.

Background

The flip-flop is an information storage device having two stable states, and is a most basic logic unit constituting various timing circuits in a circuit, and is also an important unit circuit in a digital logic circuit. There is a wide range of applications in digital systems and computers. The flip-flop has two stable level states, namely a low level 0 and a high level 1.

Metastable state refers to a state in which a flip-flop cannot reach a recognizable state within a prescribed period of time. When a flip-flop enters a metastable state, the output stable level of the flip-flop cannot be obtained, and when the output level can be stable cannot be predicted. During metastable states, the flip-flops will output intermediate levels, or may be in an oscillating state, and such unwanted output levels propagate in cascade along the various flip-flops of the signal path, causing the latter flip-flops to also fail to output the correct level.

D Flip-flops (DFF, data Flip-Flop or Delay Flip-Flop) are one of the most widely used types of Flip-flops. However, the D flip-flop includes a plurality of circuit devices therein, and when the level state of the circuit devices therein is problematic during actual use, metastable states of the D flip-flop are caused, resulting in system confusion. The metastable state occurrence probability is generally reduced in the prior art by beating a plurality of beats. For the situation that the data interaction is more and the response delay requirement is high, the mode for reducing the metastable state occurrence probability can influence the performance of the time sequence circuit, so that the time sequence characteristic of the whole circuit is influenced.

Disclosure of Invention

The application provides a D trigger for preventing metastable state, which eliminates the metastable state, avoids the DFF from being in the metastable state and rapidly enables an output end to output a stable level state.

In a first aspect, embodiments of the present application provide a metastable-prevention D flip-flop, including: a first inverter, a first latch unit, a second inverter, a second latch unit, and a potential control circuit; the input end of the first inverter is connected with the input end of the D trigger, and the output end of the first inverter is connected with the input end of the first latch unit; the output end of the first latch unit is connected with the input end of the second inverter, the output end of the second inverter is connected with the input end of the second latch unit, and the output end of the second latch unit is connected with the output end of the D trigger; the potential control circuit is used for controlling the input end and the output end of the first latch unit to be low level and high level respectively or controlling the input end and the output end of the first latch unit to be high level and low level respectively when the levels of the input end and the output end of the first latch unit are the same.

The potential control circuit of the D trigger is connected with the input end and the output end of the first latch unit, when the level states of the input end and the output end of the first latch unit are the same, the input end and the output end of the first latch unit can be forcedly pulled to different levels through the potential control circuit, for example, the output end of the first latch unit is pulled to be high level, the input end of the first latch unit is pulled to be low level, so that the same stiff state of the input end and the output end of the first latch unit is broken, metastable state is avoided, and when the D trigger is in the metastable state, the metastable state is automatically avoided, and the output end of the D trigger is enabled to output the correct level state.

In a first implementation manner of the first aspect, the potential control circuit includes a pull-up circuit and a pull-down circuit; the input end and the output end of the first latch unit are connected with a first power supply through the pull-up circuit, and are grounded through the pull-down circuit; the pull-up circuit is used for pulling the output end of the first latch unit to be high level when the levels of the input end and the output end of the first latch unit are the same; the pull-down circuit is used for pulling the input end of the first latch unit to be low level when the level of the input end and the level of the output end of the first latch unit are the same.

With reference to the first aspect and any one of the foregoing possible implementation manners, in a second possible implementation manner, the potential control circuit includes a pull-up circuit and a pull-down circuit; the input end and the output end of the first latch unit are connected with a first power supply through the pull-up circuit, and are grounded through the pull-down circuit; the pull-up circuit is used for pulling the output end of the first latch unit to be low level when the levels of the input end and the output end of the first latch unit are the same; and the pull-down circuit is used for pulling the input end of the first latch unit to be high level when the level of the input end and the level of the output end of the first latch unit are the same. The two implementations of the potential control circuit are described above, that is, the potential control circuit includes a pull-up circuit and a pull-down circuit, which can pull the input terminal of the first latch unit to a high level and pull the output terminal to a low level. The input of the first latch unit may be pulled low and the output may be pulled high.

With reference to the first aspect and any one of the foregoing possible implementation manners, in a third possible implementation manner, the pull-up circuit includes: the first PMOS tube, the first NMOS tube and the second NMOS tube; the drain electrode of the first PMOS tube is connected with the output end of the first latch unit, the source electrode of the first PMOS tube is connected with the first power supply, and the grid electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube; the grid electrode of the first PMOS tube is connected with a second power supply; the voltage of the second power supply is lower than that of the first power supply; the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube, and the grid electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube; the source electrode of the second NMOS tube is grounded, and the grid electrode of the second NMOS tube is connected with the input end of the first latch unit. The implementation mode of the pull-up circuit can be realized by using only a few simple MOS tubes, the devices are few, the occupied circuit volume is small, and the production and the manufacture are convenient.

With reference to the first aspect and any one of the foregoing possible implementation manners, in a fourth possible implementation manner, the second power supply includes: a first power supply and a first impedance; the grid electrode of the first PMOS tube is connected with a second power supply, and specifically comprises the following components: and the grid electrode of the first PMOS tube is connected with the first power supply through the first impedance. The internal driving force of the MOS tube can be increased through the first impedance, and in addition, the second power supply can be realized through the first power supply and the first impedance in order to save the signal source of the D trigger.

With reference to the first aspect and any one of the foregoing possible implementation manners, in a fifth possible implementation manner, the first impedance includes: the second PMOS tube, the third PMOS tube and the fourth PMOS tube; the drain electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube, the source electrode of the second PMOS tube is connected with the drain electrode of the third PMOS tube, the source electrode of the third PMOS tube is connected with the drain electrode of the fourth PMOS tube, and the source electrode of the fourth PMOS tube is connected with the first power supply; and the grid electrodes of the second PMOS tube, the third PMOS tube and the fourth PMOS tube are all connected with low level. In order to generate the convenience of manufacturing, the impedance is realized by connecting a plurality of MOS tubes in series, namely, the impedance is realized by utilizing the internal resistance of the MOS tubes, the number of the MOS tubes connected in series is not limited, and the larger the number is, the larger the impedance connected in series is.

With reference to the first aspect and any one of the foregoing possible implementation manners, in a sixth possible implementation manner, the pull-down circuit includes: the fifth PMOS tube, the sixth PMOS tube and the third NMOS tube; the grid electrode of the fifth PMOS tube is connected with the output end of the first latch unit, the source electrode of the fifth PMOS tube is connected with the first power supply, and the drain electrode of the fifth PMOS tube is connected with the source electrode of the sixth PMOS tube; the drain electrode of the sixth PMOS tube is connected with a third power supply; the grid electrode of the sixth PMOS tube is connected with the input end of the first latch unit; the voltage of the third power supply is lower than that of the first power supply; the grid electrode of the third NMOS tube is connected with the drain electrode of the sixth PMOS tube, the source electrode of the third NMOS tube is grounded, and the drain electrode of the third NMOS tube is connected with the input end of the first latch unit. The implementation mode of the pull-down circuit is introduced, and the pull-down circuit can be realized by using only a few simple MOS transistors, has few devices and small occupied circuit volume and is convenient to produce and manufacture.

With reference to the first aspect and any one of the foregoing possible implementation manners, in a seventh possible implementation manner, the third power supply includes: a second impedance and ground; the drain electrode of the sixth PMOS tube is connected with a third power supply, specifically: and the drain electrode of the sixth PMOS tube is grounded through a second impedance. In order to increase the internal driving force of the MOS tube, the second impedance can be used for realizing the second impedance, and in addition, in order to save the signal source of the D trigger, the first power supply and the second impedance can be used for realizing the third power supply.

With reference to the first aspect and any one of the foregoing possible implementation manners, in an eighth possible implementation manner, the second impedance includes: the fourth NMOS tube, the fifth NMOS tube and the sixth NMOS tube; the drain electrode of the fourth NMOS tube is connected with the drain electrode of the sixth PMOS tube, the source electrode of the fourth NMOS tube is connected with the drain electrode of the fifth NMOS tube, the source electrode of the fifth NMOS tube is connected with the drain electrode of the sixth NMOS tube, and the source electrode of the sixth NMOS tube is grounded; and the grid electrodes of the fourth NMOS tube, the fifth NMOS tube and the sixth NMOS tube are all connected with a high level. In order to generate the convenience of manufacturing, the impedance is realized by connecting a plurality of MOS tubes in series, namely, the impedance is realized by utilizing the internal resistance of the MOS tubes, the number of the MOS tubes connected in series is not limited, and the larger the number is, the larger the impedance connected in series is.

With reference to the first aspect and any one of the foregoing possible implementation manners, in a ninth possible implementation manner, the pull-up circuit further includes: a seventh NMOS tube; the source electrode of the second NMOS tube is connected with the drain electrode of the seventh NMOS tube, and the source electrode of the seventh NMOS tube is grounded; and the grid electrode of the seventh NMOS tube is connected with the clock signal of the D trigger.

With reference to the first aspect and any one of the foregoing possible implementation manners, in a tenth possible implementation manner, the pull-down circuit further includes: a seventh PMOS transistor; the source electrode of the fifth PMOS tube is connected with the first power supply through the seventh PMOS tube; and the grid electrode of the seventh PMOS tube is connected with the inverted signal of the clock signal of the D trigger. In the above embodiment, the source of the second NMOS is directly grounded, and the source of the fifth PMOS is directly connected to the first power supply. Therefore, in order to reduce the overall power consumption of the D flip-flop, the seventh PMOS transistor and the seventh NMOS transistor are added in the above embodiment.

With reference to the first aspect and any one of the foregoing possible implementation manners, in an eleventh possible implementation manner, the first NMOS transistor and the second NMOS transistor are both ultra-low voltage threshold ULVT transistors.

With reference to the first aspect and any one of the foregoing possible implementation manners, in a twelfth possible implementation manner, the fifth PMOS transistor and the sixth PMOS transistor are ultra-low voltage threshold ULVT transistors.

In one implementation, the first inverter and the second inverter are both tri-state inverters.

In one implementation manner, a first enabling end and a second enabling end of the first inverter are respectively connected with a clock signal of the D flip-flop and an inverted signal of the clock signal; the first enabling end and the second enabling end of the second inverter are respectively connected with the clock signal of the D trigger and the inverted signal of the clock signal.

In one implementation, the first latch unit and the second latch unit each include: a tristate inverter and a non-tristate inverter; the input end of the non-tristate inverter is connected with the output end of the tristate inverter, and the input end of the tristate inverter is connected with the output end of the non-tristate inverter; the input end of the non-tri-state inverter is used as the input ends of the first latch unit and the second latch unit, and the output end of the non-tri-state inverter is used as the output ends of the first latch unit and the second latch unit.

In one implementation, the two interlocking inverters in the first and second latch units include one tri-state inverter and one non-tri-state inverter.

In a second aspect, embodiments of the present application further provide a method for preventing metastable states, which is applied to a D flip-flop, where the D flip-flop includes a first inverter, a first latch unit, a second inverter, a second latch unit, and a potential control circuit; the input end of the first inverter is connected with the input end of the D trigger, and the output end of the first inverter is connected with the input end of the first latch unit; the output end of the first latch unit is connected with the input end of the second inverter, the output end of the second inverter is connected with the input end of the second latch unit, and the output end of the second latch unit is connected with the output end of the D trigger; the method comprises the following steps: when the levels of the input end and the output end of the first latch unit are the same, the input end and the output end of the first latch unit are respectively controlled to be low level and high level, or the input end and the output end of the first latch unit are respectively controlled to be high level and low level.

When the level states of the input terminal and the output terminal of the first latch unit are the same, the input terminal and the output terminal of the first latch unit may be forcibly pulled to different levels, for example, the output terminal of the first latch unit is pulled to a high level and the input terminal of the first latch unit is pulled to a low level. Therefore, the dead state that the level of the input end and the output end of the first latch unit is the same is broken, metastable state is avoided, and when the metastable state of the D trigger occurs, the metastable state is automatically avoided, so that the output end of the D trigger outputs the correct level state.

In a first implementation manner of the second aspect, when the levels of the input terminal and the output terminal of the first latch unit are the same, the input terminal and the output terminal of the first latch unit are respectively controlled to be a low level and a high level, specifically: when the levels of the input end and the output end of the first latch unit are the same, the output end of the first latch unit is pulled up to be high level by a pull-up circuit, and the input end of the first latch unit is pulled down to be low level by a pull-down circuit; the input end and the output end of the first latch unit are connected with a first power supply through the pull-up circuit, and the input end and the output end of the first latch unit are grounded through the pull-down circuit.

With reference to the first aspect and any one of the foregoing possible implementation manners, in a second possible implementation manner, when levels of an input end and an output end of the first latch unit are the same, the input end and the output end of the first latch unit are respectively controlled to be a high level and a low level, specifically: when the levels of the input end and the output end of the first latch unit are the same, the output end of the first latch unit is pulled down to be low level through a pull-up circuit; when the levels of the input end and the output end of the first latch unit are the same, the input end of the first latch unit is pulled up to be high level through a pull-down circuit; the input end and the output end of the first latch unit are connected with a first power supply through the pull-up circuit, and the input end and the output end of the first latch unit are grounded through the pull-down circuit.

In a second aspect, embodiments of the present application further provide a method for preventing metastable states, which is applied to a D flip-flop, where the D flip-flop includes a first inverter, a first latch unit, a second inverter, a second latch unit, and a potential control circuit; the input end of the first inverter is connected with the input end of the D trigger, and the output end of the first inverter is connected with the input end of the first latch unit; the output end of the first latch unit is connected with the input end of the second inverter, the output end of the second inverter is connected with the input end of the second latch unit, and the output end of the second latch unit is connected with the output end of the D trigger; the method comprises the following steps: when the levels of the input end and the output end of the first latch unit are the same, the input end and the output end of the first latch unit are respectively controlled to be low level and high level, or the input end and the output end of the first latch unit are respectively controlled to be high level and low level. When the input end and the output end of the first latch unit have the same level, the input end and the output end of the first latch unit are both high level, or are both low level, or are both half high level. Of course, the half high level corresponds to the half low level.

The essential reason why the metastable state of the D flip-flop occurs is that the internal latch is in a state of unstable latch, specifically, CP starts sampling when the rising edge or the falling edge of the input signal at the input end changes, and the latch latches unstably, so that a state of level stiffness occurs, and therefore, in the embodiment of the present application, a pull-up circuit and a pull-down circuit are added at the input end and the output end of the first latch unit, so that the level stiffness state is forcedly broken.

According to the method provided by the embodiment, when the level states of the input end and the output end of the first latch unit are stiff, the output end of the first latch unit is pulled up to be in a high level state, the input end of the first latch unit is pulled down to be in a low level state, the level states of the input end and the output end of the first latch unit are opposite, and therefore the stiff state of the input end level and the output end level of the first latch unit is broken. Thus avoiding metastable state, and when the metastable state of the D trigger occurs, automatically avoiding metastable state, so that the output end of the D trigger outputs correct level state.

In a second implementation manner of the second aspect, when the levels of the input terminal and the output terminal of the first latch unit are the same, the input terminal and the output terminal of the first latch unit are respectively controlled to be a high level and a low level, specifically: when the levels of the input end and the output end of the first latch unit are the same, the output end of the first latch unit is pulled down to be low level through a pull-up circuit; when the levels of the input end and the output end of the first latch unit are the same, the input end of the first latch unit is pulled up to be high level through a pull-down circuit; the input end and the output end of the first latch unit are connected with a first power supply through the pull-up circuit, and the input end and the output end of the first latch unit are grounded through the pull-down circuit.

In a third aspect, embodiments of the present application further provide a clock domain crossing synchronization circuit, including more than two D flip-flops: a first D flip-flop and a second D flip-flop; the input end of the first D trigger is used for receiving data of a first clock domain; the output end of the first D trigger is connected with the input end of the second D trigger; the pulse input end of the first D trigger and the pulse input end of the second D trigger are used for receiving clock signals of a second clock domain, wherein the first clock domain and the second clock domain are asynchronous clock domains.

From the above technical solutions, the embodiments of the present application have the following advantages:

the D trigger is internally provided with a potential control circuit which is connected with the input end and the output end of the first latch unit. When the level states of the input end and the output end of the first latch unit are the same, the D flip-flop provided by the embodiment of the application can forcedly pull the input end and the output end of the first latch unit to different levels through the potential control circuit, for example, pull the output end of the first latch unit to high level and pull the input end of the first latch unit to low level. Therefore, the dead state that the level of the input end and the output end of the first latch unit is the same is broken, metastable state is avoided, and when the metastable state of the D trigger occurs, the metastable state is automatically avoided, so that the output end of the D trigger outputs the correct level state.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a D flip-flop;

FIG. 2 is a waveform diagram corresponding to metastability;

FIG. 3a is a schematic diagram of a D flip-flop for preventing metastability according to an embodiment of the present application;

FIG. 3b is a schematic diagram of a D flip-flop for preventing metastability according to an embodiment of the present application;

FIG. 4 is a schematic diagram of the latch interior provided in an embodiment of the present application;

FIG. 5 is a schematic diagram of another D flip-flop for preventing metastability according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a D flip-flop for preventing metastability according to an embodiment of the present application;

FIG. 7 is a schematic diagram of another D flip-flop for preventing metastability according to an embodiment of the present application;

fig. 8 is a schematic diagram of a D flip-flop for preventing metastability according to an embodiment of the present application.

Detailed Description

In order to enable those skilled in the art to better understand the technical solutions provided by the embodiments of the present application, the following description describes a D flip-flop with reference to the accompanying drawings.

Referring to fig. 1, a schematic diagram of a D flip-flop is shown.

The D flip-flop includes a data input D, a data output Q and a pulse input, as can be seen from fig. 1, D is connected to external data din, and the pulse input is connected to an external clock signal clk. For example, on the rising edge of clk, Q outputs data of D, and when D is 1, Q is 1. When D is 0, Q is 0.

The process of metastability of the D flip-flop is described below in conjunction with the accompanying figures. Referring to fig. 2, a waveform diagram corresponding to metastability is shown.

The setup time and hold time of the flip-flop define a time window around the rising edge of the clock, and if the data at the data input of the flip-flop changes (or data updates) within the time window, a timing violation occurs. Because the setup and hold time requirements are violated, a node within the flip-flop may float within a voltage range and fail to stabilize in either a logic 0 or logic 1 state. If data is collected during the time window phase, the transistors in the flip-flop cannot be reliably set to the level corresponding to a logic 0 or a logic 1. So that the transistor is not at the high or low level corresponding to the saturation region at this time, but is hovering in an intermediate level state (the intermediate level may be a correct value, or may not).

In order to eliminate metastable state, the method can be realized by beating a plurality of beats, such as beating 3 beats or beating 5 beats, but for the occasion with high real-time requirement, the plurality of beats causes signal transmission delay, and the requirement of products cannot be met.

In view of the above, the present application provides a D flip-flop including a potential control circuit connected to an input terminal and an output terminal of a first latch unit. When the level states of the input end and the output end of the first latch unit are the same, the D flip-flop provided by the embodiment of the application can forcedly pull the input end and the output end of the first latch unit to different levels through the potential control circuit, for example, pull the output end of the first latch unit to high level and pull the input end of the first latch unit to low level. Therefore, the dead state that the level of the input end and the output end of the first latch unit is the same is broken, metastable state is avoided, and when the metastable state of the D trigger occurs, the metastable state is automatically avoided, so that the output end of the D trigger outputs the correct level state.

In order to enable those skilled in the art to better understand the present invention, the following description will make clear and complete descriptions of the technical solutions according to the embodiments of the present invention with reference to the accompanying drawings.

Embodiment one:

referring to fig. 3a, a schematic diagram of a D flip-flop for preventing metastability according to an embodiment of the present application is shown.

The metastable state preventing D flip-flop provided in this embodiment includes: a first inverter 10, a first latch unit 20, a second inverter 30, a second latch unit 40, and a potential control circuit 100;

the input end of the first inverter 10 is connected with the input end of the D trigger, and the output end of the first inverter 10 is connected with the input end of the first latch unit 20; the output end of the first latch unit 20 is connected with the input end of the second inverter 30, the output end of the second inverter 30 is connected with the input end of the second latch unit 40, and the output end of the second latch unit 40 is connected with the output end of the D trigger;

the potential control circuit 100 is configured to control the input terminal and the output terminal of the first latch unit 20 to be low level and high level, respectively, or to control the input terminal and the output terminal of the first latch unit 20 to be high level and low level, respectively, when the levels of the input terminal and the output terminal of the first latch unit 20 are the same.

When the input terminal and the output terminal of the first latch unit 20 have the same level, the input terminal and the output terminal of the first latch unit 20 are both at the high level, both at the low level, or both at the half-high level. Of course, the half high level corresponds to the half low level.

When the metastable state of the D flip-flop occurs, the level states of the input end and the output end of the first latch unit 20 are similar, for example, are high, are low or are half high, so that the level of the input end and the level of the output end of the first latch unit 20 are in a stiff state, and the output level of the D flip-flop cannot reach the confirmation state, namely, can be 1, can be 0, or can be in an oscillation state, and can output a useless level state. Therefore, in the embodiment of the present application, the level control circuit 100 forces the levels of the input terminal and the output terminal of the first latch unit 20 to be different, so that the level states of the two ends are opposite, and the level states are forced to break the dead state.

The method comprises the following steps:

the potential control circuit 100 is configured to pull the output terminal of the first latch unit 20 high to a high level when the input terminal and the output terminal of the first latch unit 20 are low, high, or half high; that is, when both the input terminal and the output terminal of the first latch unit 20 are 0, the potential control circuit 100 pulls the output terminal of the first latch unit 20 high to 1. When both the input terminal and the output terminal of the first latch unit 20 are 1, the potential control circuit 100 pulls the output terminal of the first latch unit 20 high to 1. When the input terminal and the output terminal of the first latch unit 20 are both half high, the potential control circuit 100 pulls the output terminal of the first latch unit 20 high to 1. As can be seen from the above, the potential control circuit 100 essentially pulls up the level state of the output terminal of the first latch unit 20, that is, when the input terminal of the first latch unit 20 and the level of the output terminal have a dead state, the level state of the output terminal of the first latch unit 20 is pulled up to the high level regardless of the specific level state of the input terminal of the first latch unit 20.

The half-high state corresponds to the half-low state.

The potential control circuit 100 is configured to pull the input terminal of the first latch unit 20 low to a low level when the input terminal and the output terminal of the first latch unit 20 are low, high, or half high. That is, when both the input terminal and the output terminal of the first latch unit 20 are 0, the potential control circuit 100 pulls down the input terminal of the first latch unit 20 to 0. When the input terminal and the output terminal of the first latch unit 20 are both 1, the potential control circuit 100 pulls down the input terminal of the first latch unit 20 to 0. When the input terminal and the output terminal of the first latch unit 20 are both half high, the potential control circuit 100 pulls down the input terminal of the first latch unit 20 to 0. As can be seen from the above, the potential control circuit 100 essentially pulls down the level state of the input terminal of the first latch unit 20, that is, when the level of the input terminal and the output terminal of the first latch unit 20 is in a stiff state, the level state of the input terminal of the first latch unit 20 is pulled down to a low level regardless of the specific level state of the input terminal of the first latch unit 20.

In the D flip-flop provided in this embodiment, when the level states of the input terminal and the output terminal of the first latch unit are stiff, a potential control circuit is added in the D flip-flop, and the potential control circuit is connected to the input terminal and the output terminal of the first latch unit. When the level states of the input end and the output end of the first latch unit are the same, the D flip-flop provided by the embodiment of the application can forcedly pull the input end and the output end of the first latch unit to different levels through the potential control circuit, for example, pull the output end of the first latch unit to high level and pull the input end of the first latch unit to low level. Therefore, the dead state that the level of the input end and the output end of the first latch unit is the same is broken, metastable state is avoided, and when the metastable state of the D trigger occurs, the metastable state is automatically avoided, so that the output end of the D trigger outputs the correct level state.

A specific implementation of the potential control circuit is described below with reference to the accompanying drawings. The potential control circuit in this embodiment includes a pull-up circuit and a pull-down circuit. The pull-up circuit and pull-down circuit may include two implementations:

first kind: the input terminal and the output terminal of the first latch unit are pulled to a high level and a low level, respectively. The method comprises the following steps: the input end and the output end of the first latch unit are connected with a first power supply through the pull-up circuit, and are grounded through the pull-down circuit; the pull-up circuit is used for pulling the output end of the first latch unit to be high level when the levels of the input end and the output end of the first latch unit are the same; the pull-down circuit is used for pulling the input end of the first latch unit to be low level when the level of the input end and the level of the output end of the first latch unit are the same.

Second kind: the input terminal and the output terminal of the first latch unit are pulled to a low level and a high level, respectively. The method comprises the following steps: the input end and the output end of the first latch unit are connected with a first power supply through the pull-up circuit, and are grounded through the pull-down circuit; the pull-up circuit is used for pulling the output end of the first latch unit to be low level when the levels of the input end and the output end of the first latch unit are the same; and the pull-down circuit is used for pulling the input end of the first latch unit to be high level when the level of the input end and the level of the output end of the first latch unit are the same.

The following description will take an example in which the pull-up circuit pulls the output terminal of the first latch unit to a high level and the pull-down circuit pulls the input terminal of the first latch unit to a low level with reference to the accompanying drawings.

Referring to fig. 3b, a schematic diagram of a D flip-flop for preventing metastability according to an embodiment of the present application is shown.

The D flip-flop for preventing metastability provided in this embodiment includes: a first inverter 10, a first latch unit 20, a second inverter 30, a second latch unit 40, a pull-up circuit 50, and a pull-down circuit 60; it should be noted that the above circuits are all inside the D flip-flop.

the first inverter 10 and the second inverter 30 are both used for inverting the input signal and outputting the inverted input signal, for example, when the input signal is high level 1, the output signal is low level 0; when the input signal is low level 0, the output signal is high level 1.

The first inverter 10 and the second inverter 30 may be tri-state flip-flops or non-tri-state flip-flops.

When the first inverter 10 and the second inverter 30 may be tri-state flip-flops, the enable terminal of the first inverter 10 is connected to the clock signal of the D flip-flop and the inverted signal of the clock signal; the enable terminal of the second inverter 30 is connected to the clock signal of the D flip-flop and the inverted signal of the clock signal.

The first latch unit 20 and the second latch unit 40 may have the same structure or may be different from each other. However, in order to make the manufacturing process simple and easy to implement, the actual product may take the same structure. As the name suggests, the latch unit temporarily stores the signal to maintain a certain level state, so that the level state of the output terminal does not change along with the level state change of the input terminal, and the level state of the input terminal is saved to the output terminal only when the latch signal is present, and is not changed until the next latch signal arrives.

When the structures of the first latch unit 20 and the second latch unit 40 are identical, two interlocking inverters in the first latch unit and the second latch unit include one tri-state inverter and one non-tri-state inverter. The structure of the first latch unit 20 and the second latch unit 40, which are interlocked between the two inverters, can be seen in fig. 4.

Wherein the first inverter 10 and the first latch unit 20 form a first latch. Similarly, the second inverter 30 and the second latch unit 40 form a second latch.

As can be seen from fig. 4, the latch unit comprises two inverters, wherein the inverter 21 is a normal inverter and the inverter 22 is an inverter with enable control, i.e. a tri-state inverter. The output end of the inverter 21 is connected with the input end of the inverter 22, and the output end of the inverter 22 is connected with the input end of the inverter 21, so that the two inverters form an interlocking, and the function of signal latching is realized. And because the driving capability of the two inverters is the same, a better interlocking effect is realized.

Wherein two enable terminals of the inverter 22 are connected to the clock signal CP of the D flip-flop and the inverted signal of the clock signal

The input end and the output end of the first latch unit 20 are both connected with a power supply through the pull-up circuit 50, and the input end and the output end of the first latch unit 20 are both grounded through the pull-down circuit 60;

When the metastable state of the D flip-flop occurs, the level states of the input end and the output end of the first latch unit 20 are similar, for example, are high, are low or are half high, so that the level of the input end and the level of the output end of the first latch unit 20 are in a stiff state, and the output level of the D flip-flop cannot reach the confirmation state, namely, can be 1, can be 0, or can be in an oscillation state, and can output a useless level state. Accordingly, the embodiment of the present application forces the levels of the input terminal and the output terminal of the first latch unit 20 to be pulled up and pulled down, respectively, by the pull-up circuit 50 and the pull-down circuit 60, forcing it to break the dead state.

The method comprises the following steps:

the pull-up circuit 50 is configured to pull the output terminal of the first latch unit 20 high to a high level when the input terminal and the output terminal of the first latch unit 20 are both low, both high, or both half high; that is, when both the input terminal and the output terminal of the first latch unit 20 are 0, the pull-up circuit 50 pulls the output terminal of the first latch unit 20 high to 1. When the input terminal and the output terminal of the first latch unit 20 are both 1, the pull-up circuit 50 pulls the output terminal of the first latch unit 20 high to 1. When the input terminal and the output terminal of the first latch unit 20 are both half high, the pull-up circuit 50 pulls the output terminal of the first latch unit 20 high to 1. It can be seen that the pull-up circuit 50 essentially pulls up the level state of the output terminal of the first latch unit 20, i.e. when the input terminal of the first latch unit 20 and the level of the output terminal have a dead state, the level state of the output terminal of the first latch unit 20 is pulled high regardless of the specific level state of the input terminal of the first latch unit 20.

The half-high state corresponds to the half-low state.

The pull-down circuit 60 is configured to pull the input terminal of the first latch unit 20 low to a low level when the input terminal and the output terminal of the first latch unit 20 are low, high, or half high. That is, when both the input terminal and the output terminal of the first latch unit 20 are 0, the pull-down circuit 60 pulls down the input terminal of the first latch unit 20 to 0. When the input and output of the first latch unit 20 are both 1, the pull-down circuit 60 pulls the input of the first latch unit 20 low to 0. When the input and output of the first latch unit 20 are both half high, the pull-down circuit 60 pulls the input of the first latch unit 20 low to 0. It can be seen that the pull-down circuit 60 essentially pulls down the level state of the input terminal of the first latch unit 20, i.e. when the level of the input terminal and the output terminal of the first latch unit 20 is in a stiff state, the level state of the input terminal of the first latch unit 20 is pulled low regardless of the specific level state of the input terminal of the first latch unit 20.

In the D flip-flop provided in this embodiment, when the level states of the input end and the output end of the first latch unit are stiff, the output end of the first latch unit is pulled up to be in a high level state by the pull-up circuit, and the input end of the first latch unit is pulled down to be in a low level state by the pull-down circuit, so that the level states of the input end and the output end of the first latch unit are opposite, and the stiff state of the input end level and the output end level of the first latch unit is broken. Thus avoiding metastable state, and when the metastable state of the D trigger occurs, automatically avoiding metastable state, so that the output end of the D trigger outputs correct level state. In addition, when the metastable state does not occur, the level states of the input terminal and the output terminal of the first latch unit are always opposite, and the added pull-up circuit and pull-down circuit are not active.

Because the inverter and the latch are relatively mature electronic components, the embodiment of the application is not specifically described, and the specific model and type of the inverter and the latch are not specifically limited in the embodiment of the application, and can be selected by a person skilled in the art according to the actual application scenario of the D flip-flop. The implementation manner of the pull-up circuit and the pull-down circuit will be described in detail below with reference to the drawings, so long as the pull-up circuit that pulls up the level can be implemented, and similarly, the pull-down circuit that pulls down the level can be implemented, which only provides a specific circuit structure in this embodiment.

Embodiment two:

referring to fig. 5, a schematic diagram of another metastable prevention D flip-flop according to an embodiment of the present application is shown.

As shown in fig. 5, the first inverter 10 and the second inverter 30 are both pulse-controlled inverters.

Pulse control terminals of the first inverter 10 and the second inverter 30 are respectively connected with a clock signal CP of the D trigger and an inverted signal of the clock signal

As shown in fig. 5, the internal structures of the first latch unit 20 and the second latch unit 40 are the same, and the specific structure is described in detail with reference to fig. 4, and will not be repeated here.

First, referring to the pull-up circuit, as shown in fig. 5, the pull-up circuit includes: the first PMOS tube PH, the first NMOS tube Nb and the second NMOS tube Na;

the drain electrode of the first PMOS tube PH is connected with the output end of the first latch unit, the source electrode of the first PMOS tube PH is connected with the first power supply, and the grid electrode of the first PMOS tube PH is connected with the drain electrode of the first NMOS tube Nb; and the grid electrode of the first PMOS tube PH is connected with a second power supply.

The source electrode of the first NMOS tube Nb is connected with the drain electrode of the second NMOS tube Na, and the grid electrode of the first NMOS tube Nb is connected with the drain electrode of the first PMOS tube PH; the source electrode of the second NMOS tube Na is grounded, and the grid electrode of the second NMOS tube Na is connected with the input end of the first latch unit.

The pull-down circuit is described below, as shown in fig. 5, and includes: a fifth PMOS tube Pb, a sixth PMOS tube Pa and a third NMOS tube NL;

the grid electrode of the fifth PMOS tube Pb is connected with the output end of the first latch unit, the source electrode of the fifth PMOS tube Pb is connected with the power supply, and the drain electrode of the fifth PMOS tube Pb is connected with the source electrode of the sixth PMOS tube Pa; the drain electrode of the sixth PMOS tube Pa is connected with a third power supply; the grid electrode of the sixth PMOS tube Pa is connected with the input end of the first latch unit; thus, the voltage of the third power supply is lower than the first power supply;

the grid electrode of the third NMOS tube NL is connected with the drain electrode of the sixth PMOS tube Pa, the source electrode of the third NMOS tube NL is grounded, and the drain electrode of the third NMOS tube NL is connected with the input end of the first latch unit.

Since the pull-up circuit and the pull-down circuit are both connected to the input terminal and the output terminal of the first latch unit, the pull-up circuit and the pull-down circuit operate simultaneously.

The working principles of the pull-up circuit and the pull-down circuit are respectively described below with reference to the accompanying drawings under three different conditions corresponding to the metastable state of the D flip-flop.

First kind: the input a and the output B of the first latch unit are both low.

When both points a and B are at low level at the same time, pa and Pb are turned on, and since the source of Pb is connected to the first power supply, i.e., connected to high level, the point G1 is raised when Pa and Pb are turned on, i.e., the point G1 is high level, causing NL to be turned on. Since NL is on, the potential at the a point is pulled low, i.e., a is pulled down to a low level.

Thus breaking the level-stiff state of the point A and the point B, the point A becomes low level, and the point B becomes high level. So that metastability can be automatically avoided.

Second kind: the input terminal a and the output terminal B of the first latch unit are both high.

When both points A and B are at high level, na and Nb are conducted, and because the source electrode of Na is grounded, the point G2 is pulled low when Na and Nb are conducted, namely the point G2 is at low level, so that the PH tube is conducted. Since the PH tube is on, the potential at point B is pulled high, i.e., point B is pulled high.

Thus breaking the level-stiff state of the point a and the point B, the point B becomes high, and the point a becomes low when the point B is high due to the inverter in the first latch unit. So that metastability can be automatically avoided.

Third kind: the input a and the output B of the first latch unit are both half high (equivalent to both half low).

It will be appreciated that when both points a and B are in the half-high state, it may also be referred to as both points a and B being in the half-low state.

When both points A and B are at half-height, pa and Pb are conducted, and since the source electrode of Pb is connected with the first power supply, namely, the high level is connected, the point G1 is lifted when Pa and Pb are conducted, namely, the point G1 is at the high level, so that NL is conducted. Since NL is on, the potential at the a point is pulled low, i.e., a is pulled down to a low level.

It can be seen that the switching state of each tube is the same when both points a and B are half high as when both points a and B are low.

When the D flip-flop has no metastable state, the level states of the A and B points are always opposite, one pipe of the corresponding Pa and Pb pipes is always cut off, and one pipe of the corresponding Na and Nb pipes is also always cut off, so that the pull-up circuit and the pull-down circuit are not active.

Here, in order that Pa, pb, na, and Nb are easily driven, an ultra low voltage threshold (ULVT, ultra Low Voltage Threshold) tube may be used for Pa, pb, na, and Nb.

In addition, the two pipes PH and NL can be larger in size, and the corresponding driving capability is stronger, so that the two pipes PH and NL have enough capability of breaking the level stiff state of the two points A and B.

Embodiment III:

referring to fig. 6, a schematic diagram of another metastable prevention D flip-flop according to an embodiment of the present application is shown.

The PMOS tube is conducted under the condition that the source voltage is higher than the grid voltage, so that the voltage of the second power supply is required to be lower than that of the first power supply; for a simple manufacturing process, only one power supply may be applied, the second power supply being realized with the first power supply, for example comprising: a first power supply VCC1 and a first impedance Z1;

the grid electrode of the first PMOS tube PH is connected with a second power supply, and specifically comprises the following components:

the grid electrode of the first PMOS tube PH is connected with the first power supply through the first impedance Z1.

The specific implementation manner of the first impedance is not specifically limited in the embodiments of the present application. For simple manufacturing process, the impedance may be implemented using the internal resistance of the MOS, for example, at least one PMOS transistor may be used. In order to increase the impedance, a plurality of PMOS tubes can be connected in series to realize the first impedance Z1, and the more the MOS tubes connected in series, the larger the formed impedance. The number of the PMOS tubes connected in series is not particularly limited in the embodiment of the application, and can be selected according to actual needs.

The following description will take an example that the first impedance is implemented by three PMOS transistors connected in series, referring to fig. 7, where the first impedance includes: the second PMOS tube P2, the third PMOS tube P3 and the fourth PMOS tube P4;

The second PMOS tube P2, the third PMOS tube P3 and the fourth PMOS tube P4 are connected in series and then connected between the power supply and the grid electrode of the first PMOS tube PH;

the gates of the second PMOS tube P2, the third PMOS tube P3 and the fourth PMOS tube P4 are all connected with a low level TieL.

Similarly, in order to save cost and reduce manufacturing process difficulty, the third power supply may be realized by ground, that is, the drain electrode of the sixth PMOS transistor is connected to the third power supply, specifically:

the drain electrode of the sixth PMOS tube Pa is grounded through a second impedance Z2.

Similar to the first impedance, the second impedance Z2 may also be realized by the internal resistance of the MOS transistors, and in order to increase the resistance of the second impedance Z2, a plurality of MOS transistors may be connected in series, and the more MOS transistors connected in series, the greater the impedance is formed. The number of MOS tubes connected in series is not particularly limited, and three MOS tubes connected in series are taken as an example for introduction. For example, the second impedance includes: the fourth NMOS tube N4, the fifth NMOS tube N5 and the sixth NMOS tube N6;

the fourth NMOS transistor N4, the fifth NMOS transistor N5, and the sixth NMOS transistor N6 are connected in series, and then connected between the drain electrode of the sixth PMOS transistor Pa and ground;

the gates of the fourth NMOS transistor N4, the fifth NMOS transistor N5, and the sixth NMOS transistor N6 are all connected to the high level tie h.

The sources of the low level tie l and the high level tie h are not particularly limited in the embodiments of the present application.

In this embodiment, in order to facilitate the implementation of the D flip-flop manufacturing process, the first impedance is implemented by using a plurality of PMOS transistors in series, that is, the first impedance is implemented by using the internal resistance of the MOS transistor. And similarly, the second impedance is realized by connecting a plurality of NMOS tubes in series, namely, the second impedance is realized by utilizing the internal resistance of the MOS tubes. Since the MOS transistor is easily implemented in a semiconductor process, it is unnecessary to connect resistors to implement the first and second impedances.

In modern computers and communication chips, a large number of D flip-flops are included, and for scenes with high communication and computation delay requirements, the delay requirement of asynchronous processing signal interaction is as small as possible, so that a low-delay design and a metastable-free D flip-flop are required to be used for asynchronous data interaction.

Embodiment four:

referring to fig. 8, a schematic diagram of a D flip-flop for preventing metastability according to an embodiment of the present application is provided.

The source of Na in the above embodiment is directly grounded, and the source of Pb is directly connected to the first power supply. This results in some power consumption and increases the power wasted by the D flip-flop, so that another implementation is described below in conjunction with fig. 8 in order to reduce the overall power consumption of the D flip-flop.

The D flip-flop provided in this embodiment, the pull-up circuit further includes: a seventh NMOS transistor N7;

the source electrode of the second NMOS tube Na is grounded through the seventh NMOS tube N7;

the gate of the seventh NMOS transistor N7 is connected to the clock signal CP of the D flip-flop.

I.e. the switching state of N7 is controlled by the clock signal CP, N7 is turned on when CP is high. When CP is low, N7 is not turned on, and thus when CP is low, N7 is not turned on so that power consumption does not occur. Therefore, the N7 is conducted when the pull-up circuit needs to work, and is not conducted when the pull-up circuit does not need to work, so that the power consumption of the whole D trigger is reduced.

Similarly, the pull-down circuit further includes: a seventh PMOS tube P7;

the source electrode of the fifth PMOS tube Pb is connected with the first power supply VCC1 through the seventh PMOS tube P7;

the grid electrode of the seventh PMOS tube P7 is connected with the inverted signal of the clock signal of the D trigger

I.e. the switching state of P7 is controlled by the inverted signal of the clock signal CPWhen->At low level, P7 is turned on. When->At high level P7 is not conductive, therefore when +.>At high level, P7 is not conductive and thus does not generate power consumption. Therefore, the P7 is conducted when the pull-down circuit needs to work, and is not conducted when the pull-down circuit does not need to work, so that the power consumption of the whole D trigger is reduced.

In summary, the D flip-flop provided in the embodiment of the present application controls the conducting states of N7 and P7 through the clock signal, so that N7 and P7 are conducted when the first flip-flop works, thereby reducing the power consumption of the whole D flip-flop.

The source of the clock signal of the D flip-flop is not particularly limited in the embodiments of the present application, and may be implemented using a circuit capable of generating the clock signal.

The D flip-flop provided in the above embodiment may be applied to occasions with high requirements for real-time communication or calculation delay, such as communication and computer equipment, automatic driving, and the internet of vehicles, and may also be applied to the artificial intelligence field. The D trigger provided by the embodiment of the application can be in the technical field of low-delay synchronization, and can ensure no metastable state, so that the output level is stable.

Based on the metastable-preventing D flip-flop provided in the above embodiment, the embodiment of the present application further provides a metastable-preventing method, which is specifically described below.

The metastable state prevention method is applied to a D trigger, and the D trigger comprises a first inverter, a first latch unit, a second inverter, a second latch unit and a potential control circuit; the input end of the first inverter is connected with the input end of the D trigger, and the output end of the first inverter is connected with the input end of the first latch unit; the output end of the first latch unit is connected with the input end of the second inverter, the output end of the second inverter is connected with the input end of the second latch unit, and the output end of the second latch unit is connected with the output end of the D trigger;

The method comprises the following steps:

when the levels of the input end and the output end of the first latch unit are the same, the input end and the output end of the first latch unit are respectively controlled to be low level and high level, or the input end and the output end of the first latch unit are respectively controlled to be high level and low level.

When the input end and the output end of the first latch unit have the same level, the input end and the output end of the first latch unit are both high level, or are both low level, or are both half high level. Of course, the half high level corresponds to the half low level.

In the method provided in this embodiment, when the level states of the input end and the output end of the first latch unit are the same, the input end and the output end of the first latch unit may be forced to be pulled to different levels by the potential control circuit, for example, the output end of the first latch unit is pulled to a high level, and the input end of the first latch unit is pulled to a low level. Therefore, the dead state that the level of the input end and the output end of the first latch unit is the same is broken, metastable state is avoided, and when the metastable state of the D trigger occurs, the metastable state is automatically avoided, so that the output end of the D trigger outputs the correct level state.

In one implementation manner, when the levels of the input end and the output end of the first latch unit are the same, the input end and the output end of the first latch unit are respectively controlled to be a low level and a high level, specifically:

when the levels of the input end and the output end of the first latch unit are the same, the output end of the first latch unit is pulled up to be high level by a pull-up circuit, and the input end of the first latch unit is pulled down to be low level by a pull-down circuit; the input end and the output end of the first latch unit are connected with a first power supply through the pull-up circuit, and the input end and the output end of the first latch unit are grounded through the pull-down circuit.

In another implementation manner, when the levels of the input end and the output end of the first latch unit are the same, the input end and the output end of the first latch unit are respectively controlled to be a high level and a low level, specifically:

when the levels of the input end and the output end of the first latch unit are the same, the output end of the first latch unit is pulled down to be low level through a pull-up circuit; when the levels of the input end and the output end of the first latch unit are the same, the input end of the first latch unit is pulled up to be high level through a pull-down circuit; the input end and the output end of the first latch unit are connected with a first power supply through the pull-up circuit, and the input end and the output end of the first latch unit are grounded through the pull-down circuit.

Based on the metastable-prevention D flip-flop and the metastable-prevention method provided in the above embodiments, the embodiments of the present application further provide a clock domain crossing synchronization circuit, including the two D flip-flops described in the above embodiments: a first D flip-flop and a second D flip-flop;

the input end of the first D flip-flop is used for receiving data of a first clock domain;

the output end of the first D trigger is connected with the input end of the second D trigger;

the pulse input end of the first D trigger and the pulse input end of the second D trigger are used for receiving clock signals of a second clock domain, wherein the first clock domain and the second clock domain are asynchronous clock domains.

The circuit comprises a D trigger which can prevent metastability, so that the clock domain crossing synchronous circuit can realize reliable transmission of data.

It should be understood that in this application, "at least one" means one or more, and "a plurality" means two or more. "and/or" for describing the association relationship of the association object, the representation may have three relationships, for example, "a and/or B" may represent: only a, only B and both a and B are present, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b or c may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c may be single or plural.

The above embodiments are merely for illustrating the technical solution of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the corresponding technical solutions.

Claims

1. A metastable-prevention D flip-flop, comprising: a first inverter, a first latch unit, a second inverter, a second latch unit, and a potential control circuit;

the input end of the first inverter is connected with the input end of the D trigger, and the output end of the first inverter is connected with the input end of the first latch unit; the output end of the first latch unit is connected with the input end of the second inverter, the output end of the second inverter is connected with the input end of the second latch unit, and the output end of the second latch unit is connected with the output end of the D trigger;

the potential control circuit is used for controlling the input end and the output end of the first latch unit to be low level and high level respectively or controlling the input end and the output end of the first latch unit to be high level and low level respectively when the levels of the input end and the output end of the first latch unit are the same; the potential control circuit comprises a pull-up circuit and a pull-down circuit; the input end and the output end of the first latch unit are connected with a first power supply through the pull-up circuit, and are grounded through the pull-down circuit; the pull-down circuit includes: the fifth PMOS tube, the sixth PMOS tube and the third NMOS tube; the grid electrode of the fifth PMOS tube is connected with the output end of the first latch unit, the source electrode of the fifth PMOS tube is connected with the power supply, and the drain electrode of the fifth PMOS tube is connected with the source electrode of the sixth PMOS tube; the drain electrode of the sixth PMOS tube is connected with a third power supply; the grid electrode of the sixth PMOS tube is connected with the input end of the first latch unit; the voltage of the third power supply is lower than that of the first power supply; the grid electrode of the third NMOS tube is connected with the drain electrode of the sixth PMOS tube, the source electrode of the third NMOS tube is grounded, and the drain electrode of the third NMOS tube is connected with the input end of the first latch unit.

2. The D flip-flop of claim 1 wherein,

the pull-up circuit is used for pulling the output end of the first latch unit to be high level when the levels of the input end and the output end of the first latch unit are the same;

the pull-down circuit is used for pulling the input end of the first latch unit to be low level when the level of the input end and the level of the output end of the first latch unit are the same.

3. The D flip-flop of claim 1 wherein,

the pull-up circuit is used for pulling the output end of the first latch unit to be low level when the levels of the input end and the output end of the first latch unit are the same;

and the pull-down circuit is used for pulling the input end of the first latch unit to be high level when the level of the input end and the level of the output end of the first latch unit are the same.

4. The D flip-flop of claim 2, wherein said pull-up circuit comprises: the first PMOS tube, the first NMOS tube and the second NMOS tube;

the drain electrode of the first PMOS tube is connected with the output end of the first latch unit, the source electrode of the first PMOS tube is connected with the first power supply, and the grid electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube; the grid electrode of the first PMOS tube is connected with a second power supply; the voltage of the second power supply is lower than that of the first power supply;

The source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube, and the grid electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube; the source electrode of the second NMOS tube is grounded, and the grid electrode of the second NMOS tube is connected with the input end of the first latch unit.

5. The D flip-flop of claim 4, wherein said second power supply comprises: a first power supply and a first impedance;

the grid electrode of the first PMOS tube is connected with a second power supply, and specifically comprises the following components:

and the grid electrode of the first PMOS tube is connected with the first power supply through the first impedance.

6. The D flip-flop of claim 5, wherein said first impedance comprises: the second PMOS tube, the third PMOS tube and the fourth PMOS tube;

the drain electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube, the source electrode of the second PMOS tube is connected with the drain electrode of the third PMOS tube, the source electrode of the third PMOS tube is connected with the drain electrode of the fourth PMOS tube, and the source electrode of the fourth PMOS tube is connected with the first power supply;

and the grid electrodes of the second PMOS tube, the third PMOS tube and the fourth PMOS tube are all connected with low level.

7. The D flip-flop of claim 6, wherein said third power supply comprises: a second impedance and ground;

The drain electrode of the sixth PMOS tube is connected with a third power supply, specifically:

and the drain electrode of the sixth PMOS tube is grounded through a second impedance.

8. The D flip-flop of claim 7, wherein said second impedance comprises: the fourth NMOS tube, the fifth NMOS tube and the sixth NMOS tube;

the drain electrode of the fourth NMOS tube is connected with the drain electrode of the sixth PMOS tube, the source electrode of the fourth NMOS tube is connected with the drain electrode of the fifth NMOS tube, the source electrode of the fifth NMOS tube is connected with the drain electrode of the sixth NMOS tube, and the source electrode of the sixth NMOS tube is grounded;

and the grid electrodes of the fourth NMOS tube, the fifth NMOS tube and the sixth NMOS tube are all connected with a high level.

9. The D flip-flop of any of claims 4-8, wherein said pull-up circuit further comprises: a seventh NMOS tube;

the source electrode of the second NMOS tube is connected with the drain electrode of the seventh NMOS tube, and the source electrode of the seventh NMOS tube is grounded;

and the grid electrode of the seventh NMOS tube is connected with the clock signal of the D trigger.

10. The D flip-flop of claim 6, wherein said pull-down circuit further comprises: a seventh PMOS transistor;

the source electrode of the fifth PMOS tube is connected with the first power supply through the seventh PMOS tube;

And the grid electrode of the seventh PMOS tube is connected with the inverted signal of the clock signal of the D trigger.

11. The D flip-flop of claim 4, wherein said first NMOS transistor and said second NMOS transistor are both ultra low voltage threshold ULVT transistors.

12. The D flip-flop of claim 6 or 8, wherein said fifth PMOS transistor and sixth PMOS transistor are both ultra low voltage threshold ULVT transistors.

13. A method for preventing metastability, which is characterized by being applied to a D trigger, wherein the D trigger comprises a first inverter, a first latch unit, a second inverter, a second latch unit and a potential control circuit; the input end of the first inverter is connected with the input end of the D trigger, and the output end of the first inverter is connected with the input end of the first latch unit; the output end of the first latch unit is connected with the input end of the second inverter, the output end of the second inverter is connected with the input end of the second latch unit, and the output end of the second latch unit is connected with the output end of the D trigger; the potential control circuit comprises a pull-up circuit and a pull-down circuit; the input end and the output end of the first latch unit are connected with a first power supply through the pull-up circuit, and are grounded through the pull-down circuit; the pull-down circuit includes: the fifth PMOS tube, the sixth PMOS tube and the third NMOS tube; the grid electrode of the fifth PMOS tube is connected with the output end of the first latch unit, the source electrode of the fifth PMOS tube is connected with the power supply, and the drain electrode of the fifth PMOS tube is connected with the source electrode of the sixth PMOS tube; the drain electrode of the sixth PMOS tube is connected with a third power supply; the grid electrode of the sixth PMOS tube is connected with the input end of the first latch unit; the voltage of the third power supply is lower than that of the first power supply; the grid electrode of the third NMOS tube is connected with the drain electrode of the sixth PMOS tube, the source electrode of the third NMOS tube is grounded, and the drain electrode of the third NMOS tube is connected with the input end of the first latch unit;

The method comprises the following steps:

14. The method according to claim 13, wherein when the levels of the input and output terminals of the first latch unit are the same, the input and output terminals of the first latch unit are controlled to be low and high, respectively, in particular:

15. The method according to claim 13, wherein when the levels of the input and output terminals of the first latch unit are the same, the input and output terminals of the first latch unit are controlled to be high and low levels, respectively, in particular: