CN108540110A - D type flip flop - Google Patents
D type flip flop Download PDFInfo
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- CN108540110A CN108540110A CN201710117126.0A CN201710117126A CN108540110A CN 108540110 A CN108540110 A CN 108540110A CN 201710117126 A CN201710117126 A CN 201710117126A CN 108540110 A CN108540110 A CN 108540110A
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- type flip
- flip flop
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- latch
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/3562—Bistable circuits of the master-slave type
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Abstract
A kind of d type flip flop, including：With the slave latch of main latch coupling；It is described to include from latch：The output data of the main latch is exported to the first output end of the d type flip flop suitable for being connected during clock signal is in the first logical value with the first switch of the first output end of d type flip flop coupling；The data opposite with the output data logic of the main latch are exported to the second output terminal of the d type flip flop suitable for being connected during the clock signal is in the first logical value with the second switch of d type flip flop second output terminal coupling；The latch cicuit coupled respectively with the first output end of the d type flip flop and second output terminal, suitable for during the clock signal is the second logical value, the output data of the first output end of the d type flip flop and second output terminal is latched, first logical value is opposite with the second logical value logic.The operating rate of d type flip flop can be improved using said program.
Description
Technical field
The present invention relates to electronic circuit technology fields, and in particular to a kind of d type flip flop.
Background technology
D type flip flop is in ultra-large integrated (Very Large Scale Integration, VLSI) circuit using very
Extensively, the performance for improving d type flip flop is one of entire most important task of VLSI circuit performances of enhancing.
In practical applications, operating rate is the most important parameter index of d type flip flop.Traditional master-slave D flip-flop by
In with very high anti-interference ability, circuit job stability is high, is widely used in VLSI circuits.But this master-slave type
The operating rate of d type flip flop is slower, cannot be satisfied the requirement to operating rate.
Invention content
Present invention solves the technical problem that being how to improve the operating rate of d type flip flop.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of d type flip flop, including：It is coupled with data input pin
Main latch, and with the main latch coupling slave latch；It is described to include from latch：With the d type flip flop
The first switch of one output end coupling, suitable for being connected during clock signal is in the first logical value, by the main latch
Output data is exported to the first output end of the d type flip flop；The second switch coupled with the d type flip flop second output terminal,
It, will be opposite with the output data logic of the main latch suitable for being connected during the clock signal is in the first logical value
Data are exported to the second output terminal of the d type flip flop；It is coupled respectively with the first output end of the d type flip flop and second output terminal
Latch cicuit, be suitable for the clock signal be the second logical value during, it is defeated to the first output end of the d type flip flop and second
The output data of outlet is latched, and first logical value is opposite with the second logical value logic.
Optionally, first logic device is 1, and second logical value is 0.
Optionally, at least one of the first switch and second switch are made of single transistor.
Optionally, the first switch is the first NMOS tube, the grid and clock signal output terminal of first NMOS tube
Coupling, source electrode are coupled with the main latch, and drain electrode is coupled with the first output end of the d type flip flop.
Optionally, the second switch is the second NMOS tube, the grid and clock signal output terminal of second NMOS tube
Coupling, source electrode are coupled with the main latch, and drain electrode is coupled with the d type flip flop second output terminal.
Optionally, the main latch includes：Third switchs, the first phase inverter, the 4th switch and the second phase inverter,
In, the third switch is coupled with the data input pin, suitable for being closed when the clock signal is in the second logical value,
It is disconnected when the clock signal is in the first logical value；First phase inverter is connected with third switch, is suitable in institute
When stating third switch and being closed, the output end of data transmission that the data input pin is inputted to the main latch；Described
Four switches and second inverter series, and it is in parallel with first phase inverter, it is suitable for being in first in the clock signal
It is closed when logical value, is disconnected when the clock signal is in the second logical value；The input terminal of second phase inverter with it is described
The output end of first phase inverter couples, and output end is coupled with the 4th switch, is suitable for when the 4th switch is closed, to institute
The data for stating the output end of main latch are latched.
Optionally, the source electrode of second NMOS tube and the output end of second phase inverter couple.
Optionally, the output end coupling of the source electrode Yu the main latch of first NMOS tube.
Optionally, the latch cicuit includes：The third phase inverter and the 4th phase inverter of cross-coupled.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that：
Using the above scheme, during the clock signal is in the first logical value, the output number with the main latch
It is directly exported to the second output terminal of d type flip flop by second switch according to the opposite data of logic, and phase inverter need not be passed through again
It could export to the second output terminal of d type flip flop, so as to shorten the delay time of data transmission, improve the work of d type flip flop
Make speed.
Further, at least one of described first switch and second switch are operated alone by the clock signal, it can
To reduce the quantity of the transistor of clock signal driving, so as to reduce since clock signal logic converts consumed work(
Consumption, can also reduce the overall power of d type flip flop, and can simplify the circuit structure from latch, it is easier to which circuit is real
It is existing.
Description of the drawings
Fig. 1 is a kind of electrical block diagram of d type flip flop；
Fig. 2 is a kind of electrical block diagram of d type flip flop provided in an embodiment of the present invention；
Fig. 3 is the d type flip flop data transmission contrast schematic diagram in d type flip flop and Fig. 2 in Fig. 1；
Fig. 4 is the contrast schematic diagram of power consumption between d type flip flop in d type flip flop and Fig. 2 in Fig. 1.
Specific implementation mode
Fig. 1 is a kind of structural schematic diagram of d type flip flop 10.Referring to Fig.1, the d type flip flop 10 may include：Main latch
11 and from latch 12.Wherein, main latch 11 may include：Switch T1, switch T2, phase inverter I2 and phase inverter I3.From lock
Storage 12 may include：Switch T3, switch T4, phase inverter I4 and phase inverter I5.Main latch 11 is low level latch, that is, is existed
Latch in pellucidity when low level.It is high level latch from latch 12, i.e., is in transparence in high level
The latch of state.CLK signal is clock signal, and CLKB signals are the inverted signals of clock signal.Switch T1~T4 is by bicrystal
Pipe is constituted, and each transistor is directly or indirectly driven by clock signal clk.
Specifically, when clock signal clk is low level, main latch 11 is transparent, and input data D is by switch T1 and instead
The opposite data DB of phase device I2 outputs logic.Be in latch mode from latch 12 at this time, the output end Q of entire d type flip flop 10 and
QB carried out logic state holding for the output data in a upper period.
When clock signal clk is reversed to high level by low level, main latch 11 is in latch mode, to output data
DB is kept, and is in pellucidity from latch 12, data DB is transferred to Q by switch T3 and phase inverter I4, to complete
Transmission of the data D to data Q.It is defeated only in the rising edge of clock signal clk in the whole work process of the trigger
The logic state of input data D can just be followed and change by going out the value of data Q.
As can be seen that the transmission delay of d type flip flop 10 is a transmission gate T3 and one from circuit structure shown in FIG. 1
In the sum of the propagation delay time of phase inverter I4, cause the operating rate of d type flip flop 10 slower.
In view of the above-mentioned problems, an embodiment of the present invention provides a kind of d type flip flop, the first logic is in the clock signal
During value, the data opposite with the output data logic of the main latch are directly exported by second switch to d type flip flop
Second output terminal, and could need not be exported to the second output terminal of d type flip flop by phase inverter again, it is passed so as to shorten data
Defeated delay time improves the operating rate of d type flip flop.
It is understandable to enable above-mentioned purpose, feature and the advantageous effect of the present invention to become apparent, below in conjunction with the accompanying drawings to this
The specific embodiment of invention explains in detail.
With reference to Fig. 2, an embodiment of the present invention provides a kind of d type flip flop 20, the d type flip flop 20 may include：With data
The main latch 21 of input terminal coupling, and the slave latch 22 with the coupling of the main latch 21.
Wherein, described to may include from latch 22：
The first switch N1 coupled with 20 first output end QB of the d type flip flop, suitable for being in the clock signal clk
It is connected during first logical value, the output data DB of the main latch 21 is exported to the first output of the d type flip flop 20
Hold QB；
With the second switch N2 of 20 second output terminal Q couplings of the d type flip flop, it is suitable for being in first in the clock signal
It is connected during logical value, the data n1 opposite with the output data logic of the main latch 21 is exported to the d type flip flop
20 second output terminal Q；
Respectively with 20 first output end QB of the d type flip flop and the latch cicuit 221 of second output terminal Q couplings, it is suitable for
During the clock signal clk is the second logical value, to the defeated of the d type flip flop 20 first output end QB and second output terminal Q
Go out data to be latched.
In above-mentioned d type flip flop 20, during being the first logical value due to clock signal clk, the output number of main latch 21
According to after second switch N2, you can output to 20 second output terminal Q of d type flip flop, data transfer delay are the biography of second switch N2
Defeated delay, it is possible thereby to improve the operating rate of d type flip flop 20.
In specific implementation, first logical value is opposite with the second logical value logic.For example, patrolling when described first
Volume value for 0 when, second logical value can be 1, when first logical value be 1 when, second logical value can be 0.
Specifically can according to d type flip flop 20 and sequential relationship in integrated circuits between other circuits be configured.
In specific implementation, due to the setting of latch cicuit 221, first switch N1 can be made up and second switch N2 is being passed
Threshold value loss when transmission of data is high level, therefore in an embodiment of the present invention, the first switch N1 and second switch N2 can
To be the switch being made of single transistor, i.e., by single clock signal drive switch, relative to shown in Fig. 1 from latch
Device 12, clock signal clk institute driving element quantity are reduced, so as to reduce by the caused work(of clock signal logic conversion
Consumption.And since first switch N1 and second switch N2 number of transistors are reduced, the structure of first switch N1 and second switch N2
Simplify, is also decreased from the power consumption of latch 12.
In specific implementation, the switch of various structures may be used in the first switch N1 and second switch N2, specifically not
It is restricted, and the structure of the first switch N1 and second switch N2 may be the same or different, as long as can be in clock
It is opened or closed under the control of signal CLK.For example, first switch N1 and second switch N2 can be ambipolar three pole
It manages (Bipolar Junction Transistor, BJT), can also be insulated gate bipolar transistor (Insulated
Gate Bipolar Transistor, IGBT), can also be metal-oxide-semiconductor.
In one embodiment of this invention, the first switch N1 can be the first NMOS tube, first NMOS tube
Grid is coupled with clock signal clk output end, and source electrode is coupled with the main latch 21, drain electrode and the d type flip flop 20 first
Output end QB couplings.
In one embodiment of this invention, the second switch N2 can be the second NMOS tube, second NMOS tube
The grid of N2 is coupled with clock signal clk output end, and source electrode is coupled with the main latch 21, drain electrode and the d type flip flop 20
Second output terminal Q couplings.
In specific implementation, the structure of the main latch 21 may exist a variety of, as long as can be in clock signal
During second logical value, data D is transmitted to the output end of main latch 21.
In one embodiment of this invention, the main latch 21 may include：Third switch T1, the first phase inverter I2,
4th switch T2 and the second phase inverter I3.Wherein：
The third switch T1 is coupled with the data input pin, is suitable for being in the second logic in the clock signal clk
It is closed when value, is disconnected when the clock signal clk is in the first logical value；
The first phase inverter I2 connects with the third switch T1, is suitable for when the third switch T1 is closed, by institute
The data D for stating data input pin input is transmitted to the output end of the main latch 21；
The 4th switch T2 connects with the second phase inverter I3, and in parallel with the first phase inverter I2, is suitable for
The clock signal clk is closed when being in the first logical value, is disconnected when the clock signal clk is in the second logical value；
The output end of the input terminal of the second phase inverter I3 and the first phase inverter I2 couple, output end and described the
Four switch T2 couplings, are suitable for when the 4th switch T2 is closed, are carried out to the data DB of the output end of the main latch 21
It latches.
In specific implementation, the source electrode of the second NMOS tube N2 can be with the output end coupling of the second phase inverter I3
It connects.The source electrode of the first NMOS tube N1 can be coupled with the output end of the main latch 21.
In specific implementation, the latch cicuit 221 may exist a variety of circuit structures, as long as can be in clock signal
During CLK is in the second logical value, the output data of the first output end QB and second output terminal Q is latched.
In one embodiment of this invention, the latch cicuit 221 may include：The third phase inverter I4 of cross-coupled and
4th phase inverter I5.Third phase inverter I4 and the 4th phase inverter I5 from the connection type in latch 22 there may be a variety of.
For example, the input terminal of the third phase inverter I4 can be coupled with the first output end QB, output end can be with second
Output end Q couplings.Correspondingly, the input terminal of the 4th phase inverter I5 can be coupled with second output terminal Q, and output end can be with
First output end QB couplings.
For another example, the input terminal of the third phase inverter I4 can be coupled with second output terminal Q, output end can with it is first defeated
Outlet QB couplings.Correspondingly, the input terminal of the 4th phase inverter I5 can be coupled with the first output end QB, and output end can be with
Second output terminal Q couplings.
With reference to Fig. 2, when clock signal clk is low level, main latch 21 is in pellucidity, and input data D passes through
Third switch T1 and the first phase inverter I2, the output data DB opposite with input data D logics.First switch N1 and second at this time
Switch N2 is disconnected, and is disconnected from latch 22 and main latch 21, the output of the output end Q and QB of d type flip flop 20 to a upper period
Data carry out logic state holding.
When clock signal clk becomes the rising edge arrival of high level, i.e. clock signal clk from low level, main latch
21 are changed into latch mode, the T1 shutdowns of third switch by pellucidity, and the 4th switch T2 is opened, the output data of main latch 21
DB keeps stablizing by the 4th switch T2, the first phase inverter I2 and the second phase inverter I3, and output data DB is used as from latch 22
Input data be input to from latch 22.Correspondingly, it is changed into pellucidity from latch 22 by latch mode, first opens
N1 and second switch N2 openings are closed, it is defeated that data DB and data n1 are transferred to first by first switch N1 and second switch N2 respectively
Outlet QB and second output terminal Q, to complete data D to data Q transmission.
After clock signal clk stabilizes to high level, main latch 21 is in latch mode, when to clock CLK rising edges
The output data DB at quarter latch and as the input data from latch 22.And it is in pellucidity from latch 22, it is right
The latch data of main latch 21 is responded.
During clock signal clk becomes low level from high level, i.e., when the failing edge of clock signal clk arrives,
It is disconnected from latch 22 and main latch 21, is changed into latch mode from latch 21, passes through the first output end of latch cicuit pair
The output data of QB and second output terminal Q are latched.Main latch 21 reenters pellucidity, is carried out to input data D
Response.
It can thus be seen that in above-mentioned d type flip flop 20, when the rising edge of clock signal arrives, from 22 meeting of latch
Input data D is responded so that the output data of the first output end QB and second output terminal Q follows the change of input data D
Change and change, remaining moment circuit is in latch mode, and d type flip flop is a positive edge master-slave D flip-flop at this time.
Relative to d type flip flop 10 shown in Fig. 1, using the circuit structure from latch 22, data on the one hand can be made
Transmission delay shortens to delay of the NMOS tube as transmission gate from T (delay)=T (T3)+T (I4), in clock signal clk
It is effective along arrive when, data DB and n1 respectively by first switch N1 and second switch N2 i.e. reach corresponding output end into
Row output, improves the operating rate of d type flip flop 20.On the other hand, the quantity of the transistor of clock signal clk driving is by tradition
8 be reduced to 6, to reduce due to clock convert caused by power consumption, and due to structure simplify, transistor totality
Number is reduced, and circuit power consumption can also decrease.
Fig. 3 is the data transmission contrast schematic diagram between d type flip flop 20 in d type flip flop 10 and Fig. 2 in Fig. 1.Wherein, V
(CLK) curve changed over time for the voltage of clock signal, V (D) are the curve that the voltage of input data D changes over time, V
(Q1) curve changed over time for the second output terminal voltage of d type flip flop 10, V (Q2) are the second output terminal of d type flip flop 20
The curve that changes over time of voltage.From figure 3, it can be seen that the data transfer delay of d type flip flop 20 is much smaller than d type flip flop 10
Data transfer delay.
Fig. 4 is the contrast schematic diagram of power consumption between d type flip flop 20 in the d type flip flop 10 in Fig. 1 and Fig. 2.Wherein, P1 D
For the power consumption of trigger 10 with the change curve of working frequency, P2 is the power consumption of d type flip flop 20 with the change curve of working frequency.From
Fig. 4 can be seen that under same working frequency, and the value of P1 is typically larger than the value of P2, and the difference between P1 and P2 is about
13%.Therefore power consumption can effectively be reduced using d type flip flop 20.
It is understood that above-mentioned d type flip flop 10 can be applied in a variety of integrated circuits, it is not restricted specifically, such as SAR
ADC.It is specific no matter to be applied in which kind of circuit structure, do not constitute the limitation to the embodiment of the present invention, and the present invention's
Within protection domain.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (9)
1. a kind of d type flip flop, which is characterized in that including：With data input pin coupling main latch, and with the main latch
The slave latch of device coupling；It is described to include from latch：
The first switch coupled with the first output end of the d type flip flop, suitable for being led during clock signal is in the first logical value
It is logical, the output data of the main latch is exported to the first output end of the d type flip flop；
With the second switch of d type flip flop second output terminal coupling, it is suitable for being in for the first logical value phase in the clock signal
Between be connected, the data opposite with the output data logic of the main latch are exported to the second output terminal of the d type flip flop；
The latch cicuit coupled respectively with the first output end of the d type flip flop and second output terminal, is suitable in the clock signal
During the second logical value, to be latched to the output data of the first output end of the d type flip flop and second output terminal, described
One logical value is opposite with the second logical value logic.
2. d type flip flop as described in claim 1, which is characterized in that first logic device is 1, and second logical value is
0。
3. d type flip flop as claimed in claim 2, which is characterized in that at least one of the first switch and second switch
It is made of single transistor.
4. d type flip flop as claimed in claim 3, which is characterized in that the first switch be the first NMOS tube, described first
The grid of NMOS tube is coupled with clock signal output terminal, and source electrode is coupled with the main latch, drain electrode and the d type flip flop first
Output end couples.
5. d type flip flop as claimed in claim 4, which is characterized in that the second switch be the second NMOS tube, described second
The grid of NMOS tube is coupled with clock signal output terminal, and source electrode is coupled with the main latch, drain electrode and the d type flip flop second
Output end couples.
6. d type flip flop as claimed in claim 5, which is characterized in that the main latch includes：Third switchs, the first reverse phase
Device, the 4th switch and the second phase inverter, wherein
The third switch, couples with the data input pin, suitable for being closed when the clock signal is in the second logical value,
It is disconnected when the clock signal is in the first logical value；
First phase inverter is connected with third switch, is suitable for, when the third is switched and is closed, the data being inputted
Hold the data transmission of input to the output end of the main latch；
4th switch and second inverter series, and it is in parallel with first phase inverter, it is suitable for believing in the clock
Number be in the first logical value when be closed, disconnected when the clock signal is in the second logical value；
The input terminal of second phase inverter and the output end of first phase inverter couple, and output end switchs coupling with the described 4th
It connects, is suitable for, when the 4th switch is closed, latching the data of the output end of the main latch.
7. d type flip flop as claimed in claim 6, which is characterized in that the source electrode of second NMOS tube and second reverse phase
The output end of device couples.
8. d type flip flop as claimed in claim 6, which is characterized in that the source electrode of first NMOS tube and the main latch
Output end coupling.
9. such as claim 1~8 any one of them d type flip flop, which is characterized in that the latch cicuit includes：Cross-coupled
Third phase inverter and the 4th phase inverter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710117126.0A CN108540110A (en) | 2017-03-01 | 2017-03-01 | D type flip flop |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710117126.0A CN108540110A (en) | 2017-03-01 | 2017-03-01 | D type flip flop |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108540110A true CN108540110A (en) | 2018-09-14 |
Family
ID=63488364
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710117126.0A Pending CN108540110A (en) | 2017-03-01 | 2017-03-01 | D type flip flop |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108540110A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110995206A (en) * | 2019-12-13 | 2020-04-10 | 海光信息技术有限公司 | Flip-flop circuit |
| CN113556102A (en) * | 2021-07-21 | 2021-10-26 | 昂赛微电子（上海）有限公司 | Asynchronous reset D flip-flop |
| CN115085718A (en) * | 2022-08-22 | 2022-09-20 | 上海韬润半导体有限公司 | Data selector |
| WO2023249966A1 (en) * | 2022-06-21 | 2023-12-28 | Sehat Sutardja | Ultra-low power d flip-flop with reduced clock load |
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| CN1439196A (en) * | 2000-12-15 | 2003-08-27 | 皇家菲利浦电子有限公司 | Pulsed D-flip-flop using differential cascode switch |
| WO2008095997A1 (en) * | 2007-02-08 | 2008-08-14 | Texas Instruments Deutschland Gmbh | Complementary output flip-flop |
| CN101431320A (en) * | 2007-11-08 | 2009-05-13 | 中芯国际集成电路制造(上海)有限公司 | High-stability D trigger structure |
| WO2015005992A1 (en) * | 2013-07-09 | 2015-01-15 | Raytheon Company | Fully differential symmetrical high speed static cmos flip flop circuit |
| CN104617925A (en) * | 2013-11-01 | 2015-05-13 | 恩智浦有限公司 | Latch circuit |
| CN105450201A (en) * | 2014-09-23 | 2016-03-30 | 恩智浦有限公司 | Fault resistant flip-flop |
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| CN1439196A (en) * | 2000-12-15 | 2003-08-27 | 皇家菲利浦电子有限公司 | Pulsed D-flip-flop using differential cascode switch |
| WO2008095997A1 (en) * | 2007-02-08 | 2008-08-14 | Texas Instruments Deutschland Gmbh | Complementary output flip-flop |
| CN101431320A (en) * | 2007-11-08 | 2009-05-13 | 中芯国际集成电路制造(上海)有限公司 | High-stability D trigger structure |
| WO2015005992A1 (en) * | 2013-07-09 | 2015-01-15 | Raytheon Company | Fully differential symmetrical high speed static cmos flip flop circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110995206A (en) * | 2019-12-13 | 2020-04-10 | 海光信息技术有限公司 | Flip-flop circuit |
| CN113556102A (en) * | 2021-07-21 | 2021-10-26 | 昂赛微电子（上海）有限公司 | Asynchronous reset D flip-flop |
| WO2023249966A1 (en) * | 2022-06-21 | 2023-12-28 | Sehat Sutardja | Ultra-low power d flip-flop with reduced clock load |
| CN115085718A (en) * | 2022-08-22 | 2022-09-20 | 上海韬润半导体有限公司 | Data selector |
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