CN115085718A

CN115085718A - Data selector

Info

Publication number: CN115085718A
Application number: CN202211002592.1A
Authority: CN
Inventors: 李闻界; 管逸
Original assignee: Shanghai Taorun Semiconductor Co ltd
Current assignee: Shanghai Taorun Semiconductor Co ltd
Priority date: 2022-08-22
Filing date: 2022-08-22
Publication date: 2022-09-20

Abstract

The present invention relates to a data selector which selects one of a first signal and a second signal input to the data selector according to a selection signal and outputs the selected signal. The data selector may include a selection stage and an inversion stage. The selection stage may include a first transmission gate disposed on an input line of the first signal and a second transmission gate disposed on an input line of the second signal, each transmission gate including an inverter and a MOS transistor selection switch. The MOS tube selection switch enables the inverter of one transmission gate of the first transmission gate and the second transmission gate to be in a conducting state and the inverter of the other transmission gate to be in a disconnecting state according to the selection signal, wherein the output end of the inverter of the first transmission gate and the output end of the inverter of the second transmission gate are connected and are connected to the output end of the selection stage. The inverting stage may be adapted to invert the signal input thereto.

Description

Data selector

Technical Field

The present invention relates to the field of electronic circuits, and more particularly, to a data selector.

Background

The current data selector has the problems of more logic circuits and more complexity, and therefore, the transmission delay, the power consumption, the noise and other related transmission quality are influenced. Taking the conventional alternative data selector of fig. 1 as an example, it generally consists of an and gate, an or gate, and an inverter. The logistic function expression of the data selector may be represented as Y = a SEL + B (— SEL). In fig. 1, when the selection signal SEL is 1, the output F = B; when the selection signal SEL is 0, F = a is output. Therefore, the data selector in fig. 1 completes the selection of the data input signal according to the selection signal, and the data input signal needs to pass through at least two stages of logic circuits from input to output, so that the transmission properties such as transmission delay, power consumption, noise and the like are less ideal.

Disclosure of Invention

In view of the above, the present invention aims to provide a data selector.

A data selector of an aspect of the present invention selects one of a first signal and a second signal input to the data selector according to a selection signal and outputs the selected signal. The data selector may include a selection stage and an inversion stage. The selection stage may include a first transmission gate disposed on an input line of the first signal and a second transmission gate disposed on an input line of the second signal, each transmission gate including an inverter and a MOS transistor selection switch. The MOS tube selection switch enables the inverter of one transmission gate of the first transmission gate and the second transmission gate to be in a conducting state and the inverter of the other transmission gate to be in a disconnecting state according to the selection signal, wherein the output end of the inverter of the first transmission gate and the output end of the inverter of the second transmission gate are connected and are connected to the output end of the selection stage. The inverting stage may be adapted to invert the signal input thereto.

Optionally, the inverter comprises a CMOS inverter.

Alternatively, the MOS transistor selection switch may include an NMOS transistor selection switch and a PMOS transistor selection switch. The source electrode of the PMOS tube selection switch is connected with the drain electrode of the PMOS tube of the CMOS phase inverter, and the drain electrode of the PMOS tube selection switch is connected with the output end of the CMOS phase inverter. The drain electrode of the NMOS tube selection switch is connected with the output end of the CMOS phase inverter, and the source electrode of the NMOS tube selection switch is connected with the drain electrode of the NMOS tube of the CMOS phase inverter. In the first transmission gate, the grid of the PMOS tube selection switch is connected with a selection signal, and the grid of the NMOS tube selection switch is connected with an inverted signal of the selection signal. In the second transmission gate, the grid of the PMOS tube selection switch is connected with the inverted signal of the selection signal, and the grid of the NMOS tube selection switch is connected with the selection signal.

Alternatively, the inverting stage may comprise an inverter, an input of the inverter being connected to the output of the selection stage, an output of the inverter being the output of the data selector.

Optionally, the inverting stage may comprise a first inverter and a second inverter. The first inverter has an input terminal receiving the first signal and an output terminal connected to an input terminal of the first transmission gate. The input end of the second inverter receives the second signal, and the output end of the second inverter is connected to the input end of the second transmission gate.

Optionally, the inverting stage may include a third transmission gate and a fourth transmission gate. The third transmission gate multiplexes the first transmission gate and is connected between the output terminal of the first transmission gate and the output terminal of the selection stage. The fourth transmission gate multiplexes the second transmission gate and is connected between the output terminal of the second transmission gate and the output terminal of the selection stage.

Optionally, the data selector may further comprise one or more latches. The one or more latches are used to latch or transmit one or more of the first signal, the second signal, and the selected signal in accordance with the control signal.

Optionally, the latch may include a first CMOS transmission gate, a second CMOS transmission gate, a first inverter, and a second inverter. The input end of the latch is connected with the first end of the first CMOS transmission gate, the second end of the first CMOS transmission gate is connected with the input end of the first phase inverter, the output end of the first phase inverter is connected with the input end of the second phase inverter, the output end of the second phase inverter is connected with the first end of the second CMOS transmission gate, and the second end of the second CMOS transmission gate is connected back to the second end of the first CMOS transmission gate. And a connecting line between the output end of the first inverter and the input end of the second inverter is connected with the output end of the latch. The grid electrode of the PMOS tube of the first CMOS transmission gate is connected with the control signal, the grid electrode of the NMOS tube is connected with the inverted signal of the control signal, the grid electrode of the NMOS tube of the second CMOS transmission gate is connected with the control signal, and the grid electrode of the PMOS tube is connected with the inverted signal of the control signal.

Alternatively, the latch may include a first latch and a second latch. The input end of the first latch receives the first signal, and the output end of the first latch is connected with the input end of the first transmission gate. The input end of the second latch receives the second signal, and the output end of the second latch is connected with the input end of the second transmission gate.

Optionally, the latch may further comprise a third inverter. The input end of the third inverter is connected with the output end of the first inverter and the input end of the second inverter, and the output end of the third inverter is connected with the output end of the latch.

Alternatively, the input of the latch may be connected to the output of the selection stage, and the output of the latch may be the output of the data selector.

As described above, according to the data selector of the present invention, by providing fewer logic circuits and using the transmission gate design of the MOS process, the data selector of the present invention has a lower transmission delay and is more desirable in terms of transmission power consumption, noise, and other properties. In addition, the data selector of the invention can also have the function of data latching.

Drawings

Fig. 1 is a block diagram of a conventional alternative data selector.

Fig. 2 is a schematic structural diagram of a transmission gate according to an embodiment of the present invention.

Fig. 3A-3B are schematic diagrams of two configurations of a data selector according to an embodiment of the invention.

Fig. 4A is a schematic structural diagram of another data selector according to an embodiment of the present invention.

Fig. 4B is a graph comparing experimental results of waveform simulation of the data selector of fig. 4A and 1.

Fig. 5A-5B are schematic diagrams of two structures of a data selector with data latch function according to an embodiment of the invention.

Fig. 5C is a schematic diagram of the structure of the latch shown in fig. 5A-5B.

FIG. 5D is a schematic diagram of a latch according to another embodiment of the invention.

Detailed Description

The following description is of some of the several embodiments of the invention and is intended to provide a basic understanding of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention.

For the purposes of brevity and explanation, the principles of the present invention are described herein with reference primarily to exemplary embodiments thereof. However, those skilled in the art will readily recognize that the same principles are equally applicable to all types of data selectors and that these same principles may be implemented therein, as well as any such variations, without departing from the true spirit and scope of the present patent application.

Moreover, in the following description, reference is made to the accompanying drawings that illustrate certain exemplary embodiments. Electrical, mechanical, logical, and structural changes may be made to these embodiments without departing from the spirit and scope of the invention. In addition, while a feature of the invention may have been disclosed with respect to only one of several implementations/embodiments, such feature may be combined with one or more other features of the other implementations/embodiments as may be desired and/or advantageous for any given or identified function. The following description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims and their equivalents.

Terms such as "comprising" and "comprises" mean that, in addition to having elements (modules) and steps that are directly and explicitly stated in the description and claims, the solution of the invention does not exclude the presence of other elements (modules) and steps that are not directly or explicitly stated.

The data selector of the present invention may select between the first signal and the second signal input to the data selector in accordance with the selection signal SEL and output the selected signal (the first signal or the second signal), for example, when SEL =1 (i.e., the selection signal is at a low level), the data selector selects and outputs the first signal, and when SEL =0 (i.e., the selection signal is at a high level), the data selector selects and outputs the second signal.

The data selector may include a selection stage and an inversion stage. The selection stage comprises a first transmission gate arranged on the first signal input line and a second transmission gate arranged on the second signal input line, each transmission gate respectively comprises an inverter and a MOS tube selection switch, the MOS tube selection switch enables the inverter of one transmission gate of the first transmission gate and the second transmission gate to be in a conducting state and enables the inverter of the other transmission gate to be in a disconnecting state according to a selection signal, wherein the output end of the inverter of the first transmission gate and the output end of the inverter of the second transmission gate are connected and are connected to the output end of the selection stage.

Specifically, the input and output terminals of the inverters constitute the input and output terminals of the transmission gate, the first signal and the second signal can be input to the corresponding inverter, and the selection signal controls whether the corresponding inverter is turned on by controlling the MOS transistor selection switch (for example, connected to the gate of the MOS transistor used as the switch). One of the two transmission gates can be turned on and the other turned off (or nearly turned off, e.g., by placing the MOS transistors in a high impedance state) by configuring the select signal. For example, when the selection signal SEL =1, the inverter of the first transmission gate is turned on and the inverter of the second transmission gate is turned off to normally transmit the first signal out; when the selection signal SEL =0, the inverter of the second transmission gate is turned on and the inverter of the first transmission gate is turned off to normally transmit the second signal out. This can be achieved by various selection signal access methods, for example, the selection signal access methods of the first transmission gate and the second transmission gate may be opposite, so that one input (0 or 1) of two inputs of the selection signal only conducts one transmission gate, and the other input of the two inputs only conducts the other transmission gate.

As is apparent from the above description, the signal passing through the transmission gate is an inverted signal of the original signal, and therefore, an inverting stage may be further provided for inverting the signal inputted thereto to restore the phase of the selected signal. It will thus be appreciated that an inverting stage may be provided before the selection stage for inverting the first and second signals before being input to the selection stage for selection; the inverting stage may be disposed after the selection stage for inverting the selected first signal or second signal.

Compared with the existing alternative data selector shown in fig. 1, the structure of the selection stage plus the inversion stage is only provided with a two-stage inversion device structure, the logic circuit is less and simpler to set, transmission delay, noise, power consumption and the like caused by the structure of the data selector can be effectively reduced, and the data selector is suitable for being applied to high-speed and low-power-consumption circuits.

It should be noted that the inverting stage or inverter that performs the inverting function above may be any form of inverting device, such as a CMOS inverter, a TTL inverter, or the like. In the embodiment of the present invention, an inversion system such as an inverter using a CMOS inverter as a transfer gate or an inversion stage of a data selector, a data latch structure for inverting a transfer signal, and multiplexing a transfer gate again as an inversion stage is specifically mentioned, but it is understood that the present invention is not limited thereto.

Fig. 2 shows a specific structure of a preferred transmission gate according to an embodiment of the present invention. As shown in fig. 2, the transmission gate can be considered to be composed of a CMOS inverter and a MOS transistor switch. The CMOS inverter gate comprises an NMOS transistor and a PMOS transistor, wherein the source electrode of the PMOS transistor is connected with a working voltage V _DD The drain electrode is connected with the drain electrode of the NMOS tube, and the source electrode of the NMOS tube is grounded. The NMOS transistor and the PMOS transistor share a grid electrode and serve as an input end of the CMOS inverter, and a common drain electrode of the NMOS transistor serves as an output end of the CMOS inverter.

In fig. 2, two MOS transistors are inserted on the basis of the CMOS inverter as selection switches controlled by selection signals, and the two MOS transistor selection switches include an NMOS transistor selection switch and a PMOS transistor selection switch. The source electrode of the PMOS tube selection switch is connected with the drain electrode of a PMOS tube of the CMOS phase inverter, and the drain electrode of the PMOS tube selection switch is connected with the output end of the CMOS phase inverter; the drain electrode of the NMOS tube selection switch is connected with the output end of the CMOS phase inverter, and the source electrode of the NMOS tube selection switch is connected with the drain electrode of the NMOS tube of the CMOS phase inverter. In the first transmission gate, the gate of the NMOS tube selection switch is connected with a selection signal SEL, and the gate of the PMOS tube selection switch is connected with an inverted signal SELN of the selection signal SEL. In the second transmission gate, the gate of the NMOS transistor selection switch is connected to the inverted signal SELN of the selection signal, and the gate of the PMOS transistor selection switch is connected to the selection signal SEL.

The input end D is connected to the common gate of the NMOS transistor and the PMOS transistor of the CMOS inverter, and the gates of the two MOS transistor switches are respectively connected to input signals CKP and CKN, wherein the phases of CKP and CKN are opposite (for example, CKN can be a signal obtained by CKP through the CMOS inverter). Therefore, the original CMOS inverter can be normally connected into the circuit through gating the two MOS tube switches, so that the input signal of the input end D is inverted and output to the output end OUT. Specifically, when CKN =1 and CKP =0, the output OUT is the inverse of D, i.e., the output OUT is the inverse of D

The transmission gate can normally function as a CMOS inverter. When CKN =0 and CKP =1, the transmission gate exhibits a high impedance state, which corresponds to the two MOS switches connected to the CMOS inverter being turned off, and thus the CMOS inverter is also in the off state. Therefore, the connection or disconnection of the transmission gate can be realized through the gate input control of the two MOS tube switches, and any one of CKN and CKP can be connected with a selection signal SEL. For example, CKN of the first transmission gate in fig. 2 is connected to the selection signal SEL, while CKP is connected to the inverted signal SELN of the selection signal SEL; CKN of the second transmission gate is connected to SELN, while CKP is connected to SEL.

The CMOS phase inverter also utilizes the MOS tube process, can be integrated with the MOS tube selection switch more favorably, ensures that the signal transmission of a selection stage only needs to pass through a corresponding circuit of the MOS tube, and can further reduce the transmission delay and improve the transmission quality compared with the existing selector comprising a multi-stage logic gate.

Fig. 3A-3B are schematic diagrams of two configurations of a data selector 300 according to an embodiment of the invention. Block 301 in fig. 3A-3B is the transmission gate of fig. 2, the input of the transmission gate 301 is the input D in fig. 2, the output of the transmission gate 301 is the output OUT in fig. 2, the VDDR terminal represents the operating voltage to which the CMOS inverter of the transmission gate 301 is connected, and the AVSS terminal represents the ground terminal of the CMOS inverter of the transmission gate 301. One transmission gate 301 receives a first signal input and the other transmission gate 301 receives a second signal input.

As can be seen from fig. 3A-3B, the select signal SEL is connected to the CKN terminal in one of the transmission gates 301 (so the inverse SELN of the select signal SEL is connected to its CKP terminal), and to the CKP terminal in the other transmission gate 301 (so the inverse SELN of the select signal SEL is connected to its CKN terminal). Therefore, when SEL is high, SELN is low, and/or when SEL is low, SELN is high, only one of the two transmission gates 301 is in a normally on state (i.e., having the CMOS inverter therein turned on to function as a normal inversion) and the other is in a high impedance state (i.e., an off state). Thus, the first signal and the second signal can be selected according to the selection signal SEL and output to the output terminal of the data selector 300.

It will be appreciated that the signal passing through the transmission gate 301 is an inverted version of the original signal, and therefore an inverter is required to restore the original phase of the signal. Thus, the inverters can be arranged in two ways (i.e., fig. 3A and 3B), where fig. 3A and 3B differ in the arrangement point of the inverter 302, one inverter in fig. 3A is arranged on the common output line of the two transmission gates 301, and one inverter is arranged on the input line of each of the two transmission gates 301 in fig. 3B.

The structure of the data selector 300 is simpler, the number of logic circuits is smaller, and fewer logic circuits need to be passed in data transmission, compared to the conventional data selector structure of fig. 1, thereby having lower transmission delay as well as power consumption, noise, and the like.

Fig. 4A is a schematic structural diagram of another data selector 400 according to an embodiment of the present invention, and a transmission gate 401 in the data selector 400 corresponds to the transmission gate 301 in fig. 3A and 3B. It can be seen that the data selector 400 reuses two transmission gates 401 to perform the inverting function, wherein the two transmission gates 401 on the same input line have the same circuit structure, the same components, and the same selection signal connection (i.e., the two transmission gates of the selection stage are multiplexed to form the inverting stage). Thus, it will be appreciated that in the present embodiment, the inverting stage and the selection stage may be used interchangeably, given that the two transmission gates on the same input line are identical. Thus, fig. 4A constitutes a data selector composed of dual edge flip-flops, which also uses a simpler structure and fewer logic circuits to achieve the enhancement of the transmission effect.

The inventors compared the simulation of the data selector 400 of fig. 4A with the conventional data selector of fig. 1, as shown in fig. 4B. It can be seen that the delay in the simulation of the conventional data selector is around 30.1ps, while the transmission delay of the data selector 400 is reduced to around 18.4ps for the same input signal. As can be seen from the simulation results, the data selector of the present invention shows more desirable propagation delay characteristics.

Fig. 5A-5B are schematic diagrams of two structures of a data selector 500 with data latching function according to an embodiment of the present invention. Wherein the transmission gate 501 corresponds to the transmission gate structure as described in fig. 2 or fig. 3, 4. Fig. 5A differs from fig. 5B in the set point of the latch 502, the two latches 502 of fig. 5A being arranged on the input lines of the two transmission gates 501, respectively, and the latches 502 of fig. 5B being arranged on the common output line of the two transmission gates 501, respectively. The latch, which is used to hold the level state on the corresponding line, may be any type of latch and is preferably a latch constructed using CMOS transmission gates. Thus, the data selector of the present invention further has a data latch function, and can store the input state or the output state of the data selector. It will be appreciated that latches may be provided before and after the select stage.

For example, in the structure of fig. 5A, the latch 502 is used to latch (i.e., maintain the level signal state) the first signal and the second signal, and then to select the first signal and the second signal. In the structure of fig. 5B, the first signal and the second signal are selected first, and then the selected signals are latched.

FIG. 5C shows a block diagram of one type of latch. The latch is composed of a first CMOS transmission gate TG1, a second CMOS transmission gate TG2, an inverter I1 and an inverter I2. The control terminal of the CMOS transmission gate may be respectively connected to the control signal CLK and the inverted signal CLKN of the control signal through the inverter. And the control terminals of the first CMOS transmission gate TG1 and the second CMOS transmission gate TG2 are in reverse.

In fig. 5C, when CLK is at high level 1, TG1 is turned on (transmissible) and TG2 is turned off (equivalent to off), and a signal can be output from the input terminal D to the output terminal Q and its inverted signal is output; when CLK is at low level 0, TG2 is turned on (transmissible) and TG1 is turned off (equivalent to being turned off), and the inverted signal output from the last transmission can be fed back to the a terminal through inverters I3 and TG2 at the B terminal, thereby achieving the retention (i.e., latching) of the signal state. Therefore, the latch or transmission function can be realized by the input change of the control signal CLK, and the output is the inversion of the input signal, so that an inverter is not needed to be additionally arranged before and after the transmission gate.

Fig. 5D is a schematic diagram of a latch according to another embodiment of the present invention, which is based on fig. 5C and adds a third inverter I3 at the output terminal. The input of the third inverter I3 is connected to the output of the first inverter I1 and the input of the second inverter I2, and the output of the third inverter I3 is connected to the output of the latch. Thus, the latch latches a signal that is in phase with the input signal. The latch of fig. 5D can be equally applied to the data selector of fig. 5A and 5B, and it can be understood that when the latch of fig. 5D is applied, phase recovery of the output can be realized by only arranging an inverter on the input line or the output line before and after the transmission gate of fig. 5A and 5B (not shown). In addition, two newly added inverters (a third inverter I3 and one inverter arranged on the input line or the output line before and after the transmission gate) can be formed into a pair of buffer structures, so that the buffering and signal driving capabilities are further exerted, and the quality of the selection signal output by the data selector is further optimized.

The above mainly describes the data selector of the present invention. Although only a few embodiments of the present invention have been described in detail, those skilled in the art will appreciate that the present invention may be embodied in many other forms without departing from the spirit or scope thereof. Accordingly, the present examples and embodiments are to be considered as illustrative and not restrictive, and various modifications and substitutions may be made therein without departing from the spirit and scope of the present invention as defined by the appended claims.

Claims

1. A data selector, wherein the data selector selects one of a first signal and a second signal input to the data selector according to a selection signal and outputs the selected signal, the data selector comprising:

a selection stage including a first transmission gate provided on an input line of the first signal and a second transmission gate provided on an input line of the second signal, each transmission gate including an inverter and a MOS transistor selection switch, the MOS transistor selection switch causing the inverter of one of the first transmission gate and the second transmission gate to be in an on state and the inverter of the other transmission gate to be in an off state in accordance with the selection signal, wherein an output terminal of the inverter of the first transmission gate and an output terminal of the inverter of the second transmission gate are connected and are both connected to an output terminal of the selection stage;

and an inverting stage for inverting the signal input thereto.

2. The data selector of claim 1, wherein the inverter comprises a CMOS inverter.

3. The data selector of claim 2,

the MOS tube selection switch comprises an NMOS tube selection switch and a PMOS tube selection switch, wherein,

the source electrode of the PMOS tube selection switch is connected with the drain electrode of the PMOS tube of the CMOS phase inverter, the drain electrode of the PMOS tube selection switch is connected with the output end of the CMOS phase inverter,

the drain electrode of the NMOS tube selection switch is connected with the output end of the CMOS phase inverter, the source electrode of the NMOS tube selection switch is connected with the drain electrode of the NMOS tube of the CMOS phase inverter,

in the first transmission gate, the grid electrode of the PMOS tube selection switch is connected with the selection signal, the grid electrode of the NMOS tube selection switch is connected with the inverted signal of the selection signal,

in the second transmission gate, the grid of the PMOS tube selection switch is connected with the inverted signal of the selection signal, and the grid of the NMOS tube selection switch is connected with the selection signal.

4. The data selector of claim 1, wherein the inverting stage includes an inverter having an input coupled to the output of the selection stage and an output as the output of the data selector.

5. The data selector of claim 1, wherein the inverting stage comprises:

a first inverter having an input terminal receiving the first signal and an output terminal connected to the input terminal of the first transmission gate; and

and the input end of the second inverter receives the second signal, and the output end of the second inverter is connected to the input end of the second transmission gate.

6. The data selector of claim 1, wherein the inverting stage comprises:

a third transmission gate multiplexing the first transmission gate, the third transmission gate being connected between an output of the first transmission gate and an output of the selection stage; and

a fourth transmission gate multiplexing the second transmission gate, the fourth transmission gate connected between the output of the second transmission gate and the output of the selection stage.

7. The data selector of claim 1, wherein the data selector further comprises one or more latches to latch or transfer one or more of the first signal, the second signal, and the selected signal according to a control signal.

8. The data selector of claim 7,

the latch comprises a first CMOS transmission gate, a second CMOS transmission gate, a first phase inverter and a second phase inverter, the input end of the latch is connected with the first end of the first CMOS transmission gate, the second end of the first CMOS transmission gate is connected with the input end of the first phase inverter, the output end of the first phase inverter is connected with the input end of the second phase inverter, the output end of the second phase inverter is connected with the first end of the second CMOS transmission gate, the second end of the second CMOS transmission gate is connected back to the second end of the first CMOS transmission gate,

wherein a connection line between the output end of the first inverter and the input end of the second inverter is connected with the output end of the latch,

and the grid electrode of the PMOS tube of the first CMOS transmission gate is connected with the control signal, the grid electrode of the NMOS tube of the first CMOS transmission gate is connected with the inverted signal of the control signal, the grid electrode of the NMOS tube of the second CMOS transmission gate is connected with the control signal, and the grid electrode of the PMOS tube is connected with the inverted signal of the control signal.

9. The data selector of claim 8, wherein the latch comprises:

a first latch, the input end of which receives the first signal, and the output end of which is connected with the input end of the first transmission gate; and

and the input end of the second latch receives the second signal, and the output end of the second latch is connected with the input end of the second transmission gate.

10. The data selector of claim 7 wherein the latch further comprises a third inverter, an input of the third inverter being connected to the output of the first inverter and the input of the second inverter, an output of the third inverter being connected to the output of the latch.

11. The data selector of claim 7 wherein an input of the latch is connected to an output of the selection stage and an output of the latch is connected as an output of the data selector.