CN111555754B - Metastable state detection circuit applied to synchronous clock sampling of high-speed analog-to-digital converter - Google Patents
Metastable state detection circuit applied to synchronous clock sampling of high-speed analog-to-digital converter Download PDFInfo
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- H—ELECTRICITY
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- H03M1/1071—Measuring or testing
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
Abstract
The invention discloses a metastable state detection circuit applied to synchronous clock sampling of a high-speed analog-to-digital converter, which comprises a D trigger DFF2, a D trigger DFF3 and at least one D trigger DFF, wherein the D end of the D trigger DFF2 is connected with an RCLK signal through a delay circuit, the CLK end of the D trigger DFF3 is connected with an MCLK signal through a delay circuit, the MCLK signal is also input to the CLK end of the D trigger DFF2, and the RCLK signal is also input to the D end of the D trigger DFF 3; the Q end of the D trigger DFF2 is connected with the D end of the D trigger DFF, the Q end of the D trigger DFF3 is connected with the CLK end of the D trigger DFF, and the Q end of the D trigger DFF is used as the output of the metastable state detection circuit; metastable state detection can be carried out without frequency division of a main clock, and the problem of phase discrimination deviation does not exist.
Description
Technical Field
The invention relates to the technical field of integrated circuits and the like, in particular to a metastable state detection circuit applied to synchronous clock sampling of a high-speed analog-to-digital converter.
Background
In practical use, a plurality of chips are often used at the same time in the high-speed ADC, a group of synchronous clocks is required for synchronizing output data and data clocks among the chips, and the synchronous clocks are continuously sampled by a main clock in the chips to realize the synchronization function among the chips.
The synchronous clock frequency is generally 2^N frequency division of a main clock, a situation that a metastable state is sampled may occur when the main clock samples the synchronous clock, because the main clock and the synchronous clock have different frequencies, the conventional solution idea is to firstly frequency-divide 2^N of the main clock to obtain a frequency-divided clock, then the frequency-divided clock and the synchronous clock detect a phase difference through a phase discriminator, and judge whether the sampling is in the metastable state according to the phase difference. This kind of detection mode needs the frequency division circuit, can make two clock phases of input phase discriminator and actual sampling main clock and synchronous clock phase deviation to some extent like this, leads to the phase discrimination deviation, needs to give the great allowance in metastable state judgement area. The phase difference value judging circuit generally receives the phase discriminator after the phase discriminator output passes through RC filtering, and the circuit of this kind uses the device more and more complicated, and signal transmission path is longer, and some logic delay matches will appear great deviation a little, and difficult differentiation to the phase difference of picosecond rank, moreover because the existence of comparator maladjustment can lead to phase detection to have the fixed detection deviation.
Disclosure of Invention
The invention aims to provide a metastable state detection circuit applied to synchronous clock sampling of a high-speed analog-to-digital converter, which can carry out metastable state detection without frequency division of a main clock and has no problem of phase discrimination deviation.
The invention is realized by the following technical scheme: a metastable state detection circuit applied to synchronous clock sampling of a high-speed analog-to-digital converter comprises a D trigger DFF2, a D trigger DFF3 and at least one D trigger DFF, wherein the D end of the D trigger DFF2 is connected with an RCLK signal through a delay circuit, the CLK end of the D trigger DFF3 is also connected with an MCLK signal through a delay circuit, the MCLK signal is also input to the CLK end of the D trigger DFF2, and the RCLK signal is also input to the D end of the D trigger DFF 3; the Q end of the D trigger DFF2 is connected with the D end of the D trigger DFF, the Q end of the D trigger DFF3 is connected with the CLK end of the D trigger DFF, and the Q end of the D trigger DFF is used as the output of the metastable state detection circuit.
In order to further realize the invention, the following arrangement structure is adopted: when the number of the D flip-flops DFF is more than 1, the Q terminal of the previous D flip-flop DFF is connected with the D terminal of the next D flip-flop DFF first, the Q terminal of the last D flip-flop DFF is used as the output of the metastable state detection circuit, the D terminal of the first D flip-flop DFF is connected with the Q terminal of the D flip-flop DFF2, and the CLK terminal of any one D flip-flop DFF is connected with the Q terminal of the D flip-flop DFF 3.
Compared with the prior art, the invention has the following advantages and beneficial effects:
(1) The invention can carry out metastable state detection without frequency division of the main clock and has no phase discrimination deviation problem.
(2) The device used by the invention is completely the same as the device actually sampled, thereby ensuring the consistency of the deviation of the device under each temperature, power supply voltage and process angle and leading the phase discrimination to achieve higher precision.
Drawings
FIG. 1 is a schematic diagram of the connection of MCLK and RCLK when the ADC is in use.
FIG. 2 is a schematic view of the structure of the present invention.
FIG. 3 is a schematic diagram of a sample in the metastable region.
FIG. 4 is a schematic diagram of a sample in the non-metastable region.
Fig. 5 is a schematic diagram of an optimized structure of the present invention.
Detailed Description
The present invention will be described in further detail with reference to examples, but the embodiments of the present invention are not limited thereto.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings of the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like are used in the orientations and positional relationships indicated in the drawings, which are merely for convenience of description and simplicity of description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature "on," "above" and "over" the second feature may include the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
Example 1:
the invention designs a metastable state detection circuit applied to synchronous clock sampling of a high-speed analog-to-digital converter, which can carry out metastable state detection without frequency division of a main clock and has no problem of phase discrimination deviation, and as shown in fig. 2 and fig. 5, the following setting modes are particularly adopted: the digital-to-analog converter comprises a D trigger DFF2, a D trigger DFF3 and at least one D trigger DFF, wherein the D end of the D trigger DFF2 is connected with an RCLK signal through a delay circuit, the CLK end of the D trigger DFF3 is also connected with an MCLK signal through a delay circuit, the MCLK signal is also input to the CLK end of the D trigger DFF2, and the RCLK signal is also input to the D end of the D trigger DFF 3; the Q end of the D trigger DFF2 is connected with the D end of the D trigger DFF, the Q end of the D trigger DFF3 is connected with the CLK end of the D trigger DFF, and the Q end of the D trigger DFF is used as the output of the metastable state detection circuit.
Example 2:
the present embodiment is further optimized based on the above embodiments, and the same parts as the foregoing technical solutions will not be described herein again, as shown in fig. 2 and fig. 5, in order to further implement the present invention, the following setting structure is particularly adopted: when the number of the D flip-flops DFF is more than 1, the Q terminal of the previous D flip-flop DFF is connected with the D terminal of the next D flip-flop DFF first, the Q terminal of the last D flip-flop DFF is used as the output of the metastable state detection circuit, the D terminal of the first D flip-flop DFF is connected with the Q terminal of the D flip-flop DFF2, and the CLK terminal of any one D flip-flop DFF is connected with the Q terminal of the D flip-flop DFF 3.
Example 4:
the embodiment is a practical application of the present invention, as shown in fig. 1 to 5, and includes an analog-to-digital converter ADC1, an analog-to-digital converter ADC2, and an analog-to-digital converter ADC3, which have the same circuit structure, a metastable state detection circuit and a sampling circuit are all present in the analog-to-digital conversion circuit ADC1, the analog-to-digital conversion circuit ADC2, and the analog-to-digital conversion circuit ADC3, an RCOUT1 output of the analog-to-digital converter ADC1 is input as an RCLK signal of the analog-to-digital converter ADC2, an RCOUT2 output of the analog-to-digital converter ADC1 is input as an RCLK signal of the analog-to-digital converter ADC3, and an MCLK output of the analog-to-digital converter ADC1 is simultaneously input as an MCLK signal of the analog-to-digital converter ADC2 and an MCLK signal of the analog-to-digital converter ADC 3.
As a preferred arrangement, the analog-to-digital converter ADC1 serves as a master ADC, and the analog-to-digital converter ADC2 and the analog-to-digital converter ADC3 serve as slave ADCs, when using a chip synchronization function, the analog-to-digital converter ADC1 sends a synchronization clock RCLK to the analog-to-digital converter ADC2 and the analog-to-digital converter ADC3, and after receiving the RCLK from the slave ADC, the slave ADC performs sampling via the MCLK (master clock) to achieve synchronization between chips (master ADC and slave ADC).
The sampling circuit is provided with a D trigger DFF1, the D end of the D trigger DFF1 is used as an RCLK signal access end, the CLK end of the D trigger DFF1 is used as MCLK signal input, the Q end of the D trigger DFF1 is used as CK1 signal output, and the D end and the CLK end of the D trigger DFF1 are both connected with the metastable state detection circuit.
The metastable state detection circuit comprises a D trigger DFF2, a D trigger DFF3 and at least one D trigger DFF, an RCLK signal is input to the D end of the D trigger DFF2 through a delay circuit, an MCLK signal is also input to the CLK end of the D trigger DFF3 through a delay circuit, the MCLK signal is also input to the CLK end of the D trigger DFF2, and the RCLK signal is also input to the D end of the D trigger DFF 3D; the Q end of the D trigger DFF2 is connected with the D end of the D trigger DFF, the Q end of the D trigger DFF3 is connected with the CLK end of the D trigger DFF, and the Q end of the D trigger DFF is used as the output of the metastable state detection circuit.
In order to detect whether the edge of the RCLK signal is sampled when the MCLK signal samples the RCLK signal, that is, metastable state sampling occurs, the metastable state detection circuit in fig. 2 is used for detecting, and the working steps are as follows:
1) Firstly, delaying an MCLK signal and an RCLK signal by a delay circuit (delay) td to respectively generate a signal MCK1 and a signal RCK1, and setting a delay time td according to design requirements during actual use, wherein the magnitude of the delay time td determines a metastable state area;
2) Using the same DFF (D flip-flop DFF 2) as in the sampling circuit, Q1 is generated by sampling the signal RCK1 with the MCLK signal (this sampling step is equivalent to sampling RCLK using MCLK shifted forward by td time); using D flip-flop DFF3, sampling the RCLK signal by signal MCK1 to generate Q2 (i.e., sampling the RCLK signal with the MCLK signal delayed by time td);
3) The OUT signal is obtained by using Q2 as the clock sample Q1 through the D flip-flop DFF, and this signal can be used as a flag bit for whether the sample is in a metastable state or not.
The principle of operation of the entire metastability detection circuit is to sample the RCLK signal using the MCLK _ PRE signal generated by advancing the MCLK signal by the time td and the MCLK _ DLY signal generated by delaying the MCLK signal by the time td as the sampling clock. As shown in fig. 3 (taking the rising edge sampling as an example), when the rising edge of the RCLK signal is in the region td times before and after the rising edge of the MCLK signal, the MCLK _ PRE signal and the MCLK _ DLY signal are sampled to 0 and 1, respectively. As shown in FIG. 4, both the MCLK _ PRE and MCLK _ DLY signals sample a 0 or a 1 when the rising edge of the RCLK signal is outside the region of time td before and after the rising edge of the MCLK signal. Therefore, whether the MCLK signal sampling RCLK signal is in a metastable state area can be judged according to the sampling result.
Further, when the number of the D flip-flops DFF is more than 1, the Q terminal of the previous D flip-flop DFF is connected to the D terminal of the next D flip-flop DFF first, the Q terminal of the last D flip-flop DFF is used as the output of the metastable state detection circuit, the D terminal of the first D flip-flop DFF is connected to the Q terminal of the D flip-flop DFF2, and the CLK terminal of any one D flip-flop DFF is connected to the Q terminal of the D flip-flop DFF 3.
When more than 1D trigger DFF is arranged, the requirement of accuracy can be increased, for example, whether the sampling is in a metastable state is judged through outputting q 1-qn by n D trigger DFFs.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way, and all simple modifications and equivalent variations of the above embodiments according to the technical spirit of the present invention are included in the scope of the present invention.
Claims (2)
1. A metastability detection circuit applied to synchronous clock sampling of a high-speed analog-to-digital converter, characterized by: the digital controlled clock signal input device comprises a D trigger DFF2, a D trigger DFF3 and at least one D trigger DFF, wherein the D end of the D trigger DFF2 is connected with an RCLK signal through a delay circuit, the CLK end of the D trigger DFF3 is connected with an MCLK signal through a delay circuit, the MCLK signal is also input to the CLK end of the D trigger DFF2, and the RCLK signal is also input to the D end of the D trigger DFF 3; the Q end of the D trigger DFF2 is connected with the D end of the D trigger DFF, the Q end of the D trigger DFF3 is connected with the CLK end of the D trigger DFF, and the Q end of the D trigger DFF is used as the output of the metastable state detection circuit.
2. The meta-stable state detection circuit applied to the synchronous clock sampling of the high-speed analog-to-digital converter of claim 1, wherein: when the number of the D flip-flops DFF is more than 1, the Q terminal of the previous D flip-flop DFF is connected with the D terminal of the next D flip-flop DFF first, the Q terminal of the last D flip-flop DFF is used as the output of the metastable state detection circuit, the D terminal of the first D flip-flop DFF is connected with the Q terminal of the D flip-flop DFF2, and the CLK terminal of any one D flip-flop DFF is connected with the Q terminal of the D flip-flop DFF 3.
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| JP7439266B2 (en) | 2020-08-20 | 2024-02-27 | チャンシン メモリー テクノロジーズ インコーポレイテッド | Detection circuit and detection method |
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Effective date of registration: 20231023 Address after: 201306 2nd floor, no.979 Yunhan Road, Lingang New Area, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai Patentee after: Mingkesi (Shanghai) Microelectronics Technology Co.,Ltd. Address before: No.14, east section 3, 2nd Ring Road, Chenghua District, Chengdu, Sichuan 610000 Patentee before: CHENGDU MECS MICROELECTRONICS TECHNOLOGY CO.,LTD. |