CN108347245A - Clock dividers - Google Patents
Clock dividers Download PDFInfo
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- CN108347245A CN108347245A CN201810191560.8A CN201810191560A CN108347245A CN 108347245 A CN108347245 A CN 108347245A CN 201810191560 A CN201810191560 A CN 201810191560A CN 108347245 A CN108347245 A CN 108347245A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
- H03K23/42—Out-of-phase gating or clocking signals applied to counter stages
- H03K23/44—Out-of-phase gating or clocking signals applied to counter stages using field-effect transistors
Abstract
The invention discloses a kind of Clock dividers, the Clock dividers include control signal generator module and fractional frequency signal generation module；Control signal generator module generates control signal corresponding with input clock signal for receiving input clock signal and frequency division parameter, and according to frequency division parameter, then sends control signals to the fractional frequency signal generation module；Fractional frequency signal generation module generates sampled clock signal corresponding with the input clock signal for receiving input clock signal, and according to the control signal of reception；Along following, the starting clock edge of the input clock signal corresponding clock cycle is synchronous to be changed the starting clock of sampled clock signal corresponding clock cycle.The present invention ensures that the sampled clock signal of frequency dividing generation still has preferable clock jitter performance in its corresponding sampling edge when as sampling clock, greatly weakens the restriction of dynamic property of the clock jitter performance on sampling clock edge to analog-digital converter sampling medium-and-high freuqncy signal when.
Description
Technical field
The present invention relates to signal processing technology field, more particularly to a kind of Clock dividers.
Background technology
With the rapid development of Modern Communication System, sampling rate and resolution ratio to analog-digital converter also propose therewith
Increasingly higher demands.With more and more wider by the bandwidth of sampled signal, it is getting faster by the frequency of sampled signal, sampling clock
Influence of the clock jitter performance to the dynamic property (such as signal-to-noise ratio) of analog-digital converter it is increasing, therefore, sampling clock
Jitter performance largely restricts the raising of the signal-to-noise ratio of analog-digital converter.
In the prior art, for the convenience of system application, the clock signal of same frequency is often sent to each of system
In circuit module.Specifically, its internal sample clock of analog-digital converter is by using traditional CMOS (Complementary
Metal Oxide Semiconductor, complementary metal oxide semiconductor) Clock dividers divide the clock signal of input
It generates；There are the clock jitter better performances even if input clock in the scaling down processing mode, still, the output clock generated
Clock jitter performance is poor, therefore the serious high-speed ＆ resolution ADC that restricts samples high-frequency signal and intermediate-freuqncy signal
When dynamic property raising.
Invention content
The technical problem to be solved by the present invention is in order to overcome in the prior art analog-digital converter use traditional CMOS when
Clock frequency divider carries out scaling down processing to clock signal, and the clock jitter performance that there is output clock is poor, seriously restricts height
The defect of the raising of dynamic property when speed, high-precision adc sampling high-frequency signal and intermediate-freuqncy signal, it is therefore intended that carry
For a kind of Clock dividers.
The present invention is to solve above-mentioned technical problem by following technical proposals：
The present invention provides a kind of Clock dividers, and the Clock dividers include control signal generator module and fractional frequency signal
Generation module；
The control signal generator module is used to receive input clock signal and frequency division parameter, and according to the frequency division parameter
Control signal corresponding with the input clock signal is generated, the control signal, which is then sent to the fractional frequency signal, generates
Module；
The fractional frequency signal generation module is used to receive the input clock signal, and according to the control signal of reception
Generate sampled clock signal corresponding with the input clock signal；
The starting clock of the sampled clock signal corresponding clock cycle is along following the input clock signal corresponding
The starting clock of clock cycle changes along synchronous.
Preferably, the control signal generator module is additionally operable to receive the first clock with the input clock signal reverse phase
Signal.
Preferably, the Clock dividers further include the first NOT gate；
First NOT gate is electrically connected with the control signal generator module, anti-for carrying out the input clock signal
Phase processor obtains first clock signal.
Preferably, the control signal generator module includes counter and end cycle detection circuit；
The count value is sent to the end cycle detection circuit by the counter for exporting count value；
The end cycle detection circuit for receiving the input clock signal, and according to the input clock signal and
The count value generates the control signal；
Wherein, the control signal includes first control signal and second control signal, and the first control signal and
The second control signal was in the same clock cycle.
Preferably, the counter includes at least one flip-flop element；
The flip-flop element include first d type flip flop (a kind of trigger) with set and reset function, NAND gate,
Or door and the second NOT gate；
One input terminal of the NAND gate is electrically connected with described or door the input terminal, the output end of the NAND gate and institute
State the set end electrical connection of the first d type flip flop；
Described or door another input terminal is electrically connected with the output end of second NOT gate, described or door output end and institute
State the reset terminal electrical connection of the first d type flip flop；
The input end of clock of first d type flip flop is electrically connected with the output end of first NOT gate, the first D triggerings
The output end of device is electrically connected with the end cycle detection circuit.
Preferably, the end cycle detection circuit includes nor gate, third NOT gate, the 4th NOT gate, the 5th NOT gate, the 6th
NOT gate, the second d type flip flop and third d type flip flop；
The input terminal electrical connection different from the one of the nor gate respectively of the output end of each first d type flip flop；
The output end of the nor gate is electrically connected with the input terminal of second d type flip flop；
The output end of second d type flip flop respectively with the input terminal of the 5th NOT gate and the third d type flip flop
Input terminal is electrically connected；
The input terminal of the third NOT gate is electrically connected with the output end of first NOT gate, the output end of the third NOT gate
It is electrically connected respectively with the input terminal of the input end of clock of second d type flip flop and the 4th NOT gate；
The output end of 4th NOT gate is electrically connected with the input end of clock of the third d type flip flop；
The output end of the third d type flip flop is electrically connected with the input terminal of the 6th NOT gate；
The output end of 5th NOT gate and the output end of the 6th NOT gate are electric with the fractional frequency signal generation module
Connection；
Wherein, the output end of the 5th NOT gate exports the first control signal, and the output end of the 6th NOT gate is defeated
Go out the second control signal；
The output end of 5th NOT gate respectively with another input terminal of the NAND gate, the input terminal of second NOT gate
Electrical connection.
Preferably, when the count value meets the first setting count value, the institute of the end cycle detection circuit output
It states first control signal and the second control signal controls the fractional frequency signal generation module output and follows the input clock
The starting clock of signal corresponding clock cycle changes the sampled clock signal along synchronous；
When the count value meets the second setting count value, the fractional frequency signal generation module exports a fixed clock
Periodic signal；
Wherein, the clock cycle of the fixed clock periodic signal is identical as the clock cycle of the input clock signal.
Preferably, the fractional frequency signal generation module includes the first PMOS tube (Positive channel Metal
Oxide Semiconductor, mos field effect transistor), the second PMOS tube, third PMOS tube, first
NMOS (N Metal Oxide Semiconductor, N-type metal-oxide semiconductor (MOS)) pipes, the second NMOS tube and the 3rd NMOS
Pipe；
The grid of first PMOS tube is electrically connected with the output end of the 5th NOT gate, the source electrode of first PMOS tube
It is electrically connected with power end, the drain electrode of first PMOS tube is electrically connected with the source electrode of second PMOS tube；
The grid of second PMOS tube is electrically connected with the clock signal input terminal mouth, the drain electrode of second PMOS tube
Respectively with the draining of the third PMOS tube, the drain electrode of first NMOS tube and the drain electrode of second NMOS tube are electrically connected；
The grid of the third PMOS tube is electrically connected with the output end of the 6th NOT gate, the source electrode of the third PMOS tube
It is electrically connected with the power end；
The drain electrode of the third PMOS tube is also electrically connected with the clock signal output terminal mouth；
The grid of first NMOS tube is electrically connected with the clock signal input terminal mouth, the source electrode of first NMOS tube
It is electrically connected respectively with the drain electrode of the source electrode of second NMOS tube and the 3rd NMOS；
The grid of second NMOS tube is electrically connected with the output end of the 5th NOT gate；
The grid of the third NMOS tube is electrically connected with the output end of the 6th NOT gate, the source electrode of the third NMOS tube
Ground connection.
Preferably, the starting failing edge of the sampled clock signal corresponding clock cycle follows the input clock signal
The starting rising edge synch of corresponding clock cycle changes；Or, in the starting of the sampled clock signal corresponding clock cycle
It rises along the starting failing edge synchronization variation for following the input clock signal corresponding clock cycle.
The positive effect of the present invention is that：
The present invention will need to carry out the clock of the input clock signal of clock jitter performance optimization along respectively by control letter
Number generation module and fractional frequency signal generation module cooperation processing, generate the sampled clock signal for being used as sampling after frequency dividing, at this
Additional increased clock jitter very little during reason, to ensure the sampled clock signal of frequency dividing generation when as sampling clock
Its corresponding clock is along still having preferable clock jitter performance, to considerably reduce the clock jitter on sampling clock edge
The restriction of dynamic property of the performance to analog-digital converter when sampling medium-and-high freuqncy signal, optimizes existing analog-digital converter and is adopting
Dynamic property when sample medium-and-high freuqncy signal.
Description of the drawings
Fig. 1 is the module diagram of the Clock dividers of present pre-ferred embodiments；
Fig. 2 is the electrical block diagram of the control signal generator module of the Clock dividers of present pre-ferred embodiments；
Fig. 3 is the electrical block diagram of the end cycle detection circuit of the Clock dividers of present pre-ferred embodiments；
Fig. 4 is the electrical block diagram of the fractional frequency signal generation module of the Clock dividers of present pre-ferred embodiments；
Fig. 5 is the principle schematic of the Clock dividers of present pre-ferred embodiments.
Specific implementation mode
The embodiment for further illustrating the present invention, but therefore not limiting the present invention to below by the mode of embodiment
Among range.
As shown in Figure 1, the Clock dividers of the present embodiment include the first NOT gate 1, control signal generator module 2 and frequency dividing letter
Number generation module 3.
Control signal generator module 2 is for receiving and the first clock signal of input clock signal reverse phase.
Specifically, the first NOT gate 1 is electrically connected with control signal generator module 2, for input clock signal to be carried out reverse phase
Processing obtains the first clock signal.
Control signal generator module 2 is additionally operable to receive input clock signal and frequency division parameter, and is generated according to frequency division parameter
Control signal corresponding with input clock signal, then sends control signals to fractional frequency signal generation module 3；
Fractional frequency signal generation module 3 is generated and is inputted for receiving input clock signal, and according to the control signal of reception
The corresponding sampled clock signal of clock signal.
Wherein, the starting clock edge of sampled clock signal corresponding clock cycle follows the corresponding clock of input clock signal
The starting clock in period changes along synchronous.
In addition, the general rising edge for only using clock signal or failing edge are as sampling clock edge in sampling system.This reality
The Clock dividers of example are applied when carrying out sampling clock, is used as using the failing edge of input clock signal and needs clock jitter performance
The sampling clock edge of optimization.The upper drop of input clock signal can also be used along as the clock for needing clock jitter performance to optimize
Then the corresponding clock of the situation is trembled using the failing edge of sampled clock signal as the sampling clock edge of sampling system on edge
Dynamic performance optimization process just repeats no more herein.
In the present embodiment, the clock edge optimized as clock jitter performance using the failing edge of input clock signal, and will
Input clock signal is divided into the clock signal for generating control signal and the clock signal for generating fractional frequency signal, rather than
Control signal generator module 2 and fractional frequency signal generation module 3 the two modules are directly driven using input clock signal, to subtract
The driving load of light input clock signal, reduces deterioration of the load to the clock jitter performance of the failing edge of input clock signal,
And then improve the clock jitter performance of the failing edge of input clock signal.
It includes counter 21 and end cycle detection circuit 22 to control signal generator module 2.
As shown in Fig. 2, counter 21 is used to export count value, and count value is sent to end cycle detection circuit 22.
End cycle detection circuit 22 is used to receive input clock signal, and according to input clock signal and count value, raw
At control signal；
Wherein, control signal includes first control signal and second control signal, and first control signal and second controls
Signal was in the same clock cycle.
When count value meets the first setting count value, first control signal and that end cycle detection circuit 22 exports
Two control signal control fractional frequency signal generation modules, 3 output follows the starting clock edge of input clock signal corresponding clock cycle
Synchronous variation sampled clock signal；
When count value meets the second setting count value, fractional frequency signal generation module 3 exports a fixed clock period letter
Number；
Wherein, the clock cycle of fixed clock periodic signal and the clock cycle of input clock signal are identical.
Specifically, counter 21 includes at least one flip-flop element 211.Counter 21 is programmable counter, is realized
The arbitrary frequency dividing ratio of Clock dividers.General counter includes multiple flip-flop elements 211, it is preferable that as shown in Fig. 2, triggering
The quantity of device unit 211 be 3, it can be achieved that frequency dividing ratio be 1~8.
Flip-flop element 211 includes the first d type flip flop 2111, NAND gate 2112 or the door for having set and reset function
2113 and second NOT gate 2114；
One input terminal of NAND gate 2112 with or an input terminal of door 2113 be electrically connected, the output end of NAND gate 2112 and
The set end of one d type flip flop 2111 is electrically connected；
Or another input terminal of door 2113 is electrically connected with the output end of the second NOT gate 2114 or the output end of door 2113 and
The reset terminal of one d type flip flop 2111 is electrically connected；
The input end of clock of first d type flip flop 2111 is electrically connected with the output end of the first NOT gate 1, the first d type flip flop 2111
Output end be electrically connected with end cycle detection circuit 22.
End cycle detection circuit 22 is used to receive input clock signal, and according to input clock signal and count value, raw
At first control signal s1 and second control signal s2.
As shown in figure 3, specifically, end cycle detection circuit 22 includes nor gate 221, third NOT gate 222, the 4th NOT gate
223, the 5th NOT gate 224, the 6th NOT gate 225, the second d type flip flop 226 and third d type flip flop 227.
Different with the one of the nor gate 221 input terminal electrical connections respectively of the output end of each first d type flip flop 2111.Such as figure
Shown in 3, output end a, b, c of three the first d type flip flops 2111 input terminal electrical connection different with the one of nor gate 221 respectively.
The output end of nor gate 221 is electrically connected with the input terminal of the second d type flip flop 226；
The input with the input terminal and third d type flip flop 227 of the 5th NOT gate 224 respectively of the output end of second d type flip flop 226
End electrical connection；
The input terminal of third NOT gate 222 is electrically connected with the output end of the first NOT gate 1, the output end difference of third NOT gate 222
It is electrically connected with the input terminal of the input end of clock of the second d type flip flop 226 and the 4th NOT gate 223.
The output end of 4th NOT gate 223 is electrically connected with the input end of clock of third d type flip flop 227；
The output end of third d type flip flop 227 is electrically connected with the input terminal of the 6th NOT gate 225；
The output end of 5th NOT gate 224 and the output end of the 6th NOT gate 225 are electrically connected with fractional frequency signal generation module 3；
Wherein, the output end of the 5th NOT gate 224 exports first control signal s1, the output end output the of the 6th NOT gate 225
Two control signal s2；
The output end of 5th NOT gate 224 respectively with another input terminal of NAND gate 2112, the input terminal of the second NOT gate 2114
Electrical connection.
Wherein, it as shown in Fig. 2, the achievable frequency dividing ratio of Clock dividers is 1~8, for being configured to three frequency division, counts
The output valve of device 21 carries out cycle subtraction count from 2 to 0.
As shown in figure 4, in addition, fractional frequency signal generation module 3 includes the first PMOS tube 31, the second PMOS tube 32, third
PMOS tube 33, the first NMOS tube 34, the second NMOS tube 35 and third NMOS tube 36.
The grid of first PMOS tube 31 is electrically connected with the output end of the 5th NOT gate 224, source electrode and the electricity of the first PMOS tube 31
Source is electrically connected, and the drain electrode of the first PMOS tube 31 is electrically connected with the source electrode of the second PMOS tube 32；
The grid of second PMOS tube 32 is electrically connected with clock signal input terminal mouth, and the drain electrode of the second PMOS tube 32 is respectively with
The drain electrode of three PMOS tube 33, the drain electrode of the first NMOS tube 34 and the drain electrode of the second NMOS tube 35 electrical connection；
The grid of third PMOS tube 33 is electrically connected with the output end of the 6th NOT gate 225, source electrode and the electricity of third PMOS tube 33
Source is electrically connected；
The drain electrode of third PMOS tube 33 is also electrically connected with clock signal output terminal mouth 5；
The grid of first NMOS tube 34 is electrically connected with clock signal input terminal mouth 1, the source electrode of the first NMOS tube 34 respectively with
The drain electrode electrical connection of the source electrode and the 3rd NMOS56 of second NMOS tube 35；
The grid of second NMOS tube 35 is electrically connected with the output end of the 5th NOT gate 224；
The grid of third NMOS tube 36 is electrically connected with the output end of the 6th NOT gate 225, the source electrode ground connection of third NMOS tube 36.
Specifically, as shown in Figure 1, input clock signal is the input signal of logic gate in fractional frequency signal generation module 3, the
One control signal s1 and second control signal s0 is two control signals of the logic gate in fractional frequency signal generation module 3；
In the present embodiment, as shown in figure 4, work as s1=0, when s0=1, the opening of logic gate in fractional frequency signal generation module 3,
The failing edge of input clock signal generates the sampled clock signal of frequency dividing output via the logic gate of fractional frequency signal generation module 3
The rising edge of ckout, the rising edge for dividing the sampled clock signal ckout of output are used as the sampling clock edge of sampling system.By
The failing edge of ckin is the clock edge of clock jitter performance optimization in this present embodiment, and generation is directly opposite by simple logic door
Ckout rising edge clock jitter performance it is still preferable.
As shown in figure 5, the respectively oscillogram of input clock signal ckin, the oscillogram of the first clock signal ck1, counting
Device 21 time-count cycle figure, the output waveform figure of nor gate 221, the oscillogram of first control signal s1, second control signal s2
Oscillogram and sampled clock signal ckout.
When each of counter 21, which counts, is counted as 0 in the period, end cycle detection module 32 is then believed in the first clock
The failing edge of number ck1 generates effective reload signals, particularly, in the present embodiment correspond to reload signals as high level, and
Reload output high level continues an input clock signal corresponding clock cycle；Wherein, reload signals are that reloading is believed
Number, with setting of divider parameter div<2:0>Cooperation generates the set and reset of each first d type flip flop 2111 in counter 21
Signal, to which new one initial value for counting period Counter 21 be arranged.
Reload signals are subjected to reverse process, first control signal s1 generates low level and continues input clock signal pair
The clock cycle answered, the rising edge for becoming next clock cycle of high level in reload signals generates s0, produced
The low level of s0 also continue a clock cycle, while after reload signals become high level, to constituting the of counter 21
2-D trigger 226 and/or third d type flip flop 227 carry out asynchronous set/reset, make the output q of counter 21<2:0>It is updated to
Equal to div<2:0>Value, counter 21 enter next counting period.
Wherein, as shown in Fig. 2, q<2:0>For output a, b, c table of three in counter 21 first d type flip flops 2111
Show, q<2>C in corresponding diagram 2, q<1>B in respective figure 2, q<0>A in respective figure 2.
div<2:0>One three binary numbers for setting of divider parameter, for by setting of divider be this two
System number adds one, such as div<2:0>When=011, corresponding decimal number 3, it is 4 that frequency dividing ratio is arranged at this time.
Wherein, the delay td1 and td2 generated in first control signal s1 and second control signal s0, by fractional frequency signal
3 counteracting of generation module is handled, and obtains the sampled clock signal ckout's being consistent with the failing edge of output input clock signal
Rising edge, optimizes the clock jitter performance of the failing edge of input clock signal, ensure sampled clock signal that frequency dividing generates with
Make its corresponding sampling when sampling clock and greatly weakens the clock on sampling clock edge along still having preferable clock jitter performance
The restriction of dynamic property when jitter performance is to analog-digital converter sampling medium-and-high freuqncy signal.
In addition, when s1 and s0 meet other conditions, logic gate has fixed output in fractional frequency signal generation module 3, makes point
The high level of the sampled clock signal ckout of frequency output continues the clock cycle of an input clock signal, divides adopting for output
The failing edge of sample clock signal ckout is unrelated with the jitter performance of input clock.
Example will need to carry out the rising edge of the input clock signal of clock jitter performance optimization respectively by controlling in this implementation
3 cooperation of signal generator module 2 and fractional frequency signal generation module processed is handled, and generates the decline as sampled clock signal after frequency dividing
Edge, additional increased clock jitter very little in the processing procedure, to ensure sampled clock signal that frequency dividing generates as adopting
Its corresponding sampling is along still having preferable clock jitter performance when sample clock, to considerably reduce sampling clock edge
The restriction of dynamic property of the clock jitter performance to analog-digital converter when sampling medium-and-high freuqncy signal optimizes existing modulus and turns
Dynamic property of the parallel operation when sampling medium-and-high freuqncy signal.
Although specific embodiments of the present invention have been described above, it will be appreciated by those of skill in the art that these
It is merely illustrative of, protection scope of the present invention is defined by the appended claims.Those skilled in the art is not carrying on the back
Under the premise of from the principle and substance of the present invention, various changes or modifications can be made to these embodiments, but these are changed
Protection scope of the present invention is each fallen with modification.
Claims (9)
1. a kind of Clock dividers, which is characterized in that the Clock dividers include control signal generator module and fractional frequency signal
Generation module；
The control signal generator module is generated for receiving input clock signal and frequency division parameter, and according to the frequency division parameter
Then the control signal is sent to the fractional frequency signal and generates mould by control signal corresponding with the input clock signal
Block；
The fractional frequency signal generation module is generated for receiving the input clock signal, and according to the control signal of reception
Sampled clock signal corresponding with the input clock signal；
The starting clock of the sampled clock signal corresponding clock cycle is along following the corresponding clock of the input clock signal
The starting clock in period changes along synchronous.
2. Clock dividers as described in claim 1, which is characterized in that the control signal generator module be additionally operable to receive with
First clock signal of the input clock signal reverse phase.
3. Clock dividers as claimed in claim 2, which is characterized in that the Clock dividers further include the first NOT gate；
First NOT gate is electrically connected with the control signal generator module, for carrying out the input clock signal at reverse phase
Reason obtains first clock signal.
4. Clock dividers as claimed in claim 3, which is characterized in that the control signal generator module include counter and
End cycle detection circuit；
The count value is sent to the end cycle detection circuit by the counter for exporting count value；
The end cycle detection circuit is for receiving the input clock signal, and according to the input clock signal and described
Count value generates the control signal；
Wherein, the control signal includes first control signal and second control signal, and the first control signal and described
Second control signal was in the same clock cycle.
5. Clock dividers as claimed in claim 4, which is characterized in that the counter includes at least one trigger list
Member；
The flip-flop element includes the first d type flip flop, NAND gate or the door and the second NOT gate for having set and reset function；
One input terminal of the NAND gate is electrically connected with described or door the input terminal, the output end of the NAND gate and described the
The set end of one d type flip flop is electrically connected；
Described or door another input terminal is electrically connected with the output end of second NOT gate, described or door output end and described the
The reset terminal of one d type flip flop is electrically connected；
The input end of clock of first d type flip flop is electrically connected with the output end of first NOT gate, first d type flip flop
Output end is electrically connected with the end cycle detection circuit.
6. Clock dividers as claimed in claim 5, which is characterized in that the end cycle detection circuit include nor gate,
Third NOT gate, the 4th NOT gate, the 5th NOT gate, the 6th NOT gate, the second d type flip flop and third d type flip flop；
The input terminal electrical connection different from the one of the nor gate respectively of the output end of each first d type flip flop；
The output end of the nor gate is electrically connected with the input terminal of second d type flip flop；
The input with the input terminal and the third d type flip flop of the 5th NOT gate respectively of the output end of second d type flip flop
End electrical connection；
The input terminal of the third NOT gate is electrically connected with the output end of first NOT gate, the output end difference of the third NOT gate
It is electrically connected with the input terminal of the input end of clock of second d type flip flop and the 4th NOT gate；
The output end of 4th NOT gate is electrically connected with the input end of clock of the third d type flip flop；
The output end of the third d type flip flop is electrically connected with the input terminal of the 6th NOT gate；
The output end of 5th NOT gate and the output end of the 6th NOT gate are electrically connected with the fractional frequency signal generation module；
Wherein, the output end of the 5th NOT gate exports the first control signal, and the output end of the 6th NOT gate exports institute
State second control signal；
Input terminal of the output end of 5th NOT gate respectively with another input terminal of the NAND gate, second NOT gate is electrically connected
It connects.
7. Clock dividers as claimed in claim 4, which is characterized in that when the count value meets the first setting count value
When, the first control signal and the second control signal of the end cycle detection circuit output control the frequency dividing letter
The output of number generation module follows the starting clock of the input clock signal corresponding clock cycle to change the sampling along synchronous
Clock signal；
When the count value meets the second setting count value, the fractional frequency signal generation module exports a fixed clock period
Signal；
Wherein, the clock cycle of the fixed clock periodic signal is identical as the clock cycle of the input clock signal.
8. Clock dividers as claimed in claim 6, which is characterized in that the fractional frequency signal generation module includes the first PMOS
Pipe, the second PMOS tube, third PMOS tube, the first NMOS tube, the second NMOS tube and third NMOS tube；
The grid of first PMOS tube is electrically connected with the output end of the 5th NOT gate, source electrode and the electricity of first PMOS tube
Source is electrically connected, and the drain electrode of first PMOS tube is electrically connected with the source electrode of second PMOS tube；
The grid of second PMOS tube is electrically connected with the clock signal input terminal mouth, the drain electrode difference of second PMOS tube
With the draining of the third PMOS tube, the drain electrode of first NMOS tube and the drain electrode of second NMOS tube are electrically connected；
The grid of the third PMOS tube is electrically connected with the output end of the 6th NOT gate, the source electrode of the third PMOS tube and institute
State power end electrical connection；
The drain electrode of the third PMOS tube is also electrically connected with the clock signal output terminal mouth；
The grid of first NMOS tube is electrically connected with the clock signal input terminal mouth, the source electrode difference of first NMOS tube
It is electrically connected with the drain electrode of the source electrode of second NMOS tube and the 3rd NMOS；
The grid of second NMOS tube is electrically connected with the output end of the 5th NOT gate；
The grid of the third NMOS tube is electrically connected with the output end of the 6th NOT gate, and the source electrode of the third NMOS tube connects
Ground.
9. Clock dividers as described in claim 1, which is characterized in that the sampled clock signal corresponding clock cycle
Starting failing edge follows the starting rising edge synch of the input clock signal corresponding clock cycle to change；Or, the sampling
The starting rising edge of clock signal corresponding clock cycle follows under the starting of the input clock signal corresponding clock cycle
Drop changes along synchronous.
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| CN201810191560.8A CN108347245B (en) | 2018-03-08 | 2018-03-08 | Clock frequency divider |
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| CN201810191560.8A CN108347245B (en) | 2018-03-08 | 2018-03-08 | Clock frequency divider |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114337652A (en) * | 2022-02-15 | 2022-04-12 | 山东兆通微电子有限公司 | Frequency divider circuit and frequency synthesizer |
| WO2023178803A1 (en) * | 2022-03-23 | 2023-09-28 | 长鑫存储技术有限公司 | Signal sampling circuit and semiconductor memory |
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