WO2000018010A1

WO2000018010A1 - Rs flip-flop and a frequency divider implemented with the flip-flop

Info

Publication number: WO2000018010A1
Application number: PCT/FI1999/000716
Authority: WO
Inventors: Paulus Carpelan
Original assignee: Nokia Networks Oy
Priority date: 1998-09-18
Filing date: 1999-09-07
Publication date: 2000-03-30
Also published as: FI982014A0; AU5519799A; FI982014A; FI105424B

Abstract

The invention relates to an RS flip-flop and to an RS flip-flop provided with a clock input, and to a frequency divider to be implemented therewith. To produce for example a fast divider generating a clock signal with a symmetrical pulse ratio, a frequency divider is constructed from two RS flip-flops provided with a clock input by means of a master-slave connection. In such a case, both the master and the slave flip-flop include and RS flip-flop (RS_FF) having two cross-connected inverters (1' and 2') known per se and two control means (M3' and M6') for forced control of the inverters through setting and resetting inputs to the desired state. Furthermore, a third and fourth inverter (1 and 2) are connected ahead of the RS flip-flop (RS_FF), so that the input of each inverter constitutes a clock input (CLK). The output of the third inverter is connected to the setting input of the flip-flop (RS_FF), and the voltage supply terminal (P1) of the inverter constitutes a second setting input (SET) for activating the inverter to input the desired clock signal by means of the set signal to the setting input of the flip-flop (RS_FF). The output of the fourth inverter is connected to the resetting input of the flip-flop (RS_FF) and the voltage supply terminal (P2) of the inverter constitutes a second resetting input (RESET) for activating the inverter to input the desired clock signal by means of the reset signal to the resetting input of the flip-flop (RS_FF).

Description

RS flip-flop and a frequency divider implemented with the flip-flop

Field of the Invention

The present invention relates generally to an RS flip-flop and to an RS flip-flop provided with a clock input, and to a high-speed symmetrical frequency divider to be implemented therewith, particularly to a divider of the clock frequency into two.

Background of the Invention An RS flip-flop is the basic flip-flop of bistable flip-flop circuits and is typically implemented with two nand or nor gate pairs. Figure 1 shows a conventional RS flip-flop implemented with a nand gate pair (the term latch is also used in the literature for such a circuit). An RS flip-flop has a cross- connect typical of sequencers. The flip-flop includes two static forced input, i.e. the set (S) and reset (R) inputs and two outputs Q and /Q, which are always in opposite state relative to one another (the slash / means that the active state of the signal is zero, and if there is no slash, the active state is one). By means of the forced inputs, the RS flip-flop can be forced to either of the digital states 0 or 1 , that is, the flip-flop can either be reset (Q = 0) or set (Q = 1). The intakes of the flip-flop determine in what manner the output of the flip-flop changes its state. An RS flip-flop has one forbidden control state in view of the flip-flop function: if both R and S are simultaneously set to state 1 , then both the Q and the /Q output strive simultaneously for state 0, which is an abnormal state for flip-flop function as the outputs are complements of one another. In such a control attempt, the flip-flop will end in an indeterminate operative state. An RS flip-flop having a clock (CLK) input, a so-called synchronous flip-flop circuit, is obtained when two nand gates are added ahead of a conventional RS flip-flop as in Figure 1b. The flip-flop can be implemented for example with nand gates of the CMOS 4000B series (which is the industrial standard); CMOS loops use both N-channel and P-channel enhancement-type MOS transistors. Figure 1c shows the circuit diagram of a nand gate, wherein two MOS transistors of different types as stated above have been used: transistors M1 and M2 are PMOS transistors and M3 and M4 are NMOS transistors. If both input terminals (IN_A and IN_B) are in state 1 , transistors M3 and M4 are conductive and M1 and M2 are open, in which case the output (OUT) is in state 0. If either (or both) of the input terminals is/are in state 0, one (or both) of transistors M1 and M2 is/are in conductive state and one (or both) of transistors M3 or M4 is/are open. In such a situation, the output is in state 1. The current consumption is dependent on the operating frequency, as the current consumption of the circuit is significant only during changes of the logic states.

A synchronous flip-flop circuit (Figure 1b) changes its state in step with a clock signal and stores and memorizes its state. An RS flip-flop provided with a clock input is used for example in a frequency divider, in which a conventional clock divider is constructed of two RS flip-flops, master and slave, by connecting the nand gate pairs as shown in Figure 1d; the first flip-flop RS1 is the master and the second flip-flop RS2 is the slave. The clock signal is supplied to the master flip-flop as such and to the slave flip-flop via a NOT gate, i.e., in inverted form. As is apparent from the above, one RS flip-flop provided with a clock input typically has a total of 16 transistors. In addition, since the inverter normally has 2 transistors, a conventional clock divider has a total of 34 transistors. Each transistor stage consumes time and slows down the operation of the divider. One way of accelerating the operation of the divider is to minimize the number of transistors and the connections between them. An article published in the IEEE series (IEEE Journal of Solid-State

Circuits, Vol. 30, No. 2, February 1995), Design of High-Speed, Low-Power Frequency Dividers and Phase-Locked Loops in Deep Submicron CMOS, discloses a high-speed frequency divider based on a fast D latch. The clock divider is implemented with a master-slave circuit. The master and slave are similar D latches implemented with 6 transistors, i.e., the divider has a total of 12 transistors. A good feature of the above frequency divider is its high speed. However, a factor limiting the use of the divider is the asymmetrical clock signal generated thereby, as the divider omits every second pulse from the clock signal. This being the case, the frequency divider cannot be utilized in applications in which a symmetrical clock signal is needed. Such applications include circuits utilizing both the rising and the falling edge of the clock.

Summary of the Invention

The invention relates to an RS flip-flop and to an RS flip-flop provided with a clock input, wherewith a high-speed symmetrical frequency divider can be implemented. It is an object of the present invention to provide a solution wherewith the above-stated drawbacks, particularly relating to the speed of the frequency divider and to the clock signal generated thereby, can be eliminated. This object is achieved with a solution as defined in the independent claims. The frequency divider is constructed from two master-slave RS flip- flops provided with a clock input in a known manner in such a way that the incoming clock signal is supplied to the master flip-flop as such and to the slave flip-flop as inverted. The implementation in accordance with the present invention differs essentially from the previously disclosed solutions in respect of the topology of the RS flip-flop. The basic idea of the invention is to use in the RS flip-flop inverters and controller means controlling them, instead of conventional nand or nor gates, thus enabling the number of components to be diminished. As the number of components is diminished, the number of signal lines in the circuit is naturally also diminished, which will contribute to reducing propagation delays and power consumption. A flip-flop implemented with the topology in accordance with the invention typically has 10 transistors as compared to the conventional 16 transistors. As a result, the divider implemented with the RS flip-flops also has a considerably smaller number of transistors (22) as compared to a conventional divider producing a symmetrical clock signal (34 transistors). Hence, the solution in accordance with the invention requires less components, thus saving the silicon surface area and reducing the production costs. In accordance with a preferred embodiment of the invention, the supply of the clock signal to the RS flip-flop is provided by two inverters, the "supply voltage" control of the inverters taking place by means of SET and RESET signals. The frequency divider can be implemented for example with CMOS logic circuits.

The symmetrical frequency divider in accordance with the invention can be used in connections utilizing both the rising and the falling edge of the clock. An exemplary case in which a high-rate symmetrical clock divider can be utilized is a PLL loop in which the output signal of a broadband voltage- controlled VCO oscillator is connected to a frequency divider in which it is divided by a suitable integer. The output signal of the divider is thus the output signal of the entire phase-locked loop, or depending on the application it is also possible to connect the output of the divider as a feedback to the phase comparator of the phase-locked loop, for example.

Even though the primary application of the RS flip-flops in accordance with the invention is a symmetrical frequency divider, they can naturally also be employed in other applications in which there is a need to benefit from the above advantages.

List of Drawings

The invention will be described more closely in the following by means of the accompanying schematic figures, in which

Figures 1a - 1d show conventional block diagrams of an RS flip-flop, a clocked RS flip-flop and a clock divider, as well as a circuit diagram of a conventional nand gate,

Figure 2 is a switching diagram of an RS flip-flop in accordance with the invention,

Figure 3 is a switching diagram of a clocked RS flip-flop in accordance with the invention, Figure 4 is a schematic illustration of a symmetrical frequency divider in accordance with the invention, implemented with two RS flip-flops as shown in Figure 3,

Figure 5 shows the simulation result of the clock divider in accordance with the invention, and Figure 6a is a timing diagram illustrating the signals of the circuit in accordance with Figure 3.

Detailed Description of the Invention

Figure 4 illustrates a symmetrical frequency divider in accordance with the invention, constructed of two high-speed master-slave RS flip-flops (Clk_RS_FF), implemented with novel topology, in a known manner so that the incoming clock signal is supplied to the first flip-flop as such and to the second flip-flop as inverted. The master and slave flip-flops of the frequency divider are implemented with a clocked RS flip-flop in accordance with the invention, which is illustrated in Figure 3. On the other hand, the RS flip-flop shown in Figure 2 has been used to implement the clocked RS flip-flop.

Let us consider next the implementation of the invention by way of example by means of Figures 2 and 3. It is to be noted that we use the term RS flip-flop of the circuits of Figures 2 and 3 (the literature also uses the terms RS latch and RS latch with a clock input for circuits of this kind). The RS flip- flop RS_FF shown in Figure 3 corresponds to the flip-flop shown in Figure 2. The RS flip-flop of Figure 2 has forced inputs: resetting input RESET2 and setting input SET2, and in addition to these, outputs Q and /Q. In accordance with the operating principle of the flip-flop, the states of the outputs are always reverse relative to one another. The clock signal is supplied to the flip-flop in accordance with Figure 3 with two inverters 11 and 12, the first of which (11) includes transistors M1 and M2 and the second (12) transistors M3 and M4. The transistors can be for example PMOS and NMOS transistors. The inverters are not supplied with a conventional supply voltage, but the SET and RESET signals are used as the "supply voltage". In Figure 3, the uppermost inverter includes a PMOS transistor M1 and an NMOS transistor M2. The SET input is connected to the source of the PMOS transistor, to which the supply voltage (V_dd) is normally connected in a conventional inverter. The drains of the PMOS and NMOS transistor are connected to one another, and additionally both drains are connected to the SET input of the RS flip-flop RS_FF. The lower inverter in the figure likewise has a PMOS transistor M3 and an NMOS transistor M4, and the RESET signal is connected as the "supply voltage" of this inverter, i.e. to the source of PMOS M3. Likewise, the drains of M3 and M4 are connected to one another and furthermore to the RESET input of the RS flip-flop RS_FF. The sources of both NMOS transistors M2 and M4 are connected to earth. The clock signal /CLK is supplied both to the gates of the transistors M1 and M2 of the upper inverter and to the gates of the transistors M3 and M4 of the lower inverter. The input signal of the inverters is thus the clock signal, i.e. the (rising or falling) active edge of the clock signal produces a new state in the flip-flop. As stated above, the SET signal is supplied to the current input terminal (P1) of inverter 11 and correspondingly the RESET signal is supplied to the current input terminal (P2) of inverter 12. When the SET and RESET controls are connected in this way to the current supply of the inverter, the supply voltage of the circuit is, so to speak, generated by means of these signals. The clock will get through the circuit (11) as long as the SET signal is up. When the SET signal is down, the output SET2 gives a mere zero. The inverter is thus activated only when SET is one (respectively, 12 is activated by the RESET signal). The SET and RESET signals reach the actual RS flip-flop (the RS flip-flop RS_FF in Figure 3 is the flip-flop of Figure 2) only when the clock signal (/CLK) is zero. When the clock signal is in state one, both signals (SET2 and RESET2) arriving at the RS flip-flop RS_FF are in zero state irrespective of the SET and RESET signals arriving at the inverters, and therefore the state of the flip-flop does not change (cf. the timing diagram of Figure 6).

The RS flip-flop of Figure 2 has a total of 6 transistors M1' - M6'. When the PMOS transistors M1' and M2¹ are connected as shown in the figure, the RS flip-flop maintains its state. The circuit shown in the figure further comprises two inverters, the first (11') including transistors M1' and M4' and the second (12') transistors M2' and M5'. The inverters are cross-connected, so that the output (o1) of inverter 11' is connected to the input (i2) of inverter 12' and the output (o2) of inverter 12' is connected to the input (i1) of inverter 11'. In other words, the cross-connection of the RS flip-flop is implemented as follows: the drains of the PMOS transistors M1' and M2' are connected to the drains of the NMOS transistors in such a way that the drain of transistor M1' is connected to the drains of both M3' and M4' and respectively the drain of transistor M2' is connected to the drains of both M5¹ and M6'. The drains of transistors M1', M3' and M4' are connected to the gates of transistors M2' and M5' and furthermore all the above are connected to output /Q. The gates of transistors M1' and M4' and the drains of transistors M2', M5' and M6' are interconnected, and furthermore all the above are connected to output Q (that is, the gates of transistors M1' and M4' are connected to output Q likewise as the drains of transistors M2', M5' and M6' are connected to output Q). The supply voltage (V_dd) of the circuit is connected to the sources of PMOS transistors M1' and M2'. The input SET2 is connected to the gate of NMOS transistor M3' and the input RESET2 to the gate of NMOS transistor M6'. Transistors M3' and M6¹ serving as control means can be used to force the output of either inverter to the desired value, as a result of which the output of the other inverter is changed to be reverse to the previous value, that is, when for example the output of the first inverter is forced to zero, this will force the output of the other inverter to change to one, as the inverters are cross- connected in the manner described above. Transistors M3¹ and M6' must be so designed that they shall be "stronger" than transistors M1' and M2', in the given order. That is, for example, transistor M3' must "draw downwards" more than M1' "draws upwards"; in other words, according to the flip-flop principle the heavier draws downwards.

The state of the flip-flop can change only when the clock signal CLK is down, i.e. the CLK input (Figure 3) is in state 0. In such a case, the input SET of Figure 3 is in the same state as the input SET2 of Figure 2, and the input RESET of Figure 3 is in the same state as the input RESET2 of Figure 2, respectively. When the clock signal is in state 0, the inputs SET and RESET of Figure 3 are both in state 0 irrespective of the state of the inputs SET2 and RESET2 of Figure 2.

Let us examine next the operation of an RS flip-flop provided with a clock input by means of a truth table. The changes in the state of the circuit can be seen from the table; on account of the clock pulse signal, these changes are made to take place substantially simultaneously in all parts of the circuit. In addition to the truth table, Figure 6 illustrates the signals of the circuit in accordance with the clocked RS flip-flop. SET2 and RESET2 represent input signals to the flip-flop RS_FF (Figure 3) (the values are not shown in the table).

In the table, Q^"1 and /Q^"1 correspond to the current state of the output of the clocked flip-flop and Q and /Q correspond to the new state of the flip-flop. SET and RESET are inputs of the clocked flip-flop. As is apparent from the table, they cannot simultaneously be in state 1 , since in such a case the flip- flop will end in an indeterminate operative state as both outputs strive for the same state.

It is to be seen from Figure 6, for instance, that in period Δt₁₂ the SET signal will change from 0 to 1 when the clock signal /CLK is in state 1 and the state of the flip-flop will remain unchanged, i.e. Q will remain in state 0 and /Q in state 1. However, when the clock signal /CLK changes from state 1 to state 0 at instant t₂, the state of the flip-flop also changes, i.e. the flip-flop is set to state 1 , that is, state 0 of Q changes to state one and state 1 of /Q changes to zero state; the change takes place on the falling edge of the clock signal. The flip-flop stores this setting until it is reset by a new control. The resetting of the flip-flop can be seen from the figure when the signal RESET rises up in period Δt₃₄, but the change in the state of the flip-flop does not take place until instant t₄, i.e. on the next falling edge of the clock signal. The flip-flop is reset at instant t₅, i.e. the signal SET changes from 0 to 1. In this case, the change takes place at an instant when /CLK is in state 0, and thus the flip-flop will immediately assume state 1 , that is, the state of Q changes from 0 to 1 and that of /Q from 1 to 0. The1 -state remains unchanged until the state is again reset. The outputs of the RS flip-flop can thus change only when the clock signal is down. When the clock signal is up, the state of the flip-flop remains unchanged. The signal SET2 or RESET2 corresponds to an inverted clock signal as long as the signal SET or RESET is one.

The topology of the flip-flop strives at reducing essential timing parameters, which include the stand-by times and the propagation delay.

Figure 4 shows a symmetric divider of the clock by two, with two RS flip- flops Clk_RS_FF provided with the clock input described above, implemented by means of a so-called master-slave connection. The first RS flip-flop is the master and the latter the slave flip-flop. The incoming clock signal CLK_in is supplied to the master flip-flop as such and to the slave flip-flop as inverted, that is, via a NOT gate. Output Q1 of the master flip-flop is connected to input MID2 of the slave flip-flop, and output /Q1 is connected to input /MID2 of the slave flip-flop. The outputs OUT and /OUT of the slave flip-flop are connected as a feedback to the inputs RESET and SET of the master flip-flop in said order. Said outputs of the slave flip-flop are also outputs for the entire frequency divider. Figure 5 shows the simulation result (CLK 100 MHz) of the clock divider in accordance with the invention. As is apparent from the figure, when the clock pulse is divided by two in the symmetrical frequency divider, the result will be a symmetrical clock pulse that has twice the breadth of the original pulse.

The frequency divider can be used in connections utilizing both the rising and the falling edge of the clock signal. One such implementation could be a phase-locked loop (PLL) including a voltage-controlled oscillator (VCO), such a loop being used in network terminals of a telecommunications network. The output frequency of VCO is often too high to be utilized as such, and therefore the output of the VCO is usually connected to the input of a frequency divider. The frequency is divided by using in the divider a suitable integer changeable by software, for example the integer 2. It is evident that the frequency divider can be utilized also in other dividers of the circuit. For example, many frequency synthesizers have a loop divider in the feedback path, by means of which the frequency of the output signal is divided prior to supply to the second input of the phase comparator. A reference signal is applied to the first input of the phase comparator. The phase comparator compares the reference signal and feedback signal, and on the basis of the phase difference it has detected between the input signals, it generates an output signal proportional to the phase difference, which serves as the control voltage of the oscillator. It is of significance to the phase comparator of the circuit that the clock signals are in proportion 50/50, otherwise the phase difference signal the phase comparator generates from the received signals is not useful. For example in a VCO-based PLL circuit, it is not possible to utilize the asymmetrical clock signal generated by the frequency divider disclosed in the above-stated article, but to obtain a useful signal a divider must be used that generates a symmetrical clock signal. Conventional dividers generating a symmetrical clock signal, on the other hand, are too slow for the above application.

Even though the invention has been explained in the foregoing with reference to the examples in accordance with the accompanying drawings, it is evident that the invention is not so restricted, but it can be varied within the scope of the inventive idea set forth in the appended claims. It is obvious to those skilled in the art that the RS flip-flop or RS flip-flop provided with a clock input can be used also in applications other than a frequency divider.

Claims

Claims: 1. An RS flip-flop, comprising

- two inputs (SET2 and RESET2), the first being a setting input (SET2) for setting the flip-flop into state one and the second being a resetting input (RESET2) for resetting the flip-flop to zero state,

- at least one output (Q) whose state constitutes the state of the flip-flop that can be controlled through said inputs, characterized in that the flip-flop further comprises

- two inverters (11' and 12') known per se, cross-connected in such a way that the output (o1 ) of the first inverter (11 ') is operatively connected to the input (i2) of the second inverter (12') and the output (o2) of the second inverter (I2¹) is operatively connected to the input (i1) of the first inverter (11'),

- two control means, the first being connected to the first inverter (11') and the second to the second inverter (I2¹), and said setting input being operatively connected to said first control means and said resetting input being operatively connected to said second control means for forced control of the inverters through the setting and resetting inputs to the desired state, in which case the output (o1 or o2) of at least one inverter is adapted to determine the state of said output.

2. An RS flip-flop as claimed in claim 1, characterized in that both control means consist of one PMOS transistor.

3. An RS flip-flop as claimed in claim 2, characterized in that each inverter consists of two transistors, the flip-flop including a total of six transistors.

4. An RS flip-flop as claimed in claim 1 , additionally comprising a clock input (CLK) for controlling the state of the flip-flop by means of a clock signal supplied to the clock input, characterized in that a third and fourth inverter (11 and 12) are connected ahead of the RS flip-flop (RS_FF), each having an input and output and a voltage supply terminal so that

- the input of each inverter constitutes said clock input (CLK),

- the output of the third inverter is operatively connected to the setting input of the flip-flop (RS_FF) and the output of the fourth inverter is operatively connected to the resetting input of the flip-flop (RS_FF),

- the voltage supply terminal (P1) of the third inverter constitutes a second setting input (SET) for activating the inverter to input the desired clock signal by means of the set signal to the setting input of the flip-flop (RS_FF),

- the voltage supply terminal (P2) of the fourth inverter constitutes a second resetting input (RESET) for activating the inverter to input the desired clock signal by means of the reset signal to the resetting input of the flip-flop (RS_FF).

5. An RS flip-flop as claimed in claim 1 or claim 4, c h a r a c t e r i z e d in that each of said inverters consists of a PMOS and an NMOS transistor.

6. A frequency divider for generating a signal having a substantially symmetrical pulse ratio, said divider comprising a master and slave RS flip-flop and a NOT gate that are connected in such a way that

- the incoming clock signal (CLKjn) can be supplied to the master flip- flop as such and to the slave flip-flop via the NOT gate,

- the outputs (Q and /Q) of the master flip-flop are connected to the inputs (MID2 and /MID2) of the slave flip-flop,

- the outputs (OUT and /OUT) of the slave flip-flop are connected as a feedback to the inputs (RESET and SET) of the master flip-flop,

- the outputs (OUT and /OUT) of the slave flip-flop are outputs of the frequency divider, c h a r a c t e r i z e d in that both the master and the slave flip-flop include an RS flip-flop (RS_FF) having

- two inverters (11' and 12') known per se, cross-connected in such a way that the output (o1) of the first inverter (11') is operatively connected to the input (i2) of the second inverter (I2¹) and the output (o2) of the second inverter (12') is operatively connected to the input (i1) of the first inverter (11'),

- two control means, the first being connected to the first inverter (11') and the second to the second inverter (12') and said setting input being operatively connected to said first control means and said resetting input being operatively connected to said second control means for forced control of the inverter through the setting and resetting inputs to the desired state, in which case the output (o1 or o2) of at least one inverter is adapted to determine the state of the output in the master and slave flip-flops, and that a third and fourth inverter (11 and 12) are connected ahead of the RS flip-flop (RS_FF), each having an input and output and a voltage supply terminal so that - the input of each inverter constitutes said clock input (CLK),

- the output of the third inverter is operatively connected to the setting input of the flip-flop (RS__FF) and the output of the fourth inverter is operatively connected to the resetting input of the flip-flop (RS_FF), - the voltage supply terminal (P1) of the third inverter constitutes a second setting input (SET) for activating the inverter to input the desired clock signal by means of the set signal to the setting input of the flip-flop (RS_FF),