CN110299919A - A kind of low-power consumption ultrahigh speed high-precision adc - Google Patents
A kind of low-power consumption ultrahigh speed high-precision adc Download PDFInfo
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- CN110299919A CN110299919A CN201910787405.7A CN201910787405A CN110299919A CN 110299919 A CN110299919 A CN 110299919A CN 201910787405 A CN201910787405 A CN 201910787405A CN 110299919 A CN110299919 A CN 110299919A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/1205—Multiplexed conversion systems
- H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
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Abstract
The invention discloses a kind of low-power consumption ultrahigh speed high-precision adcs, including input circuit, low speed ADC, 1/16 frequency divider and output circuit, the input circuit is connected with the low speed ADC, the low speed ADC is connected with the output circuit, and 1/16 frequency divider is connected with the input circuit and the low speed ADC respectively；The input circuit samples input signal using the frequency of 1.6GHz；The low speed ADC carries out the acquisition of signal with the frequency of 100MHz from the input circuit;For a kind of low-power consumption adc circuit framework of 10 bit resolution girz sample frequencys constructed in IC chip.
Description
Technical field
The present invention relates to modulus conversion technique fields, are a kind of low-power consumption ultrahigh speed high precision analogue conversions specifically
Device.
Background technique
With the continuous increase of input analog signal bandwidth demand and the increase of the direct sample requirement of radiofrequency signal, surpass
High-speed AD converter (ADC) chip has the huge market demand.
Existing super high-speed A/D C framework mainly have flashing type (Flash), folded interpolating, assembly line (Pipeline) and when
Between interweave etc. frameworks.
Flashing type (Flash) ADC is also referred to as parallel type ADC, and being that industry is simplest may be implemented highest conversion rate
A kind of ADC framework, but with the promotion of resolution ratio, wherein the comparator number needed is exponentially increased, cause chip area and
Power consumption significantly rises.In addition, the imbalance mismatch between large number of comparator will seriously restrict the performance of ADC.
Folded interpolating ADC is the differentiation of flashing type ADC, and its purpose is to reduce the quantity of comparator.In order to realize height
Fast high precision performance, the framework require folding factor high, cause the frequency of folder output signal high, thus to the essence of comparator
Degree and speed propose very high requirement, and design difficulty is big, and power consumption also rises with it.
Pipeline system ADC by the way that the sub- ADC of the low precision of multistage high speed is cascaded, every grade of sub- ADC in the way of assembly line according to
The secondary residual signals to prime carry out quantization conversion, to realize high-speed, high precision performance.With the raising of ADC sample frequency,
In operational amplifier settling time need to accordingly shorten, i.e., band merit increases so that power consumption rise.Especially it is operate on gigahertz (GHZ)
The hereby ADC of sample rate, the operational amplifier in pipelined architecture will consume huge power.
Time-interleaved formula ADC is a kind of framework for realizing super high-speed A/D C more popular in recent years, it utilizes multiple low speed
The work of ADC timesharing alternating sampling is realized and is converted to the high-speed quantization of signal.Low speed ADC therein can there are many frameworks to select,
Different collocation will generate different effects.However, no matter which kind of is arranged in pairs or groups, time-interleaved formula ADC itself is between the mistake low speed ADC
With sampling instant mismatch, imbalance mismatch and gain mismatch etc. more sensitive, be embodied as between low speed ADC.These mismatches are tight
Restrict the performance of time-interleaved formula ADC again.
In conclusion for the demand to low-power consumption ultrahigh speed high-precision adc in the market, currently without a standard architecture
Design, according to different index demands, ADC framework requires targetedly to design.
Summary of the invention
It is one kind in IC chip the purpose of the present invention is to provide a kind of low-power consumption ultrahigh speed high-precision adc
The low-power consumption adc circuit framework of 10 bit resolution girz sample frequencys of building.
The present invention is achieved through the following technical solutions: a kind of low-power consumption ultrahigh speed high-precision adc, including input
Circuit, low speed ADC, 1/16 frequency divider and output circuit, the input circuit are connected with low speed ADC, low speed ADC with it is described defeated
Circuit is connected out, and 1/16 frequency divider is connected with input circuit and low speed ADC respectively；The input circuit, with 1.6GHz's
Frequency samples input signal；The low speed ADC carries out the acquisition of signal with the frequency of 100MHz from input circuit.
Further is that the present invention is better achieved, and especially use following set-up modes: the low speed ADC includes 16 points
When alternating sampling work SAR_ADC, SAR_ADC is all in parallel with input circuit, 1/16 frequency divider control connects SAR_ADC,
SAR_ADC is connected with output circuit.
Further is that the present invention is better achieved, and especially uses following set-up modes: in the reference of any one SAR_ADC
Localized capacitance is all provided at voltage access point.
Further is that the present invention is better achieved, and especially use following set-up modes: 16 SAR_ADC are using same
Reference voltage.
Further is that the present invention is better achieved, and especially use following set-up modes: the input circuit includes mutual
The terminal resistance and input signal processing circuit of connection, and input signal processing circuit is connected with low speed ADC.
It is further for the present invention is better achieved, especially use following set-up modes: the terminal resistance is is connected to
Two of input signal processing circuit input terminal are serially connected and the identical resistance of resistance value.
Further is that the present invention is better achieved, and especially use following set-up modes: the output circuit includes mutual
The digital circuit and Low Voltage Differential Signal output circuit of connection, and the output end of low speed ADC is connected with digital circuit.
Further is that the present invention is better achieved, and especially use following set-up modes: the digital circuit is with 1.6GHz
Frequency output a signal in Low Voltage Differential Signal output circuit.
Further is that the present invention is better achieved, and especially use following set-up modes: the output circuit is using parallel
10 quantization digital codes of mode difference output.
Compared with prior art, the present invention have the following advantages that and the utility model has the advantages that
(1) present invention is a kind of low-power consumption adc circuit frame of 10 bit resolution girz sample frequencys constructed in IC chip
Structure.
(2) present invention is generally directed to the ADC frameworks of 10 bit resolution, 1.6 girz sample frequency to be designed, and realize low
Power consumption ultrahigh speed high-precision adc.
(3) ADC that 10 bit resolutions may be implemented in the present invention works under 1.6 girz sample frequencys, and believes in input
When number frequency is 373 megahertzs, the significance bit (ENOB) of ADC reaches 8.6.
(4) present invention mitigates the mismatch shadow in time-interleaved formula ADC between low speed ADC using Analog Circuit Design technological means
While sound to improve performance, complicated backstage figure adjustment algorithm and additional power consumption are avoided.
(5) the Analog Circuit Design technological means in the present invention to elevating ultrahigh speed high-precision adc, eliminates rear number of units
Word corrects the influence converted to signal quantization, shortens the signal quantization conversion output time.
Detailed description of the invention
Fig. 1 is the principle of the present invention figure.
Fig. 2 is low speed ADC portion schematic diagram of the present invention.
Specific embodiment
The present invention is described in further detail below with reference to embodiment, embodiments of the present invention are not limited thereto.
To keep the purposes, technical schemes and advantages of embodiment of the present invention clearer, implement below in conjunction with the present invention
The technical solution in embodiment of the present invention is clearly and completely described in attached drawing in mode, it is clear that described reality
The mode of applying is some embodiments of the invention, rather than whole embodiments.Based on the embodiment in the present invention, ability
Domain those of ordinary skill every other embodiment obtained without creative efforts, belongs to the present invention
The range of protection.Therefore, the detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit below and is wanted
The scope of the present invention of protection is sought, but is merely representative of selected embodiment of the invention.Based on the embodiment in the present invention,
Every other embodiment obtained by those of ordinary skill in the art without making creative efforts belongs to this
Invent the range of protection.
In the description of the present invention, it is to be understood that, term " center ", " longitudinal direction ", " transverse direction ", " length ", " width ",
" thickness ", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outside", " up time
The orientation or positional relationship of the instructions such as needle ", " counterclockwise " is to be based on the orientation or positional relationship shown in the drawings, and is merely for convenience of
The description present invention and simplified description, rather than the equipment of indication or suggestion meaning or element must have a particular orientation, with spy
Fixed orientation construction and operation, therefore be not considered as limiting the invention.
In addition, term " first ", " second " are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance
Or implicitly indicate the quantity of indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or
Implicitly include one or more of the features.In the description of the present invention, the meaning of " plurality " is two or more,
Unless otherwise specifically defined.
In the present invention unless specifically defined or limited otherwise, term " installation ", " connected ", " connection ", " fixation " etc.
Term shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or integral；It can be mechanical connect
It connects, is also possible to be electrically connected；It can be directly connected, can also can be in two elements indirectly connected through an intermediary
The interaction relationship of the connection in portion or two elements.It for the ordinary skill in the art, can be according to specific feelings
Condition understands the concrete meaning of above-mentioned term in the present invention.
In the present invention unless specifically defined or limited otherwise, fisrt feature second feature "upper" or "lower"
It may include that the first and second features directly contact, also may include that the first and second features are not direct contacts but pass through it
Between other characterisation contact.Moreover, fisrt feature includes the first spy above the second feature " above ", " above " and " above "
Sign is right above second feature and oblique upper, or is merely representative of first feature horizontal height higher than second feature.Fisrt feature exists
Second feature " under ", " lower section " and " following " include that fisrt feature is directly below and diagonally below the second feature, or is merely representative of
First feature horizontal height is less than second feature.
It is worth noting that: it is in this application, certain to need to be applied to techniques known or conventional technical means
When, applicant there may be do not illustrate the well-known technique specifically in the text or/and conventional technical means be it is a kind of what
Technological means, but cannot think the application not announce the technological means in text specifically and not meet Patent Law the 20th
The case where six third item.
Explanation of nouns:
The abbreviation of ADC, Analog-to-Digital Converter refer to A/D converter or analog-digital converter.
SAR_ADC, gradual approaching A/D converter.
The abbreviation of LVDS, Low-Voltage Differential Signaling, refer to low-voltage differential signal (low pressure
Differential signal).
Embodiment 1:
The present invention designs a kind of low-power consumption ultrahigh speed high-precision adc, is a kind of 10 points constructed in IC chip
The low-power consumption adc circuit framework of resolution girz sample frequency especially uses following setting structures as shown in Figure 1 and Figure 2: including
Input circuit, low speed ADC, 1/16 frequency divider and output circuit, input circuit are connected with low speed ADC, low speed ADC and output electricity
Road is connected, and 1/16 frequency divider is connected with input circuit and low speed ADC respectively；The input circuit, with the frequency of 1.6GHz
Input signal is sampled；The low speed ADC carries out the acquisition of signal with the frequency of 100MHz from input circuit.
As scheme is preferable to provide, the low-power consumption ultrahigh speed high-precision adc is mainly by input circuit, low speed
ADC, 1/16 frequency divider and the most of composition of output circuit four, wherein input circuit is reducing signal reflex, guarantees that signal passes
After being introduced in the case where defeated efficiency by signal and being buffered signal, input signal is sampled with the frequency of 1.6GHz,
And it is input to low speed ADC, while the influence caused by signal input part when low speed ADC works is isolated；Low speed ADC is received same
A reference voltage successively obtains signal from input circuit with the frequency of 100MHz, and according to reference voltage to the signal got
Quantization conversion is carried out, 10 digit numeric codes is formed and exports to output circuit；Output circuit, the quantization for receiving low speed ADC export number
Code will further use parallel form by 10 quantization code word difference outputs to the low function after imagining digital code arranging order
It is outer for digital signal processing circuit use to consume ultrahigh speed high-precision adc；1/16 frequency divider, reception frequency are 1.6 GHz
Clock, divided the 100 MHz sub-clocks for 16 phases and be conveyed to low speed ADC, so that low speed ADC realizes that timesharing is alternately adopted
Sample work.
Embodiment 2:
The present embodiment is further optimized based on the above embodiments, herein with previous embodiment technical solution same section
It will not be described in great detail, it is as shown in Figure 1 and Figure 2, further for the present invention is better achieved, especially use following set-up modes: described
Low speed ADC includes the SAR_ADC of 16 timesharing alternating samplings work, and SAR_ADC is all in parallel with input circuit, 1/16 frequency divider control
System connects SAR_ADC, and SAR_ADC is connected with output circuit.
As the scheme that is preferable to provide, low speed ADC is mainly made of the SAR_ADC that 16 timesharing alternating samplings work,
The SAR_ADC of 16 timesharing alternating samplings work is using architecture mode setting in parallel, and the outlet side of input circuit is all with 16
The SAR_ADC of a timesharing alternating sampling work is connected, and the control of 1/16 frequency divider connects 16 timesharing alternating sampling work
The SAR_ADC of SAR_ADC, the work of 16 timesharing alternating samplings are all connected with output circuit；Input circuit receives 1.6 GHz and adopts
Sample clock sample to input signal and Buffer output is received to the low speed SAR_ADC signal that 16 timesharing alternating samplings work
End；It is right after the low speed SAR_ADC of 16 timesharing alternating sampling work receives the 100MHz sampling clock divided through 1/16 frequency divider
The input signal being respectively received carries out alternately time sharing sampling and quantifies conversion output.
Embodiment 3:
The present embodiment is to advanced optimize based on any of the above embodiments, with previous embodiment technical solution same section
It will not be described in great detail herein, it is as shown in Figure 1 and Figure 2, further for the present invention is better achieved, especially use following set-up modes:
It is all provided with localized capacitance at the reference voltage access point of any one SAR_ADC, as scheme is preferable to provide, each
The reference voltage access point of SAR_ADC introduces the dynamic mismatch between localized capacitance (C_DEC) reduction reference voltage, to substantially drop
Gain mismatch between low SAR_ADC, the performance of elevating ultrahigh speed high-precision adc.
Embodiment 4:
The present embodiment is to advanced optimize based on any of the above embodiments, with previous embodiment technical solution same section
It will not be described in great detail herein, it is as shown in Figure 1 and Figure 2, further for the present invention is better achieved, especially use following set-up modes:
16 SAR_ADC use the same reference voltage, as scheme is preferable to provide, to the SAR_ of 16 timesharing alternating samplings work
ADC provides unified reference voltage (VREF_L16(is preferably 0.4V)) to eliminate quiescent voltage mismatch.
Embodiment 5:
The present embodiment is to advanced optimize based on any of the above embodiments, with previous embodiment technical solution same section
It will not be described in great detail herein, it is as shown in Figure 1 and Figure 2, further for the present invention is better achieved, especially use following set-up modes:
The input circuit includes terminal resistance and input signal processing circuit interconnected, and input signal processing circuit and low speed
ADC is connected.
As the scheme that is preferable to provide, input circuit uses terminal resistance interconnected and input signal processing circuit institute
It constitutes, wherein terminal resistance is mounted on input signal processing circuit input both ends, the terminal as high speed transmission of signals link
Match, reduce reflection, guarantees effectiveness；Input signal processing circuit, realizes the sampling and buffering of input signal, receive to
The analog input signal for quantifying conversion, after input signal is buffered, adopts input signal with the frequency of 1.6 GHz
Sample, and it is output to the low speed ADC of rear class timesharing alternation, while being isolated when low speed ADC works caused by signal input part
It influences.
Embodiment 6:
The present embodiment is to advanced optimize based on any of the above embodiments, with previous embodiment technical solution same section
It will not be described in great detail herein, it is as shown in Figure 1 and Figure 2, further for the present invention is better achieved, especially use following set-up modes:
The terminal resistance is to be connected to two of input signal processing circuit input terminal to be serially connected and the identical resistance of resistance value.
As the scheme that is preferable to provide, there are two the identical resistance of resistance value (R1, R2) series connection to be constituted for terminal resistance, preferably
Use 50 Ω resistance.
Embodiment 7:
The present embodiment is to advanced optimize based on any of the above embodiments, with previous embodiment technical solution same section
It will not be described in great detail herein, it is as shown in Figure 1 and Figure 2, further for the present invention is better achieved, especially use following set-up modes:
The output circuit includes digital circuit interconnected and Low Voltage Differential Signal output circuit, and the output end of low speed ADC with
Digital circuit is connected.
As the scheme that is preferable to provide, output circuit uses digital circuit interconnected and Low Voltage Differential Signal (LVDS)
Output circuit is constituted, and the SAR_ADC of 16 timesharing alternating sampling work receives the same reference voltage (VREF_L16), with
The frequency of 100 MHz successively obtains signal from input signal processing (buffering/sampling) circuit, and according to reference voltage to getting
Signal carry out quantization conversion, form 10 digit numeric codes and export to digital circuit；Digital circuit receives 16 timesharing alternating samplings
The quantization of the SAR_ADC of work exports digital code, by after these digital code arranging orders with the rate-adaptive pacemaker of 1.6 GHz to low pressure
Differential signal (LVDS) output circuit；Low Voltage Differential Signal (LVDS) output circuit receives the digital code of 1.6 GHz frequencies transmission,
10 quantization code word difference outputs to chip (the low-power consumption ultrahigh speed high-precision adc) are supplied outside in a parallel fashion
Digital signal processing circuit uses；1/16 frequency divider receives the clock that frequency is 1.6 GHz, and being divided is the 100 of 16 phases
MHz sub-clock is conveyed to 16 SAR_ADC, so that SAR_ADC realizes the work of timesharing alternating sampling.
Embodiment 8:
The present embodiment is to advanced optimize based on any of the above embodiments, with previous embodiment technical solution same section
It will not be described in great detail herein, it is as shown in Figure 1 and Figure 2, further for the present invention is better achieved, especially use following set-up modes:
The digital circuit is output a signal in Low Voltage Differential Signal output circuit with the frequency of 1.6GHz.
Embodiment 9:
The present embodiment is to advanced optimize based on any of the above embodiments, with previous embodiment technical solution same section
It will not be described in great detail herein, it is as shown in Figure 1 and Figure 2, further for the present invention is better achieved, especially use following set-up modes:
The output circuit uses 10 quantization digital codes of parallel mode difference output.
Embodiment 10:
The present embodiment is to advanced optimize based on any of the above embodiments, with previous embodiment technical solution same section
It will not be described in great detail herein, it is as shown in Figure 1 and Figure 2, further for the present invention is better achieved, especially use following set-up modes:
A kind of low-power consumption ultrahigh speed high-precision adc, by terminal resistance (two 50 Ohmic resistances are in series), input
The low speed SAR ADC that signal buffer/sample circuit (input signal processing circuit), 16 timesharing alternating samplings work
(SAR_ADC), digital circuit, Low Voltage Differential Signal (LVDS) output circuit and 1/16 frequency divider are constituted.
Terminal resistance is mounted on buffer input signal/sample circuit signal input both ends；Buffer input signal/sample circuit
Receive the low speed that 1.6 GHz sampling clocks sample to input signal and Buffer output works to 16 timesharing alternating samplings
SAR_ADC signal receiving end；The low speed SAR_ADC of 16 timesharing alternating sampling work receives 100 divided through 1/16 frequency divider
After MHz sampling clock, alternately time sharing sampling is carried out to the input signal being respectively received and quantifies conversion output；Digital circuit connects
It receives 100 MSPS digital signals of the low speed SAR_ADC quantization conversion of 16 timesharing alternating sampling work and is ranked up arrangement
Afterwards, with the rate-adaptive pacemaker of 1.6 GHz to Low Voltage Differential Signal (LVDS) output circuit；Ultrahigh speed high-precision adc
(ADC) final 10 quantization digital codes by Low Voltage Differential Signal (LVDS) output circuit in a parallel fashion difference output to chip
It is outer to be used for digital signal processing circuit.
When in use:
1, user installs ultrahigh speed high-precision adc (abbreviation ADC directly below) of the invention according to use environment,
Every a pair of of difference output end (D0P/D0N ~ D9P/D9N) of Low Voltage Differential Signal (LVDS) output circuit mounts build-out resistor and makees
Signal transmission matching；
2, after the completion of step 1, ADC of the invention is accessed into power supply；
3, after the completion of step 2, the differential analog signal of conversion to be quantified is accessed to ADC input terminal (VINP/ of the invention
VINN)；
4, after the completion of step 3, ADC of the invention will voluntarily complete the conversion of input analog signal to digital signal, and low
Pressure difference sub-signal (LVDS) output circuit output end (D0P/D0N ~ D9P/D9N) output, user only need to be in Low Voltage Differential Signal
(LVDS) output circuit output end (D0P/D0N ~ D9P/D9N) obtains 10 ADC quantization conversion output digital codes, transfers rear end
Carry out digital processing.
5, voluntarily quantizing process undergoes following steps to ADC of the invention:
A) analog signal of Differential Input dissipates on terminal resistance, guarantee signal by it is low reflection, it is efficient in a manner of enter
In buffer input signal/sample circuit；
B) it after input signal processing (buffering/sampling) circuit receives differential analog signal, by the signal buffer and samples,
It is delivered to the public input terminal of low speed SAR_ADC of 16 timesharing alternating samplings work；
C) the low speed SAR_ADC of 16 timesharing alternating samplings work successively carries out sampling quantity to the signal on its public input terminal
Change conversion, is respectively formed 16 groups 10 digital code transformation results and send to digital circuit processing；
D) the analog signal figure code that digital circuit receives 16 groups 10 carries out arranging order, forms 1 group 10 high-speed figures
Code is output to Low Voltage Differential Signal (LVDS) output circuit；
E) 10 high-speed figure codes that Low Voltage Differential Signal (LVDS) output circuit transmits digital circuit are exported to ADC
Chip is outer for circuit subsequent processing.
In actual use, specific embodiment are as follows:
(1) starting up's process
User installs ADC of the invention according to use environment, in every a pair of of difference of Low Voltage Differential Signal (LVDS) output circuit
Output end (D0P/D0N ~ D9P/D9N) mounts 100 Ω build-out resistors and makees signal transmission matching.It mounts and completes in build-out resistor
Afterwards, ADC of the invention is accessed into 1.9 V power supplys.After the completion of ADC plant-grid connection, by the differential analog signal of conversion to be quantified
Access ADC input terminal (VINP/VINN) of the invention；
(2) signal quantization conversion process
After the completion of ADC starting up, the differential analog signal that the maximum amplitude of oscillation is 0.4V is input to ADC input terminal (VINP/
VINN).The mounting of ADC input terminal, with matched signal source impedance, reduces reflection by terminal resistance that two 50 Ω are connected in series, improves
Effectiveness.
After the input signal of conversion to be quantified is efficiently transferred to input signal processing (buffering/sampling) circuit, input letter
Number buffering/sample circuit will buffer input signal with the gain of 0dB, and with the work clock of 1.6 GHz to buffering after
Signal sampled.Signal after sampled is discretized, and is formed " step " shape and is supplied subsequent 16 timesharing alternating sampling work
The low speed SAR_ADC of work is used.The method of sampling eliminates the sampling instant mismatch in time-interleaved formula ADC between low speed ADC, energy
Effectively promote the performance of ADC.The bandwidth Design that input signal handles (buffering/sampling) circuit is 4 GHz, guarantees input signal frequency
When rate is 373 MHz, " step " signal after sampling has the very high linearity.
" step " signal after input signal handles (buffering/sampling) circuit sampling is transported to 16 timesharing and alternately adopts
The public input terminal of low speed SAR_ADC of sample work, 16 low speed SAR_ADC are according to the sampling clock (CLK_L00 being respectively received
~ CLK_L15), successively " step " of different moments on public input terminal is adopted into therein, and according to itself received ginseng
It examines voltage and quantization conversion is carried out to " step ", form 10 digit numeric codes with the frequency of 100 MHz and be transferred to digital circuit.The present invention
In, 16 low speed SAR_ADC use successive approximation (SAR) framework, and the feature for making full use of SAR_ADC oneself power consumption low is come real
Existing low-power consumption ultrahigh speed high-precision adc (ADC) of the invention.
In order to solve the imbalance mismatch in time-interleaved formula ADC between low speed ADC, the present invention works in timesharing alternating sampling
Itself offset correction is added in SAR_ADC, the reduction of SAR_ADC imbalance is realized using charge storage technology, to reach mitigation
The purpose for mismatch of lacking of proper care.In the present invention, SAR_ADC quantifies to convert every time and starts to need 1ns protecting to complete itself offset correction
Card SAR_ADC has enough time to complete under conditions of quantifying conversion to 10 digit numeric codes for adopting " step " signal, SAR_ADC's
Working frequency is set to 100 MHz.It can obtain accordingly, need 16 such SAR_ADC timesharing alternating sampling work to constitute 1.6
The super high-speed A/D C of the sample frequency of GHz.
When SAR_ADC carries out quantization conversion to the signal sampled, a reference voltage is needed.The voltage DC value and poor
Divide the input signal maximum amplitude of oscillation consistent, is 0.4 V in the present invention.However, in SAR_ADC quantization conversion process, reference voltage
It will receive circuit influence to fluctuate, and same design has deviation after finalization of the manufacture, therefore, independently mentions in actual circuit
It supplies between the reference voltage of each timesharing alternating sampling work SAR_ADC that there are mismatches, i.e. gain mismatch, leads to time-interleaved formula
The decline of ADC performance.In the present invention, unified reference voltage is provided to disappear to the SAR_ADC of 16 timesharing alternating samplings work
Localized capacitance (C_DEC) reduction reference voltage is introduced except quiescent voltage mismatch, and in the reference voltage access point of each SAR_ADC
Between dynamic mismatch, so that the gain mismatch between low speed SAR_ADC be greatly reduced, the performance of elevating ultrahigh speed high-precision adc.
The low speed SAR_ADC of 16 timesharing alternating samplings work quantifies successively to adopt into respective internal " step " letter respectively
Number, 10 digit numeric code transformation results of 16 groups of parallel transmissions are formed, are sent with the renewal frequency of 100 MHz to digital circuit processing.
After digital circuit receives 10 digit numeric codes of this 16 groups of parallel transmissions, arranging order will be carried out to these digital codes, and with 1.6
The renewal frequency of GHz is transported to Low Voltage Differential Signal (LVDS) output circuit.In the present invention, digital circuit is in ultrahigh speed high-precision
Only make data arranging order in ADC, the mismatch influence between low speed SAR_ADC is solved by Analog Circuit Design technological means.
Compared to the ultrahigh speed high-precision adc framework using backstage figure adjustment algorithm, the digital circuit in the present invention is easy, scale
Small, power consumption is low, and does not need the additional time to correct the digital code that low speed ADC is transmitted, signal quantization conversion
It is short to export the time.
The digital code for 10 1.6 GSPS that Low Voltage Differential Signal (LVDS) output circuit comes to digital circuit transmission into
Row processing is transformed to handle outside output to ADC chip for user after current signal.
(3) quantify transformation result receive process
ADC starting up completes, and after differential analog signal is input to ADC input terminal (VINP/VINN) by user, ADC is to input
The quantization conversion of signal will carry out automatically.Digital code is converted in the quantization for the input signal that current time samples, and is quantified by ADC
Conversion needed for time delay after will appear in ADC Low Voltage Differential Signal (LVDS) output circuit output port (D0P/D0N ~
D9P/D9N).User only need to be articulated in Low Voltage Differential Signal (LVDS) output circuit output end (D0P/D0N ~ D9P/ for each
After the differential voltage at 100 Ω build-out resistor both ends D9N) obtains together, transfers rear end and carry out digital processing.
The above is only presently preferred embodiments of the present invention, not does limitation in any form to the present invention, it is all according to
According to technical spirit any simple modification to the above embodiments of the invention, equivalent variations, protection of the invention is each fallen within
Within the scope of.
Claims (9)
1. a kind of low-power consumption ultrahigh speed high-precision adc, it is characterised in that: including input circuit, low speed ADC, 1/16 point
Frequency device and output circuit, the input circuit are connected with the low speed ADC, and the low speed ADC is connected with the output circuit
It connects, 1/16 frequency divider is connected with the input circuit and the low speed ADC respectively；The input circuit, with 1.6GHz
Frequency input signal is sampled；The low speed ADC carries out signal with the frequency of 100MHz from the input circuit
It obtains.
2. a kind of low-power consumption ultrahigh speed high-precision adc according to claim 1, it is characterised in that: the low speed
ADC includes the SAR_ADC of 16 timesharing alternating samplings work, and the SAR_ADC is all in parallel with the input circuit, and described 1/16
Frequency divider control connects the SAR_ADC, and the SAR_ADC is connected with the output circuit.
3. a kind of low-power consumption ultrahigh speed high-precision adc according to claim 2, it is characterised in that: at any one
Localized capacitance is all provided at the reference voltage access point of the SAR_ADC.
4. a kind of low-power consumption ultrahigh speed high-precision adc according to claim 3, it is characterised in that: described in 16
SAR_ADC uses the same reference voltage.
5. a kind of low-power consumption ultrahigh speed high-precision adc according to claim 1 or 2 or 3 or 4, feature exist
In: the input circuit includes terminal resistance and input signal processing circuit interconnected, and input signal processing is electric
Road is connected with the low speed ADC.
6. a kind of low-power consumption ultrahigh speed high-precision adc according to claim 5, it is characterised in that: the terminal
Resistance is to be connected to two of the input signal processing circuit input terminal to be serially connected and the identical resistance of resistance value.
7. a kind of low-power consumption ultrahigh speed high-precision adc, feature described according to claim 1 or 2 or 3 or 4 or 6
Be: the output circuit includes digital circuit interconnected and Low Voltage Differential Signal output circuit, and the low speed ADC
Output end is connected with the digital circuit.
8. a kind of low-power consumption ultrahigh speed high-precision adc according to claim 7, it is characterised in that: the number
Circuit is output a signal in the Low Voltage Differential Signal output circuit with the frequency of 1.6GHz.
9. a kind of low-power consumption ultrahigh speed high-precision adc described according to claim 1 or 2 or 3 or 4 or 6 or 8, special
Sign is: the output circuit uses 10 quantization digital codes of parallel mode difference output.
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Cited By (2)
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| CN111555754A (en) * | 2020-05-26 | 2020-08-18 | 成都铭科思微电子技术有限责任公司 | Metastable state detection circuit applied to synchronous clock sampling of high-speed analog-to-digital converter |
| CN116633331A (en) * | 2023-07-21 | 2023-08-22 | 成都铭科思微电子技术有限责任公司 | Switching circuit capable of switching positive and negative voltage complementary output |
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| CN110299919B (en) | 2019-12-13 |
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