CN101388669A - Parallel type analog-to-digital conversion circuit, sampling circuit and comparison amplification circuit - Google Patents
Parallel type analog-to-digital conversion circuit, sampling circuit and comparison amplification circuit Download PDFInfo
- Publication number
- CN101388669A CN101388669A CNA2008101608038A CN200810160803A CN101388669A CN 101388669 A CN101388669 A CN 101388669A CN A2008101608038 A CNA2008101608038 A CN A2008101608038A CN 200810160803 A CN200810160803 A CN 200810160803A CN 101388669 A CN101388669 A CN 101388669A
- Authority
- CN
- China
- Prior art keywords
- switch
- amplifier
- terminal
- capacitor
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
A parallel type analog-to-digital conversion circuit, includes a reference signal generating portion and a comparison amplification portion, the comparison amplification portion including a plurality of amplifiers, input resetting switches, first sampling capacitors, second sampling capacitors, first sampling switches, and second sampling switches.
Description
Technical field
The present invention relates to a kind of parallel analog to digital conversion circuit and be used for wherein sample circuit and amplifying circuit relatively.
Background technology
Up to now, known a kind of sample circuit that is used for the bias voltage of erase amplifier, this amplifier are used for amplification input signal and export the input signal that is exaggerated like this.Figure 19 A is a kind of circuit diagram of representing the configuration of this sample circuit, and Figure 19 B is a kind of sequential chart that is used to explain the built-in function of this sample circuit.
The configuration of the sample circuit shown in Figure 19 A is described below.That is, input signal Vin is imported into the input side of amplifier A100 by switch SW100, and the input side of amplifier A100 is suitable for being connected to earth potential (being ground connection in this case) by switch SW101.And the terminal of capacitor C100 is connected to the lead-out terminal of amplifier A100, and another terminal of capacitor C100 and earth potential () between provide switch SW102.
Sample circuit 100 was operated according to two stages of reset phase and signal output stage, and the bias voltage of erase amplifier A100 and the input signal Vin that is amplified to amplifier A100.Promptly, shown in Figure 19 B, at reset phase (time period from t1 to t2 and the time period from t3 to t4), each among switch SW101 and the SW102 all remains on the state of connection (connection) does not have input voltage vin to be transfused to state to amplifier A100 so that provide a kind of.In this case, capacitor C100 is recharged based on the bias voltage of amplifier A100, and therefore the bias voltage of amplifier A100 is sampled by this capacitor C100.Afterwards, at signal output stage (time period from t2 to t3 and the time period from t4 to t5), each among switch SW101 and the SW102 all remains on disconnection (OFF) state, and switch SW100 remains on the state of connection.In this case, this input signal Vin is imported into amplifier A100, and the output signal Vo1 that is obtained by this input signal of amplification Vin in amplifier A100 is output from this amplifier A100.And, export by capacitor C100 by the output signal Vo2 that bias voltage obtained that from output signal Vo1, deducts amplifier A100.
At this, a kind of to have the comparison amplifying circuit of following the tracks of and keeping (T/H) function be exactly one of every kind of such circuit of constructing by the principle of using sample circuit 100.Figure 20 A is the circuit diagram of the configuration of a kind of relatively more stubborn amplifying circuit of the prior art of expression.
The configuration of comparison amplifying circuit is described below.Promptly, shown in Figure 20 A, input signal Vin and reference signal Vr are input to amplifier A110 by switch SW110 and SW111 and capacitor C110, and the input side of amplifier A110 is suitable for being connected to earth potential (being ground in this case) by switch AW112.On the other hand, the terminal of capacitor C111 is connected to the lead-out terminal of amplifier A110, and switch SW113 be arranged on another terminal of capacitor C111 and earth potential () between.
And shown in Figure 20 B, relatively amplifying circuit 110 is according to two stages operatings of reset phase and signal output stage.
At reset phase, each among switch SW110, SW112 and the SW113 all remains on the state of connection, and SW111 remains on off-state.At this moment, as the capacitor C110 of the capacitor that is used for comparison based on input signal Vin by and be recharged, and the voltage of input signal Vin is sampled by capacitor C110.And providing a kind of does not have input signal Vin to be transfused to state to amplifier A100.As a result, capacitor C111 is recharged based on the bias voltage of amplifier A110, and therefore the bias voltage of amplifier A110 is sampled by this capacitor C110.
At the signal output stage, each among switch SW110, SW112 and the SW113 all remains on off-state, and switch SW111 remains on the state of connection.Therefore, the output signal Vo1 that is obtained by the voltage difference between amplification input signal Vin in amplifier A110 and the reference signal Vr is output from this amplifier A110.And, export by capacitor C110 by the output signal Vo2 that bias voltage obtained that from output signal Vo1, deducts amplifier A110.
This relatively amplifying circuit 110 for example is used in parallel analog to digital conversion circuit 120 grades.Figure 21 is the circuit diagram of the configuration in the parallel analog to digital conversion circuit 120 in the expression prior art.
Now, as shown in figure 21, parallel analog to digital conversion circuit 120 usually by use only be used for resolution will comparison amplifying circuit structure (for example, in the analog to digital conversion circuit of n bit, (2n-1) individual relatively amplifying circuit).But, recently, use the parallel analog to digital conversion circuit (being referred to as " the parallel analog to digital conversion circuit of interpolation " once) of a kind of resistance interpositioning or a kind of electric capacity interpositioning to cause attention.The parallel analog to digital conversion circuit of this interpolation for example has description in publication number is the open text of Japan Patent of JP2003-100774.
At this, shown in Figure 22 is a kind of configuration of using the parallel analog to digital conversion circuit of interpolation of electric capacity interpositioning.Use the comparison amplifier section 132 of electric capacity interpositioning to be configured in the parallel analog to digital conversion circuit of the interpolation shown in Figure 22.It is pointed out that for convenience and understand, only illustrate the part of this comparison amplifier section 132 at this with being convenient to.
Relatively amplifier section 132 produces in voltage difference respectively and is created on the reference signal Vra that generates in the reference signal generating portion and voltage difference Vs1 and the Vs2 between Vrb and the input signal Vin among part 133a and the 133b.
In the first amplifier group 134, voltage difference Vs1 and Vs2 are exaggerated respectively in some amplifier A130a and A130b, and the intermediate voltage between voltage difference Vs1 and Vs2 is exaggerated at amplifier A130c.
The second amplifier group 135 comprises that a plurality of amplifier A131a to A131c are used for amplifying the voltage from the amplifier 130a to 130c of the first amplifier group 134.In addition, the second amplifier group 135 comprises a plurality of amplifier A131d and A131e, is respectively applied for amplification from the intermediate voltage between the output voltage of amplifier A130a and A130c and from the intermediate voltage between the output voltage of amplifier A130b and A130c.
Output signal from amplifier A131a to A131e is output by a capacitor Ca and two capacitor Cb.Each output signal from amplifier A131a to A131e is output after each bias voltage of amplifier A131a to A131e is eliminated by capacitor Ca.In addition, each all is connected with each other by two capacitor Cb adjacent amplifier (for example, amplifier A131a and 131d, and amplifier A131d and A131b).Therefore, all be eliminated and form (composed) each other from the output signal of adjacent amplifier and be output afterwards at its bias voltage.At this moment, the capacitance of capacitor Cb is half of capacitor Ca, this causes between from amplifier A131a and the A131c intermediate voltage between the output voltage, the intermediate voltage between from amplifier A131b and A131e between the output voltage and between from amplifier A131e and A131c each in the intermediate voltage between the output voltage all export by corresponding capacitor Cb.
Output voltage by capacitor Ca and Cb output successfully is latched in latching in the latch cicuit in the part in the next stage.And carry out based on being coded in the encoder of the latch mode in the latch cicuit, obtain digital signal thus.
Relatively the quantity of the amplifier in the amplifier section can be reduced owing to adopted the sort circuit configuration in the parallel analog to digital conversion circuit of interpolation.
Summary of the invention
But, state in the use in the parallel analog to digital conversion circuit of interpolation of electric capacity interpositioning, each amplifier A131a to A131e also must drive two capacitor Cb that are used for interpolation except the capacitor Ca that necessity drives.That is to say that the load that is applied on each amplifier doubles.
The load that is applied to each amplifier A131a to A131e is the twice of above-mentioned situation, this causes the electric current in each amplifier A131a to A131e to double, and each exports chip width (the W)/chip length (L) of driving transistors than also needing to double in amplifier A131a to A131e.
Therefore, when above-mentioned relatively amplifying circuit was used to use in the parallel analog to digital conversion circuit of interpolation of electric capacity interpositioning, the quantity of amplifier can reduce in the parallel analog to digital conversion circuit of interpolation.But, may be not enough to realize reducing power consumption and minimizing area in some cases.This is applicable to and uses resistance interpositioning, electric capacity interpositioning or the parallel analog to digital conversion circuit of interpolation of another kind of interpositioning and the parallel analog to digital conversion circuit of interpolation of use electric capacity interpositioning.
The present invention has been proposed in order to address the above problem, therefore a kind of parallel analog to digital conversion circuit and use therein relatively amplifying circuit and sample circuit need be provided, wherein, this parallel analog to digital conversion circuit can be realized lower power consumption and less area by the quantity of step-down amplifier.
In order to realize above-mentioned needs, according to embodiments of the invention, provide a kind of parallel analog to digital conversion circuit, comprising:the reference signal generating portion is used for a plurality of reference signals that formation voltage differs from one another; Relatively amplifier section is used to amplify by described a plurality of reference signals of described reference signal generating unit branch generation and the voltage difference between the input signal; And exports the voltage difference that is exaggerated like this.Described relatively amplifier section comprises:a plurality of amplifiers; Be connected respectively to described a plurality of amplifier input terminal and be adapted such that each the invalid input replacement switch of input signal of described a plurality of amplifiers; First sampling capacitor that comprises a terminal on the lead-out terminal that is connected respectively to described a plurality of amplifiers; Second sampling capacitor that comprises a terminal on the lead-out terminal that is connected respectively to described a plurality of amplifiers, and be arranged on the another terminal of described first sampling capacitor and comprise the first sampling switch between the part of predetermined potential. should compare amplifier section and also comprise the another terminal that is arranged on described the second sampling capacitor and comprise the second sampling switch between the part of predetermined potential; Wherein be used for each of described input replacement switch and the described first sampling switch being remained on the control operation of on-state section one period preset time and being used for the control operation that each described second sampling switch remains on on-state section one period preset time is alternately carried out, so that alternately be output by described first sampling capacitor and by described second sampling capacitor corresponding to the signal of the voltage difference between described input signal and described reference signal
According to another embodiment of the invention, a kind of sample circuit comprises: the amplifier that is used for amplification input signal; Input replacement switch comprises a terminal that is connected to described amplifier input terminal and is adapted such that the input signal that arrives described amplifier is invalid; And a plurality of capacitors, comprise a terminal of the lead-out terminal that each all is connected to described amplifier.Described sample circuit also comprises a plurality of sampling switchs, be separately positioned on another terminals of described a plurality of capacitors and each all comprises between the part of predetermined potential, wherein, each all remains on the state of connection after one period given time period one or more sampling switchs in described input replacement switch and described a plurality of sampling switch, in described a plurality of sampling switch remaining be one or more to be switched to one period given time period of on-state, makes that alternately the another terminal of the one or more capacitors by described a plurality of capacitors and the another terminal of all the other capacitors are output corresponding to the signal of input signal for each.
According to still another embodiment of the invention, be used to export comparison amplifying circuit, comprise: amplifier corresponding to the signal of the voltage difference between input signal and reference signal; The capacitor that is used for comparison comprises a terminal that is connected to described amplifier input terminal; The switch that is used for input signal comprises being used for a terminal of another terminal that is connected to the described capacitor that is used for comparison input signal is input to described amplifier.This comparison amplifying circuit also comprises: be used for the switch of reference signal, comprise a terminal of another terminal that is connected to the described capacitor that is used for comparison, be used for reference signal is input to described amplifier; Input replacement switch comprises a terminal that is connected to described amplifier input terminal, is used to make the input signal that obtains described amplifier invalid; And a plurality of sampling capacitors, comprise a terminal of the lead-out terminal that each all is connected to described amplifier.This comparison amplifying circuit also comprises: a plurality of sampling switchs are separately positioned on another terminals of described a plurality of sampling capacitors and each all comprises between the part of predetermined potential; Wherein, each of described switch that is used for input signal and described input replacement switch and the described switch that is used for reference signal are alternately connected, and each and one or more all the other switchs of one or more switchs of described a plurality of sampling switchs, with the operation of each and the described switch that is used for reference signal of described switch that is used for input signal and described input replacement switch synchronously, alternately connected, and corresponding to the signal of the voltage difference between described input signal and described reference signal the alternately one or more switchs by described a plurality of sampling switchs and one or how all the other switchs are output
Description of drawings
Fig. 1 is the circuit diagram of expression according to the configuration of the sample circuit of the embodiment of the invention;
Fig. 2 A, 2B and 2C are respectively the sample circuit sequential charts that are in circuit diagram, the circuit diagram that sample circuit is in second stage of phase I and are used to explain the built-in function of sample circuit according to an embodiment of the invention;
Fig. 3 represents according to an embodiment of the invention the relatively circuit diagram of the configuration of amplifying circuit;
Fig. 4 A, 4B and 4C be respectively according to an embodiment of the invention relatively amplifying circuit be in the sequential chart that circuit diagram, the comparison amplifying circuit of phase I are in the circuit diagram of second stage and are used to explain the built-in function of comparison amplifying circuit;
Fig. 5 is the circuit diagram of the parallel analog to digital conversion circuit of interpolation according to an embodiment of the invention;
Fig. 6 is used to explain the sequential chart of the built-in function of the parallel analog to digital conversion circuit of interpolation according to an embodiment of the invention;
Fig. 7 is the circuit diagram of the parallel analog to digital conversion circuit of electric capacity interpolation according to an embodiment of the invention;
Fig. 8 is the circuit diagram of the parallel analog to digital conversion circuit of single according to an embodiment of the invention imported electric current interpolation;
Fig. 9 is the circuit diagram of the parallel analog to digital conversion circuit of the imported electric current interpolation of difference (differential) according to an embodiment of the invention;
Figure 10 is the circuit diagram of the configuration of the amplifier in the parallel analog to digital conversion circuit of electric current interpolation shown in the presentation graphs 8;
Figure 11 is the circuit diagram of the configuration of the amplifier in the parallel analog to digital conversion circuit of electric current interpolation shown in the presentation graphs 9;
Figure 12 represents the configuration circuit figure of the parallel analog to digital conversion circuit of electric capacity interpolation according to an embodiment of the invention;
Figure 13 explains the sequential chart of the built-in function of the parallel analog to digital conversion circuit of electric capacity interpolation according to an embodiment of the invention;
Figure 14 represents the circuit diagram of the configuration of the part of the parallel analog to digital conversion circuit of electric capacity interpolation according to an embodiment of the invention;
Figure 15 A to 15H is a sequential chart of explaining the built-in function of the parallel analog to digital conversion circuit of electric capacity interpolation shown in Figure 13;
Figure 16 A and 16B are respectively the block diagrams of explaining that the operation of the amplifier section be used for the parallel analog to digital conversion circuit of electric capacity interpolation shown in Figure 13 and latch cicuit stops to control;
Figure 17 A to 17H is the block diagram that the operation of the amplifier section of the parallel analog to digital conversion circuit of electric capacity interpolation shown in explanation Figure 13 stops to control
Figure 18 is the configuration circuit figure that represents the parallel analog to digital conversion circuit of electric capacity interpolation according to another embodiment of the invention;
Figure 19 A and 19B are respectively the sequential charts of the interpolation operation of sample circuit in the circuit diagram of configuration of expression sample circuit of the prior art and the expression prior art;
Figure 20 A and 20B are respectively the sequential charts of representing the circuit diagram of the relatively configuration of amplifying circuit of the prior art and representing to compare in the prior art interpolation operation of amplifying circuit;
Figure 21 is the circuit diagram of the configuration of the extraordinary parallel analog to digital conversion circuit of expression prior art; And
Figure 22 is the circuit diagram of the configuration of the parallel analog to digital conversion circuit of interpolation of use electric capacity interpositioning in the expression prior art.
Embodiment
Describe sample circuit, comparison amplifying circuit below with reference to accompanying drawings in detail and comprise described sample circuit and the described relatively embodiment of the parallel analog to digital conversion circuit of amplifying circuit according to the embodiment of the invention.For the ease of the purpose of understanding, the order according to sample circuit, comparison amplifying circuit and parallel analog to digital conversion circuit is described below with reference to accompanying drawings.According in sample circuit of the present invention, comparison amplifying circuit and the parallel analog to digital conversion circuit each both can be single imported, also can be that difference (differential) is imported.But, the imported circuit of difference is equivalent to sample circuit type circuit respectively aspect equivalent electric circuit.Therefore, for the ease of understanding, will only be described as an example (from the angle of equivalent electric circuit, they also can be referred to as the imported circuit of difference) below by providing single imported circuit.
At first, with reference to Fig. 1, Fig. 2 A to 2C sample circuit is according to an embodiment of the invention described.Fig. 1 is the circuit diagram of expression according to the configuration of the sample circuit of the embodiment of the invention; And Fig. 2 A, 2B and 2C are respectively the sample circuit sequential charts that are in circuit diagram, the circuit diagram that sample circuit is in second stage of phase I and are used to explain the built-in function of sample circuit according to an embodiment of the invention;
As shown in Figure 1, the sample circuit 1 of present embodiment comprises: amplifier A1, as the switch SW1 that is used for the switch of input signal, as the switch SW2 of input replacement switch, as the capacitor C1 of first and second sampling capacitors and C2 and as the switch SW3 and the SW4 of the first and second sampling switchs.In this case, amplifier A1 amplification input signal Vin.Switch SW1 is arranged between the input terminal of input signal Vin and amplifier A1, and switch SW2 is arranged on the input terminal of amplifier A1 and have between the part of predetermined potential (in this case for earth potential).Capacitor C1 and C2 have a terminal of each lead-out terminal that is connected to amplifier A1.And switch SW3 and SW4 are separately positioned on another terminal of capacitor C1 and C2 and each all has between the part of predetermined potential (being earth potential in this case).It is pointed out that switch SW2 as input replacement switch be a kind of be used to make obtain the invalid switch of amplifier A1 input signal, and therefore under the imported situation of difference, preferably connect between the difference input terminal of amplifier A1.
Shown in Fig. 2 A, 2B and 2C, sample circuit 1 was operated repeatedly in phase I (referring to Fig. 2 A) and second stage (referring to Fig. 2 B).
At phase I (from t1 to t2 and t3 to time period of t4), shown in Fig. 2 A and 2C, sample circuit 1 remains on off-state with each switch SW2 and SW3, and switch SW1 and SW4 is remained on the state of connection.Input signal Vin is imported into the input terminal of amplifier A1, and exports from amplifier A1 by the output signal Vo1 that amplification input signal Vin is obtained.In addition, the second stage before the phase I is carried out in operation, each switch SW2 and SW3 are maintained at the state of connection, and therefore the bias voltage Vx of amplifier A1 is sampled by capacitor C1.Therefore, switch SW3 disconnects (disconnection), and this causes output signal output Vo21 (Vo1-Vx), and this output signal obtains by deducting from output signal Vo1 by described capacitor C1 bias voltage Vx that sampled, amplifier A1.On the other hand, because switch SW4 is maintained at the state of connection, capacitor C2 is recharged based on the output signal Vo1 that exports from amplifier A1, and the voltage of output signal Vo1 is sampled by capacitor C2.
Next second stage (for example from t2 to t3 and t4 to time period of t5), shown in Fig. 2 B and 2C, sample circuit 1 remains on on-state with each switch SW2 and SW3, and switch SW1 and SW4 is remained on the state of disconnection.Therefore, do not have input signal Vin to be imported into the input terminal of amplifier A1, and therefore the input terminal of amplifier A1 is arranged on ground potential by switch SW2.In addition, because switch SW3 remains on the state of connection, capacitor C1 is recharged based on the bias voltage Vx of amplifier A1, and therefore the bias voltage Vx of amplifier A1 is sampled by capacitor C1.On the other hand, because capacitor C2 remains on unsteady (floating) state, therefore deduct the output signal Vo22 (Vx-Vo1) that the output signal Vo1 that sampled in the phase I by described capacitor C2 obtains and be output by bias voltage Vx from amplifier A1.
By this way, in the amplifier A1 of this embodiment, after the phase I, each switch SW1 and SW4 remain on one period given time period of state of connection, second stage after the phase I, each switch SW2 and SW3 remain on one period given time period of state of connection. and the result alternately is output by capacitor C1 and C2 respectively corresponding to the output signal Vo21 of the input signal Vin in the phase I and Vo22 and corresponding to output signal Vo21 and the Vo22 of the input signal Vin of second stage.
Therefore, adopt sample circuit 100 of the prior art, the amplification of carrying out input signal Vin by erase amplifier A100 bias voltage only can realize at signal output stage (corresponding to the phase I of the present invention).But, adopt the sample circuit 1 in the present embodiment, the amplification of input signal Vin also can be except realizing corresponding to the second stage the phase I of described signal output stage.And with regard to the load on being applied to amplifier A1, when capacitor C1 became load, capacitor C2 remained on quick condition, and when capacitor C2 became load, capacitor C1 remained on quick condition.Therefore, when making the capacitance of capacitor C2 consistent with the capacitance of capacitor C1, electric current among the amplifier A1 needn't increase, and can make W (chip the width)/L (chip length) of the output driving transistors among the amplifier A1 than the W/L ratio that equals the output driving transistors in the sample circuit 100 of the prior art.As a result, can suppress the growth of the area in the sample circuit.
Below, describe comparison amplifier circuit with reference to corresponding accompanying drawing and use sample circuit 1 to construct one of circuit as passing through with tracking and maintenance (T/H).Fig. 3 represents according to an embodiment of the invention the relatively circuit diagram of the configuration of amplifying circuit, and Fig. 4 A, 4B and 4C be respectively according to an embodiment of the invention relatively amplifying circuit be in the sequential chart that circuit diagram, the comparison amplifying circuit of phase I are in the circuit diagram of second stage and are used to explain the built-in function of comparison amplifying circuit.
As shown in Figure 3, the comparison amplifying circuit 10 of present embodiment is the comparison amplifying circuit that is used for corresponding to the output of the signal of the voltage difference between input signal Vin and the reference signal Vr.This comparison amplifying circuit 10 comprises amplifier A10, as the capacitor C10 that is used for the capacitor of comparison, as the switch SW10 that is used for the switch of input signal, as the switch SW11 that is used for the switch of reference signal, as the switch SW12 of input replacement switch, as the capacitor C11 of first sampling capacitor with as the capacitor C1 2 of second sampling capacitor and as the switch SW13 and the SW14 of the first and second sampling switchs.In this case, capacitor C10 has a terminal of the input terminal that is connected to amplifier A10, and switch SW10 has a terminal of another terminal that is connected to capacitor C10 and input signal Vin is input to the input terminal of amplifier A10.Switch SW11 has terminal of another terminal of being connected to capacitor C10 and reference signal Vr is input to the input terminal of amplifier A10, and switch SW12 is arranged on the input terminal of amplifier A10 and have between the part of predetermined potential (being earth potential in this case).And, capacitor C11 and C12 have a terminal of each lead-out terminal that is connected to amplifier A10, and switch SW13 and SW14 are separately positioned on another terminal of capacitor C11 and C12 and each all has between the part of predetermined potential (being earth potential in this case).It is to be noted, switch SW12 as input replacement switch be a kind of be used to make obtain the invalid switch of amplifier A10 input signal, therefore and under the imported situation of difference, preferably connect between the difference input terminal of amplifier A10.
Shown in Fig. 4 A, 4B and 4C, relatively amplifying circuit 10 was alternately operated in two stages of phase I (referring to Fig. 4 A) and second stage (referring to Fig. 4 B).It is pointed out that corresponding at the signal of the input signal Vin of phase I and the voltage difference between the reference signal Vr and corresponding to alternately being output by capacitor C11 and C12 as a circulation with first and second stages at the signal of the input signal Vin of second stage and the voltage difference between the reference signal Vr.
At phase I (from t1 to t2 and t3 to time period of t4), shown in Fig. 4 A and 4C, relatively amplifying circuit 10 remains on off-state with each switch SW10, SW12 and SW13, and switch SW11 and SW14 is remained on the state of connection.Therefore, the voltage difference between reference signal Vr and the input signal Vin obtains by the voltage that the voltage from reference signal Vr deducts the input signal Vin that is sampled by capacitor C10.The voltage difference of Huo Deing is imported among the amplifier A10 subsequently and is exaggerated therein like this.The consequential signal that is produced is used as output signal Vo1 and exports from amplifier A10.In addition, the second stage before the phase I is carried out in operation, relatively amplifying circuit 10 all is maintained at the state of connection with each switch SW12 and SW13, and therefore the bias voltage Vx of amplifier A10 is sampled in capacitor C11.Therefore, switch SW13 disconnects (disconnection), and this output signal Vo21 that causes obtaining by the bias voltage Vx that deducts amplifier A10 from output signal Vo1 is by capacitor C11 output.On the other hand, because switch SW14 is maintained at the state of connection, capacitor C12 is recharged based on the output signal Vo1 that exports from amplifier A10, and the voltage of output signal Vo1 is sampled by capacitor C12.
Next second stage (for example from t2 to t3 and t4 to time period of t5), shown in Fig. 4 B and 4C, relatively amplifying circuit 10 remains on on-state with each switch SW10, SW12 and SW13, and switch SW11 and SW14 is remained on the state of disconnection.Therefore, do not have input signal Vin to be imported into the input terminal of amplifier A10, and therefore the input terminal of amplifier A10 is arranged on ground potential by switch SW12.In addition, because switch SW10 remains on the state of connection, input signal Vin voltage is sampled by capacitor C10.And because switch SW13 remains on the state of connection, capacitor C11 is recharged based on the bias voltage Vx of amplifier A10, and therefore the bias voltage Vx of amplifier A10 is sampled by capacitor C11.On the other hand, therefore capacitor C12 remains on unsteady (floating) state, deducts the output signal Vo1 that is sampled in the phase I by described capacitor C12 by the bias voltage Vx from amplifier A10 and obtains output signal Vo22 (Vx-Vo1) and be output by capacitor C12.
By this way, in the comparison amplifying circuit 10 of this embodiment, after the phase I, each switch SW11 and SW14 remain on one period given time period of state of connection, second stage after the phase I, each switch SW10, SW12 and SW13 remain on one period given time period of state of connection. the result, in the phase I, signal corresponding to the voltage difference between input signal Vin and the reference signal Vr is exported by capacitor C11, and in second stage, bias voltage Vx exports from amplifier A10.Therefore, output signal Vo21 and the Vo22 corresponding to voltage difference alternately is output by capacitor C11 and C12 respectively in first and second stages.
Therefore, adopt relatively amplifying circuit 110 of the prior art, the input signal Vin that the bias voltage by erase amplifier A110 carries out and the amplification of the voltage difference between the reference signal Vr only can realize at signal output stage (corresponding to the phase I of the present invention).But, adopt the comparison amplifying circuit 10 in the present embodiment, the amplification of the voltage difference between input signal Vin and the reference signal Vr also can be except realizing corresponding to the second stage the phase I of described signal output stage.And with regard to the load on being applied to amplifier A10, when capacitor C11 became load, capacitor C12 remained on quick condition, and when capacitor C12 became load, capacitor C11 remained on quick condition.Therefore, when making the capacitance of capacitor C12 consistent with the capacitance of capacitor C11, therefore electric current among the amplifier A10 needn't increase, and can make the W/L of the output driving transistors among the amplifier A10 than the W/L ratio of the output driving transistors among the amplifier A10 that equals in the relatively amplifying circuit 110 of the prior art.As a result, can rejection ratio than the growth of the area in the amplifying circuit.
Fig. 5 represents the circuit diagram of the parallel analog to digital conversion circuit of interpolation according to an embodiment of the invention, and the parallel analog to digital conversion circuit of this interpolation is configured to by comparing amplifying circuit 10.Although for the convenience of explaining, the present invention only is described at the parallel analog to digital conversion circuit 20 of the interpolation of 3-bit, but embodiments of the invention can also be applicable to and the parallel analog to digital conversion circuit of interpolation of the parallel analog to digital conversion circuit 20 similar 2-bits of the interpolation of 3-bit or the parallel analog to digital conversion circuit of interpolation of 4-bit or more bits.
The parallel analog to digital conversion circuit 20 of the interpolation of the 3-bit of present embodiment as shown in Figure 5 comprises reference signal generating portion 21, compares amplifier section 22, latchs part 23 and encoder 24.Although it is pointed out that in the accompanying drawings not show, the parallel analog to digital conversion circuit 20 of the interpolation of this 3-bit comprises sampling hold circuit etc.In this case, this sampling hold circuit is sampled, the sampled value of this analog input signal is kept one period given time period analog input signal, and exports this sampled value with the form of input signal Vin.
Reference signal generating portion 21 is made up of a plurality of resistance R that are used for dividing potential drop that are one another in series.Voltage difference between high voltage VRT and the low voltage VRB by five equilibrium, generates the different reference signal Vr0 to Vr6 of a plurality of voltages each other by described a plurality of resistance R that are used for dividing potential drop thus.
Relatively amplifier section 22 is made up of a plurality of relatively amplifying circuit 22a to 22d, each relatively amplifying circuit all have the configuration (structure) identical with above-mentioned relatively amplifying circuit 10.Relatively amplifying circuit 22a comprises three capacitors, i.e. capacitor C21a, capacitor C22a and capacitor C23a.Relatively amplifying circuit 22b comprises three capacitors, i.e. capacitor C21b, capacitor C22b and capacitor C23b.Relatively amplifying circuit 22c comprises three capacitors, i.e. capacitor C21c, capacitor C22c and capacitor C23c.Relatively amplifying circuit 22dc comprises three capacitors, i.e. capacitor C21d, capacitor C22d and capacitor C23d.Corresponding to the signal of the voltage difference of input signal Vin and reference signal Vr0 by the output of the capacitor C21a among the capacitor C21a to C21d.Equally, corresponding to the signal of the voltage difference of input signal Vin and reference signal Vr2 by capacitor C21b output.Corresponding to the signal of the voltage difference of input signal Vin and reference signal Vr4 by capacitor C21c output.And, corresponding to the signal of the voltage difference of input signal Vin and reference signal Vr6 by capacitor C21d output.
In addition, be transfused to adjacent relatively amplifying circuit (relatively the amplifying circuit 22a and the 22b of approximating reference voltage aspect the level difference respectively at it, 22b and 22c, and 22c and 22d) in capacitor C23a to C23c and capacitor C22b and C22d be connected to interpolating circuit 40a to 40c respectively.And, by in interpolating circuit 40a, 40b and 40c, being output between output signal Vo21a and the Vo21b, carrying out the output signal Vo22a to Vo22c that interpolation obtains between output signal Vo21b and the Vo21c and between output signal Vo21c and Vo21d.It is pointed out that output signal Vo21a to Vo21d was output in the phase I, and output signal Vo22a to Vo22c is output in second stage.
Latching part 23 is made up of latch cicuit 23a to 23g.Latch cicuit 23a to 23g compares output signal Vo21a, Vo22a, Vo21b, Vo22b, Vo21c, Vo22c and Vo21d and predetermined threshold value so that these output signals are latched in wherein.It is pointed out that latched comparator etc. also can act on latch cicuit 23a to 23g.
Encoder 24 is carried out coding based on the latch mode among the latch cicuit 23a to 23g, so that the digital signal of output 3-bit.It is pointed out that in some cases the polarity of output signal Vo21a to Vo21d and output signal Vo22a to Vo22c depends on the circuit arrangement of interpolating circuit 40a to 40c and is inverted (inverted).Like this, encoder 24 is at the latch mode of latch cicuit 23a, 23c, 23e and 23g and discern the counter-rotating (inversion) of the latch mode of latch cicuit 23b, 23d and 23f.It is pointed out that amplifier can be arranged in the previous stage of latch cicuit 23a to 23g to substitute the counter-rotating in the recognition coding device 24.In this case, reversal amplifier is used as the amplifier in the previous stage that is arranged in latch cicuit 23b, 23d and 23f.In addition, when the parallel analog to digital conversion circuit 20 of interpolation is not single imported, but difference is when imported, and this polarity inversion is by making the polarity inversion of input signal of the difference amplifier in the previous stage that arrives latch cicuit 23b, 23d and 23f carry out.When making each polarity and each the polarity of output signal Vo22a to Vo22c when consistent each other of output signal Vo21a to Vo21d by this way, any analog or digital polarity inversion all is available, as long as these polarity can be finally consistent each other.
Now will in the parallel analog to digital conversion circuit 20 of interpolation of configuration in the above described manner each relatively each concrete configuration and the operation of amplifying circuit 22a to 22d be described.It is pointed out that because relatively amplifying circuit 22a to 22d is consistent each other in structure and operation, therefore configuration and the operation that will compare amplifying circuit 22a in this description of giving an example below.
This comparison amplifying circuit 22a comprises amplifier A20a, capacitor C20a as the capacitor that is used for comparison, switch SW20a as the switch that is used for input signal, switch SW21a as the switch that is used for reference signal, switch SW22a as input replacement switch, capacitor C21a as first sampling capacitor, two capacitor C22a and C23a as second sampling capacitor, switch SW23a as the first sampling switch, and as two the switch SW24a and the SW25a of the second sampling switch.In this case, capacitor C20a has a terminal of the input terminal that is connected to amplifier A20a, switch SW20a is input to the input terminal of amplifier A20a with input signal Vin, and switch SW21a has a terminal of another terminal that is connected to capacitor C20a and reference signal Vr is input to the input terminal of amplifier A20a.Switch SW22a is arranged on the input terminal of amplifier A20a and has between the part of predetermined potential (being earth potential in this case), and capacitor C21a has a terminal of the lead-out terminal that is connected to amplifier A20a.Capacitor C22a and C23a have a terminal of each lead-out terminal that is connected to amplifier A20a, and the capacitance of each is half of capacitance of capacitor C21a, and switch SW23a is arranged on another terminal of capacitor 21a and has between the part of predetermined potential.And two switch SW24a and SW25a are separately positioned on another terminal of capacitor C22a and have between the part of predetermined potential and at another terminal of capacitor C23a with have between the part of predetermined potential.It is to be noted, switch SW22a as input replacement switch be a kind of be used to make obtain the invalid switch of amplifier A20a input signal, and under the imported situation of difference, preferably connect between the difference input terminal of amplifier A20a.
And relatively amplifying circuit 22a is according to two stages outputs of phase I and second stage signal output signal Vo21a corresponding to the voltage difference between input signal Vin and the reference signal Vr0.Fig. 6 is used to explain the sequential chart of the built-in function of the parallel analog to digital conversion circuit 20 of interpolation according to an embodiment of the invention.
At phase I (from t1 to t2 and t3 to time period of t4), as shown in Figure 6, relatively amplifying circuit 22a remains on off-state with each switch SW20a, SW22a and SW23a, and switch SW21a, SW24a and SW25a is remained on the state of connection.Therefore, the voltage of the input signal Vin that is sampled by capacitor C10 is deducted from the voltage of reference signal Vr0.Voltage difference as a result between reference signal Vr0 and the input signal Vin is imported among the amplifier A20a and is exaggerated therein.The signal that is exaggerated like this is used as output signal Vo1a and exports from amplifier A20a.In addition, the second stage before the phase I is carried out in operation, relatively amplifying circuit 22a is maintained at the state of connection with each switch SW22a and SW23a, and therefore the bias voltage Vx of amplifier A20a is sampled in capacitor C21a.Therefore, switch SW23a keeps off-state in the phase I, and this voltage difference that causes obtaining by the bias voltage Vx that deducts amplifier A20a from output signal Vo1a is exported by capacitor C21a as output signal Vo21a.On the other hand, because switch SW24a and SW25a are maintained at the state of connection, each of capacitor C22a and C23a all is recharged based on the output signal Vo1a that exports from amplifier A20a.Therefore the voltage of output signal Vo1a is by each sampling of capacitor C22a and C23a.
Next second stage (for example from t2 to t3 and t4 to time period of t5), as shown in Figure 6, relatively amplifying circuit 22a remains on on-state with each switch SW20a, SW22a and SW23a, and switch SW21a, SW24a and SW25a is remained on the state of disconnection.Therefore, therefore the input terminal of amplifier A20a is arranged on ground potential by switch SW22a.In addition, because switch SW20a remains on the state of connection, input signal Vin voltage is sampled by capacitor C20a.And because switch SW23a remains on the state of connection, capacitor C21a is recharged based on the bias voltage Vx of amplifier A20a, and therefore the bias voltage Vx of amplifier A20a is sampled by capacitor C21a.On the other hand, each of capacitor C22a and C23a remains on unsteady (floating) state, therefore deduct the voltage difference (Vx-Vo1a) that the output signal Vo1a that sampled by described capacitor C22a obtains by bias voltage Vx, and deduct the voltage difference (Vx-Vo1a) that the output signal Vo1a that sampled by described capacitor C23a obtains by bias voltage Vx and be output by capacitor C22a and C23a respectively as output signal Vo23a and output signal Vo25a from amplifier A20a from amplifier A20a.And the output signal Vo22 (={ Vo25a+Vo23b}/2) with the intermediate level between output signal Vo25a and the output signal Vo23b generates and will be output by interpolation 40a.
Below, input signal is imported continuously as input signal Vin and is handled as a circulation with first and second stages with top situation is similar.
As described above, in comparing amplifying circuit 22a, after the phase I, each switch SW21a, SW24a and SW25a remain on one period given time period of state of connection, second stage after the phase I, each switch SW20a, SW22a and SW23a remain on one period given time period of state of connection.As a result, in the phase I, export from amplifier A20a corresponding to the output signal Vo21a of the voltage difference between reference signal Vi0 and the input signal Vin.And, in second stage, corresponding to each the signal Vo21a of the voltage difference between reference signal Vr0 and the input signal Vin respectively by C22a and C23a output.
Therefore, adopt the parallel analog to digital conversion circuit of interpolation of the prior art, the input signal Vin that the bias voltage by erase amplifier carries out and the amplification of the voltage difference between the reference signal Vr only can realize at the signal output stage.But, adopt the parallel analog to digital conversion circuit of interpolation in the present embodiment, the amplification of the voltage difference between reference signal Vr0 and the input signal Vin also can be except realizing corresponding to the second stage the phase I of described signal output stage.
And with regard to the load on the amplifier A20a to A20d in being applied to comparison amplifying circuit 20a to 20d respectively, when each of capacitor C21a to C21d became load, each of capacitor C22a to C22d and C23a to C23d remained on quick condition.On the other hand, when each of capacitor C22a to C22d and C23a to C23d became load, each of capacitor C21a to C21d remained on quick condition.
And, make that each the capacitance of capacitor C22a to C22d and C23a to C23d is each half of capacitance of capacitor C21a to C21d.As a result, the electric current among the amplifier A20a to A20d needn't increase, and therefore the output driving transistors of amplifier A20a to A20d in each W/L than also needn't become with W/L of the prior art than different.As a result, in the parallel analog to digital conversion circuit of interpolation, the quantity of amplifier can access minimizing and can realize less area.
The stage corresponding to the signal output stage of it is pointed out that also can be set to second stage and replace being set to the phase I.That is to say, the state that all remains on connection in the phase I at each switch SW20a, SW22a, SW24a and SW25a is after one period given time period, and each switch SW21a and SW23a remain on one period given time period of state of connection in second stage.As a result, in the phase I, export from amplifier A20a corresponding to the signal of the voltage difference between reference signal Vr0 and the input signal Vin.And, in second stage, export by capacitor C21a corresponding to the signal of the voltage difference between reference signal Vr0 and the input signal Vin.
At this, will describe at reference Fig. 7 and utilize the electric capacity interpositioning to be described as the parallel analog to digital conversion circuit of the interpolation of interpositioning.Fig. 7 be expression electric capacity interpolation parallel analog to digital conversion circuit 20 ' circuit diagram.
As shown in Figure 7, the parallel analog to digital conversion circuit 20 of the interpolation of utilizing the electric capacity interpositioning ' in, be transfused to adjacent relatively amplifying circuit (relatively the amplifying circuit 22a and the 22b of approximating reference voltage aspect the level difference respectively at it, 22b and 22c, and 22c and 22d) in capacitor C23a to C23c and capacitor C22b to C22d be connected with each other respectively, be configured to the electric capacity interpolating circuit thus.And, by being output between output signal Vo21a and the Vo21b, carrying out the output signal Vo22a to Vo22c that interpolation obtains between output signal Vo21b and the Vo21c and between output signal Vo21c and Vo21d.It is to be noted, because capacitor C23a to C23c is connected respectively to capacitor C22b to C22d, the voltage of output signal Vo22a to Vo22c is respectively combination (composite) voltage that the output voltage signal combination with one another (compose) by the output voltage signal of capacitor C23a to C23c and capacitor C22b to C22d obtains.As mentioned above, adopt this electric capacity interpolation,, therefore can realize less area because capacitor C23a to C23c and capacitor C22b to C22d only need be connected with each other.
Below, just describe and utilize the electric current interpositioning to be described as the parallel analog to digital conversion circuit of the interpolation of interpositioning at reference Fig. 8.Fig. 8 is an expression electric current interpolation parallel analog to digital conversion circuit 20 " circuit diagram.
As shown in Figure 8, at the parallel analog to digital conversion circuit 20 of the interpolation of utilizing the electric current interpositioning " in; its be transfused to respectively approximating reference voltage aspect the level difference adjacent relatively amplifying circuit (relatively amplifying circuit 22a and 22b; 22b and 22c; and 22c and 22d) in capacitor C23a to C23c and capacitor C22b to C22d be connected respectively to amplifier A53a to A53c, be configured to the electric current interpolating circuit thus.And, by being output between output signal Vo21a and the Vo21b, carrying out the output signal Vo22a to Vo22c that interpolation obtains between output signal Vo21b and the Vo21c and between output signal Vo21c and Vo21d.Shown in Figure 9 the is parallel analog to digital conversion circuit of interpolation is not single imported but a example under the situation that difference is imported.Amplifier A20a ', A20b ' shown in Fig. 9, A52a ', A52b ', A53a ' correspond respectively to amplifier A20a, A20b, A52a, A52b and the A53a shown in Fig. 8.
At the amplifier A52a that is used for carrying out the electric current interpolation, as shown in figure 10, two MOS transistor difference are connected to common load resistance R3a and R4a to Tr5a and Tr6a and Tr7a and Tr8a.In addition, current source I3a and I4a are connected respectively to the MOS transistor difference to each to the source electrode of Tr7a and Tr8a of each and MOS transistor difference of the source electrode of Tr5a and Tr6a.And capacitor C23a is connected to and constitutes the grid of MOS transistor difference to the MOS transistor Tr7a of Tr7a and Tr8a, and output signal Vo25a is input to the grid of MOS transistor Tr7a.And capacitor C22a is connected to and constitutes the grid of MOS transistor difference to the MOS transistor Tr5a of Tr5a and Tr6a, and output signal Vo23b is input to the grid of MOS transistor Tr5a.It is pointed out that amplifier A51a, A52a to A52d and A53b to A53d have the configuration identical with amplifier A53a.Note shown in Figure 11 the is parallel analog to digital conversion circuit of interpolation is not single imported but a example under the situation that difference is imported.Therefore, in the electric current interpolation,, therefore can prevent that adjacent amplifier A20a to A20d from exerting an influence each other owing to connect by transistor.
At this, although the parallel analog to digital conversion circuit of interpolation that applies electric capacity interpolation or electric current interpolation on it is described as an example in front, embodiments of the invention can also be suitable for the parallel analog to digital conversion circuit of interpolation that has applied resistance interpolation etc. thereon.It is to be noted, although below will by provide time on it by the parallel analog to digital conversion circuit of interpolation of resistance interpolation the another kind configuration of the parallel analog to digital conversion circuit of interpolation is described as an example, this embodiment also can be applicable to the parallel analog to digital conversion circuit of interpolation by utilizing electric current interpositioning or resistance interpositioning to construct.
In the parallel analog to digital conversion circuit of above-mentioned interpolation, seven latch cicuit 23a to 23g are provided.But, output signal Vo21a to Vo21d was output in the phase I, and output signal Vo22a to Vo22d is output in second stage.Therefore, for example the same in the parallel analog to digital conversion circuit 60 of electric capacity interpolation as shown in Figure 12, output signal Vo21a to Vo21d can be latched by four latch cicuit 23a, 23c, 23e and 23g respectively in the phase I, and output signal Vo22a to Vo22d can be latched circuit 23a, 23c respectively and 23e latchs in second stage.That is to say that in this case, output signal Vo21a to Vo21d and output signal Vo22a to Vo22c are latched according to the mode of time-division.
As shown in figure 12, in the parallel analog to digital conversion circuit 60 of electric capacity interpolation, capacitor C21a to C21d is respectively by selecting switch SW26a, SW26c, SW26e and the SW26g of switch to be connected to latch cicuit 23a, 23c, 23e and 23g as output.And capacitor C23a to C23d (capacitor C22b to C2dd) is connected to latch cicuit 23a, 23c, 23e and 23g by switch SW26b, SW26d, SW26f and SW26h respectively.As a result, as shown in figure 13, each among each of switch SW26a, SW26c, SW26e and SW26g and switch SW26b, SW26d, SW26f and the SW26h is alternately remained on on-state.It may be noted that Figure 13 is the sequential chart of the sequential in the operation of the part that is associated with switch SW26a and switch SW26b of expression, and these sequential in the operation of the part of being correlated with therewith also are applicable to other switch SW26c to SW26h.
And, in the phase I, among switch SW26a, SW26c, SW26e and the SW26g each remains on the state of connection, and this causes the output signal Vo21a to Vo21d that is output by capacitor C21a to C21d to be imported into latch cicuit 23a, 23c, 23e and 23g respectively so that be latched at there (referring to Figure 13).Encoder 24 ' this moment is with reference to the latch mode among latch cicuit 23a, 23c, 23e and the 23g.
In addition, in second stage, among switch SW26b, SW26d, SW26f and the SW26h each remains on the state of connection, and this causes being imported into latch cicuit 23a, 23c, 23e and 23g respectively so that be latched at there (referring to Figure 13) by the output signal Vo22a to Vo22d of capacitor C23a to C23d output.Encoder 24 ' this moment is with reference to the latch mode among latch cicuit 23a, 23c, 23e and the 23g.
And encoder 24 ' based on the latch mode among latch cicuit 23a, 23c, 23e and the 23g is in the digital signal of phase I and second stage output corresponding to input signal Vin.For example, when in the phase I, latch mode among latch cicuit 23a, 23c, 23e and the 23g is " 0 (L level) ", " 1 (H level) ", " 1 (H level) " and " 1 (H level) ", and in second stage, latch mode among latch cicuit 23a, 23c, 23e and the 23g is " 0 (L level) ", " 1 (H level) ", " 1 (H level) " and " 1 (H level) ", and encoder 24 ' output has the digital signal of value " 101 ".
Now, when being not enough among the amplifier A20a to A20d in the parallel analog to digital conversion circuit 60 of electric capacity interpolation obtain sufficient amplification factor, between switch SW26a and SW26b, SW26c and SW26d, SW26e and SW26f and SW26g and SW26h and latch cicuit 23a, 23c, 23e and 23g, amplifier section 25a to 25d is set respectively.Figure 14 has represented a kind of configuration, and wherein, amplifier section 25a is arranged between switch SW26a and SW26b and latch cicuit 23a, and amplifier section 25b is arranged between switch SW26c and SW26d and latch cicuit 23c.Therefore it may be noted that amplifier section 25c has the configuration identical with 25b with amplifier section 25a with 25d, omit its relevant elaboration at this for easy.
In amplifier section 25a to 25d, in the phase I, output signal Vo21a and Vo21d are exaggerated and export, and in second stage, output signal Vo22a and Vo22d are exaggerated and export.Therefore, amplifieroperation and and the operation (being used for the operation of the bias voltage of erase amplifier A21a to A21d) of resetting need implement repeatedly in phase I and second stage.Therefore, each among the amplifier section 25a to 25d all need be operated with the operational cycle of the operational cycle that doubles amplifier A20a to A20d.
But, the parallel analog to digital conversion circuit high speed operation of electric capacity interpolation, the enforcement of can not being charged is operated in this replacement that causes being used for amplifier A20a to A20d.
For example, operation with amplifier 25b is described as an example, shown in Figure 15 A to 15H, at sequential t11 to t14, the output signal Vo21b that imports in the phase I (referring to Figure 15 A) can be exaggerated under the state that the output signal Vo24b from amplifier A21b is reset by replacement amplifier A21b (by making switch SW27b and SW28b be converted to connection).But, in the sequential from t14 to t16d, output signal Vo21b is exaggerated under situation about can not fully reset by replacement amplifier A21b from the output signal Vo24b of amplifier A21b.Therefore, owing to can not in latch cicuit 23c, obtain correct information, therefore there is possibility from encoder 24 ' output error (false) digital signal.This situation also is applicable to latch cicuit 23a, 23e and 23g.
In order to solve this situation, in the parallel analog to digital conversion circuit 60 of the electric capacity interpolation of present embodiment, according to obtain in the phase I by latch cicuit 23a, 23c, 23e and 23g with the level (level) of detected input signal Vin determine among the amplifier section 25a to 25d with an operated amplifier section, the operation that then is under an embargo of other amplifier section.As a result, just can prevent encoder 24 ' obtain wrong information from latch cicuit 23a, 23c, 23e and 23g.That is to say, according in the result of phase I and needs have less amplitude at second stage input signal detected, that arrive this amplifier section.On the other hand, the input signal that arrives other amplifier sections has bigger amplitude.Therefore other amplifier sections are forbidden being operated, and this causes such state to be avoided, and promptly in this state, each in other amplifier sections of being paid close attention to all is enough to obtain Reset Status.
For example, when in the phase I, latch cicuit 23a, 23c, 23e and 23g remain on " 0 (L level) ", " 1 (H level) ", " 1 (H level) " and " 1 (H level) " respectively, shown in Figure 16 A, will from the digital signal of encoder 24 ' output " 101 " or " 110 ".Therefore, in second stage, the output signal that must detect from amplifier 25a is to remain on " 0 (L level) " still to remain on " 1 (H level) ".And, when the output signal from amplifier section 25a remains on " 0 (L level) " in second stage, then become the digital signal of " 101 " from encoder 24 ' output.On the other hand, when the output signal from amplifier section 25a remains on " 1 (H level) " in second stage, then become the digital signal of " 110 " from encoder 24 ' output.
Subsequently, in second stage, shown in Figure 16 B, amplifier section 25b to 25d except amplifier section 25a and latch cicuit 23a and the operation of latch cicuit 23c, 23e and 23g all stop.As a result, each among the amplifier section 25b to 25d can both be set at Reset Status in the time period of second stage.Therefore, latch cicuit road 23c, 23e and 23g among instant Fig. 7 are removed, and the parallel analog to digital conversion circuit 60 of electric capacity interpolation also still can high speed operation.For example, shown in Figure 17 A to 17H, be set to reset the time period (referring to as 17H) among amplifier section 25b from time period of t14 to t15, this causes this replacement time period can be three times (treble) of output time section.As a result, this Reset Status can obtain fully.
At this, by for example switch SW27b to SW27d being converted to the operation that connection can stop amplifier section 25b to 25d., in addition, by for example among reset signal input latch circuit 23c, 23e and the 23g each being stoped the operation of latch cicuit 23c, 23e and 23g.And encoder 24 ' only detection remains on the latch mode of the latch cicuit 23a of mode of operation.In the above described manner, latch cicuit 23c, 23e and 23g are reset so that stop wherein operation in second stage, make it can reduce power consumption thus.
As mentioned above, in in the parallel analog to digital conversion circuit of electric capacity interpolation of these embodiment each, corresponding to the signal of input signal Vin in the phase I and the voltage difference between the reference signal Vr and corresponding to the signal of input signal Vin in second stage and the voltage difference between the reference signal Vr from relatively being output the amplifying circuit 22a to 22d.Therefore can provide a kind of parallel analog to digital conversion circuit,, make it can realize lower power consumption and thus than small size wherein by using the quantity that reduces amplifier corresponding to signal corresponding to voltage difference in phase I output.It is pointed out that except the electric capacity interpolation, also can carry out resistance interpolation, electric current interpolation etc. by using respectively at the signal corresponding to voltage difference of phase I and second stage output.
It is pointed out that in the above-mentioned switch each all has formations such as a kind of MOS transistor.These switchs are controlled according to the control signal that control section (for illustrating) sends in addition.For example, in the parallel analog to digital conversion circuit 60 of electric capacity interpolation as shown in figure 12, switch SW20a to SW20d, SW22a to SW22d, SW23a to SW23d, SW26b, SW26d, SW26f and SW26h are controlled according to first control signal.And switch SW21a to SW21d, SW24a to SW24d, SW25a to SW25d, SW26a, SW26c, SW26e and SW26g are controlled according to second control signal as the reverse signal of first control signal.
Although and describe embodiments of the invention with reference to the accompanying drawings, this only is illustrative, and this embodiment can realize the form that it carries out other illustrative embodiment of various changes and modifications with the knowledge based on those of ordinary skill in the art.
The parallel analog to digital conversion circuit 130 of interpolation shown in for example similar Figure 22 as shown in figure 18, can be inserted in the parallel analog to digital conversion circuit 61 of electric capacity interpolation in the following electric capacity from the output signal of amplifier A20a to A20e.That is, voltage is exaggerated in amplifier A20a to A20c in previous stage in the middle of voltage difference Vs1 and Vs2 and its, and therefore these voltage differences and intermediate voltage therebetween afterwards be exaggerated respectively in amplifier A20a to A20e in the one-level.By this way, the electric capacity interpolation is implemented.
Will be understood by those skilled in the art that,, can produce various variations, combination, sub-portfolio and alternative form, as long as they are within the scope of appended claims or its equivalents according to design needs and other factors.
The cross reference of related application
The theme that the present invention comprises relates to the Japanese patent application JP2008-023398 of application on February 2nd, 2008, and the whole of this application will comprise in this application by the reference mode.
Claims (8)
1. parallel analog to digital conversion circuit comprises:
The reference signal generating portion is used for a plurality of reference signals that formation voltage differs from one another;
Relatively amplifier section is used to amplify by described a plurality of reference signals of described reference signal generating unit branch generation and the voltage difference between the input signal, and exports the voltage difference that is exaggerated like this;
Described relatively amplifier section comprises:
A plurality of amplifiers,
Be connected respectively to described a plurality of amplifier input terminal and be adapted such that each the invalid input replacement switch of input signal of described a plurality of amplifiers,
First sampling capacitor that comprises a terminal on the lead-out terminal that is connected respectively to described a plurality of amplifiers,
Second sampling capacitor that comprises a terminal on the lead-out terminal that is connected respectively to described a plurality of amplifiers,
Be arranged on the another terminal of described first sampling capacitor and comprise the first sampling switch between the part of predetermined potential; And
Be arranged on the another terminal of described second sampling capacitor and comprise the second sampling switch between the part of predetermined potential,
Wherein be used for each of described input replacement switch and the described first sampling switch being remained on the control operation of on-state section one period preset time and being used for the control operation that each described second sampling switch remains on on-state section one period preset time is alternately carried out, make that the signal corresponding to the voltage difference between described input signal and described reference signal alternately is output by described first sampling capacitor and by described second sampling capacitor.
2. according to the parallel analog to digital conversion circuit of claim 1, wherein,
Described relatively amplifier section is provided with interpolating circuit, is used for the corresponding output signal from per two different amplifiers exported of interpolation by described second sampling capacitance.
3. according to the parallel analog to digital conversion circuit of claim 1, wherein, described relatively amplifier section comprises:
The capacitor that is used for comparison comprises a terminal that is connected respectively to described amplifier input terminal;
The switch that is used for input signal comprises being used for a terminal of another terminal that is connected respectively to the described capacitor that is used for comparison input signal is input to described amplifier;
The switch that is used for reference signal comprises being used for a terminal of another terminal that is connected respectively to the described capacitor that is used for comparison reference signal is input to described amplifier;
When described input replacement switch is switched to connection, one of described switch that is used for input signal and the described switch that is used for reference signal is switched to connection, and be switched to when disconnecting when described input replacement switch, another of described switch that is used for input signal and the described switch that is used for reference signal is switched to connection.
4. according to the parallel analog to digital conversion circuit of claim 1, also comprise:
Switch is selected in a plurality of outputs, comprises respectively being connected to a described relatively terminal of the lead-out terminal of amplifier section;
A plurality of latch cicuits, each all selects corresponding one of switch to be connected to described relatively per two different lead-out terminals of amplifier section by described a plurality of outputs; And
Encoder is used for encoding corresponding to the digital signal of input signal according to the latch mode of described a plurality of latch cicuits;
Wherein, per two outputs that comprise corresponding one terminal that is connected to described a plurality of latch cicuits select the switchs and the operations of described sampling switch synchronously to be switched on, and are latched at respectively in the mode of time-division from per two output signals of described comparison amplifier section among corresponding of described a plurality of latch cicuits.
5. according to the parallel analog to digital conversion circuit of claim 4, wherein,
Amplifier section is separately positioned on described output and selects between switch and the described latch cicuit; And
When the described first sampling switch and described second sampling one of switch were switched on, when another sampling switch was switched on according to the latch mode of described a plurality of latch cicuits, the operation of the part of described a plurality of amplifier sections was prevented from.
6. according to the parallel analog to digital conversion circuit of claim 5, wherein,
When the operation of the described part of described a plurality of amplifier sections was prevented from, the operation of the part of described a plurality of latchs also was prevented from.
7. sample circuit comprises:
The amplifier that is used for amplification input signal;
Input replacement switch comprises a terminal that is connected to described amplifier input terminal and is adapted such that the input signal that arrives described amplifier is invalid;
A plurality of capacitors comprise a terminal of the lead-out terminal that each all is connected to described amplifier; And
A plurality of sampling switchs are separately positioned on another terminals of described a plurality of capacitors and each all comprises between the part of predetermined potential;
Wherein, each of one or more sampling switchs in described input replacement switch and described a plurality of sampling switch all remains on the state of connection after one period given time period, in described a plurality of sampling switch remaining be one or more to be switched to one period given time period of on-state, makes that alternately the another terminal of the one or more capacitors by described a plurality of capacitors and the another terminal of all the other capacitors are output corresponding to the signal of input signal for each.
8. comparison amplifying circuit that is used to export corresponding to the signal of the voltage difference between input signal and reference signal comprises:
Amplifier;
The capacitor that is used for comparison comprises a terminal that is connected to described amplifier input terminal;
The switch that is used for input signal comprises being used for a terminal of another terminal that is connected to the described capacitor that is used for comparison input signal is input to described amplifier
The switch that is used for reference signal comprises being used for a terminal of another terminal that is connected to the described capacitor that is used for comparison reference signal is input to described amplifier;
Input replacement switch comprises a terminal that is connected to described amplifier input terminal, is used to make the input signal that obtains described amplifier invalid;
A plurality of sampling capacitors comprise a terminal of the lead-out terminal that each all is connected to described amplifier; And
A plurality of sampling switchs are separately positioned on another terminals of described a plurality of sampling capacitors and each all comprises between the part of predetermined potential;
Wherein, each of described switch that is used for input signal and described input replacement switch and the described switch that is used for reference signal are alternately connected, and each and one or more all the other switchs of one or more switchs of described a plurality of sampling switchs, with the operation of each and the described switch that is used for reference signal of described switch that is used for input signal and described input replacement switch synchronously, alternately connected, and corresponding to the signal of the voltage difference between described input signal and described reference signal the alternately one or more switchs by described a plurality of sampling switchs and one or how all the other switchs are output.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007238459 | 2007-09-13 | ||
| JP238459/07 | 2007-09-13 | ||
| JP2008023398A JP5109692B2 (en) | 2007-09-13 | 2008-02-02 | Parallel analog / digital conversion circuit, sampling circuit, and comparison amplifier circuit |
| JP023398/08 | 2008-02-02 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101388669A true CN101388669A (en) | 2009-03-18 |
| CN101388669B CN101388669B (en) | 2012-05-23 |
Family
ID=40477882
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008101608038A Expired - Fee Related CN101388669B (en) | 2007-09-13 | 2008-09-16 | Parallel type analog-to-digital conversion circuit, sampling circuit and comparison amplification circuit |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP5109692B2 (en) |
| CN (1) | CN101388669B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105404410A (en) * | 2014-09-04 | 2016-03-16 | 三星电子株式会社 | Semiconductor device and semiconductor system |
| CN110299919A (en) * | 2019-08-26 | 2019-10-01 | 成都铭科思微电子技术有限责任公司 | A kind of low-power consumption ultrahigh speed high-precision adc |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5928130B2 (en) * | 2012-04-25 | 2016-06-01 | 富士通株式会社 | Interpolation circuit and reception circuit |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3113031B2 (en) * | 1992-01-31 | 2000-11-27 | 株式会社東芝 | Parallel A / D converter |
| US5332997A (en) * | 1992-11-04 | 1994-07-26 | Rca Thomson Licensing Corporation | Switched capacitor D/A converter |
| JP2004173015A (en) * | 2002-11-20 | 2004-06-17 | Sony Corp | A/d converter |
-
2008
- 2008-02-02 JP JP2008023398A patent/JP5109692B2/en not_active Expired - Fee Related
- 2008-09-16 CN CN2008101608038A patent/CN101388669B/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105404410A (en) * | 2014-09-04 | 2016-03-16 | 三星电子株式会社 | Semiconductor device and semiconductor system |
| CN105404410B (en) * | 2014-09-04 | 2020-06-26 | 三星电子株式会社 | Semiconductor device and semiconductor system |
| CN110299919A (en) * | 2019-08-26 | 2019-10-01 | 成都铭科思微电子技术有限责任公司 | A kind of low-power consumption ultrahigh speed high-precision adc |
| CN110299919B (en) * | 2019-08-26 | 2019-12-13 | 成都铭科思微电子技术有限责任公司 | low-power-consumption ultrahigh-speed high-precision analog-to-digital converter |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101388669B (en) | 2012-05-23 |
| JP5109692B2 (en) | 2012-12-26 |
| JP2009089347A (en) | 2009-04-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6181314B1 (en) | Liquid crystal display device | |
| US8624635B2 (en) | Sensor circuit for concurrent integration of multiple differential signals and operating method thereof | |
| EP2270987B1 (en) | Capacitive integrate and fold charge-to-digital converter | |
| US20120081244A1 (en) | Method and apparatus for analog to digital conversion | |
| CN101133556A (en) | Switched-capacitor circuit with scaled reference voltage | |
| WO2012063520A1 (en) | Linear system coefficient estimating method, linear device column value estimating method, capacitance detecting method, integrated circuit, touch sensor system, and electronic device | |
| JP2009005139A (en) | Sequential a/d converter | |
| WO2012012662A1 (en) | Background calibration method for fixed gain amplifiers | |
| US5014055A (en) | Analog-to-digital converter and method of use utilizing charge redistribution | |
| CN101388669B (en) | Parallel type analog-to-digital conversion circuit, sampling circuit and comparison amplification circuit | |
| WO2011104786A1 (en) | Pipeline analog to digital converter and analog to digital conversion method and dynamic differential amplifier | |
| US7696916B2 (en) | Parallel type analog-to-digital conversion circuit, sampling circuit and comparison amplification circuit | |
| KR20090116709A (en) | Charge-domain pipelined analog-to-digital converter | |
| US7446573B1 (en) | Comparator systems and methods | |
| JP4330791B2 (en) | Semiconductor integrated circuit device and method for controlling semiconductor integrated circuit device | |
| US9923571B2 (en) | Ramp analog-digital converter able to provide an average of two signals directly | |
| JPH10327072A (en) | A/d converter and voltage comparator | |
| US8077070B2 (en) | Charge-domain pipelined charge-redistribution analog-to-digital converter | |
| JP4684028B2 (en) | Pipeline A / D converter | |
| US6822599B2 (en) | Integrated circuit and A/D conversion circuit | |
| JP3166603B2 (en) | D / A converter | |
| SE441713B (en) | LADDNINGSOVERFORINGSANORDNING | |
| JP4391502B2 (en) | Differential amplifier, two-stage amplifier and analog / digital converter | |
| JP2017228932A (en) | Switched capacitor circuit and AD conversion device | |
| KR100902594B1 (en) | A data driver of display device and a method for driving the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120523 Termination date: 20150916 |
|
| EXPY | Termination of patent right or utility model |