JP2004173015A - A/d converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an A/D converter capable of improving the conversion resolution and improving the conversion accuracy and stability of conversion characteristics without increasing its layout area. <P>SOLUTION: In a comparison part 30A, two third capacitors are serially connected between the output terminals of the first chopper amplifiers corresponding to the reference voltages adjacent to each other, the input terminal of a third chopper amplifier is connected to the center connection point of the third capacitors, and an intermediate voltage generation circuit 30b is constituted. The intermediate voltage of the output voltage of the two first chopper amplifiers adjacent to each other is outputted from the center connection point of the two third capacitors, the intermediate voltage is amplified further by the third chopper amplifier and the result is inputted to an encoder 40 together with the output signals of the second chopper amplifier. Thus, the conversion resolution of conversion data D<SB>out</SB>obtained by the encoder 40 is improved, the level of the intermediate voltage is stabilized and the stability of the conversion data is improved. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an A / D converter, and more particularly to an A / D converter capable of realizing analog-digital conversion with high resolution using a chopper type comparator.
[0002]
[Prior art]
In the flash A / D converter, a plurality of divided voltage elements are generated by dividing a reference voltage by a plurality of series-divided resistance elements, and each divided voltage is compared with an input voltage using each divided voltage as a reference voltage. Digital conversion data corresponding to the input voltage is output based on the result.
[0003]
In the flash A / D converter having such a configuration, high-speed conversion can be realized because the comparison circuits operate in parallel. On the other hand, the number of resistive elements for voltage division and the number of comparators are determined according to the number of bits of the conversion data to be output.
[0004]
For example, in the conventional flash A / D converter shown in FIG. 7, a plurality of voltage-dividing resistors are connected in series between two terminals to which reference voltages VRT and VRB are supplied, thereby forming a reference voltage generating unit 10. Signal S_INAnd the reference voltage generated by the reference voltage generator 10 alternately with the first sampling capacitor C₁₁~ C_N1, A plurality of second sampling carriers C₁₂~ C_N2A comparison unit 30 composed of first and second chopper-type amplifiers connected in series via the CPU and n-bit digitized conversion data D according to the output of each amplifier of the comparison unit 30_outIs output.
[0005]
With the above-mentioned conventional flash A / D converter, the input signal S_IN, For example, conversion data of n bits is obtained. For this purpose, the reference voltage generator 10 includes N = 2ⁿAnd the comparison unit 30 includes a first sampling capacitor, a first chopper-type amplifier, a second sampling capacitor, and a second chopper-type amplifier connected in series. N sets of parts are required.
[0006]
That is, in the above-described flash A / D converter, it is necessary to increase the number of voltage-dividing resistors and the number of chopper amplifiers by a power of two in order to improve the resolution of conversion. For example, an A / D converter having a conversion resolution of 9 bits requires 512 voltage-dividing resistors connected in series and the same number of capacitors and a set of chopper amplifiers, but requires a conversion resolution of 10 bits. In this case, the number of voltage dividing resistors connected in series needs to be 1024. Further, when a conversion resolution of 11 bits is required, the number of voltage dividing resistors connected in series needs to be as large as 2048.
[0007]
Here, for example, when A / D conversion is performed on an input voltage of 1 Vp-p with a conversion resolution of 10 bits, the required reference voltage, that is, the step amount of the divided voltage by the voltage dividing resistor is 1/1024 ≒ 1 mV. It becomes. This step voltage is almost the limit in consideration of the amount of noise generated on the semiconductor chip. If the conversion resolution is further increased by one bit, the number of voltage dividing resistors is required to be twice that of the stepping voltage. The voltage is further reduced by half compared to the case of 10 bits. For this reason, the area occupied by the voltage dividing resistor on the chip becomes large, and a layout taking into account the process variation of a unit resistance value of usually several Ω becomes difficult. Furthermore, since the step amount of the reference voltage obtained by dividing the voltage is very small, it is easily affected by noise generated on the substrate, and the conversion characteristics become unstable.
[0008]
In order to improve the conversion resolution without increasing the number of voltage dividing resistors, generate an intermediate voltage by a capacitor based on adjacent divided voltages, and encode by taking in the comparison result between the intermediate voltage and the input signal. A flash A / D converter which increases the conversion resolution of the A / D converter by 1 bit is disclosed in Japanese Patent No. 3268381, which is a patent document.
[0009]
[Patent Document 1]
Japanese Patent No. 3268381
[0010]
[Problems to be solved by the invention]
In the above-described conventional flash A / D converter, an intermediate voltage is directly generated by a capacitor with respect to a difference voltage sampled by the capacitor. If the amplitude of the sampled difference voltage is extremely small, the level of the output signal of the chopper amplifier becomes uncertain. For this reason, there is a disadvantage in that the conversion error increases in the least significant 1-bit data increased in the result of the A / D conversion.
[0011]
The present invention has been made in view of such circumstances, and an object of the present invention is to provide an A / D converter capable of improving conversion resolution, improving conversion accuracy, and improving stability of conversion characteristics without increasing a layout area. Is to provide.
[0012]
[Means for Solving the Problems]
To achieve the above object, an A / D converter according to the present invention is connected in series between two terminals to which a first reference voltage and a second reference voltage are applied, respectively, and generates at least two divided voltages. A plurality of voltage dividing resistance elements; and a switching circuit for applying an input signal to one electrode of the first capacitor during a sampling period and applying the divided voltage to the one electrode of the first capacitor during a comparison period. The input terminal is connected to the other electrode of the first capacitor, the output terminal is connected to one electrode of the second capacitor, the input terminal is held at a predetermined reference voltage during the sampling period, A first comparator for outputting a voltage corresponding to a difference between the divided voltage applied to the input terminal and the input signal during a period; and an input terminal connected to the other electrode of the second capacitor. A second comparator that holds the input terminal at a predetermined reference voltage during the sampling period and outputs a voltage corresponding to an output voltage of the first comparator input to the input terminal during the comparison period; Two third capacitors connected in series between the output terminals of the two first comparators corresponding to the two divided voltages adjacent to each other and having a capacitance half that of the second capacitor; A terminal is connected to a connection midpoint between the two third capacitors, the input terminal is held at a predetermined reference voltage during the sampling period, and a voltage corresponding to a voltage applied to the input terminal is output during the comparison period. And a third comparator.
[0013]
Further, the present invention preferably further includes an encoder that outputs conversion data corresponding to the input signal in accordance with the outputs of the first, second, and third amplifiers.
[0014]
In the present invention, preferably, the first, second, and third amplifiers are chopper amplifiers.
[0015]
Further, in the present invention, preferably, the first, second, and third amplifiers include a CMOS inverter and a switching element connected between an input terminal and an output terminal of the CMOS inverter. The switching element is held in a conductive state during the sampling period, and the switching element is held in a non-conductive state during the comparison period.
[0016]
According to the present invention, a signal corresponding to the difference between the reference voltage generated by the reference voltage generation circuit and the input signal is output by the first capacitor and the first amplifier, and further, the output symbol of the first amplifier is output. Is amplified by the second capacitor and the second amplifier and output to the encoder. Two third capacitors are connected in series between the output terminals of the adjacent first amplifiers, and the input terminal of the third amplifier is connected to the connection midpoint. Therefore, an intermediate voltage between the output voltages of two adjacent second amplifiers is input to the input terminal of the third amplifier. Since the capacitance value of the third capacitance element is half that of the second capacitor, the capacitance values seen from the input terminals of the second and third amplifiers are equal. The output signals of the second and third amplifiers are input to the encoder, and the conversion data is generated in accordance with the input signals, so that the conversion resolution is improved by one bit. Further, since the intermediate voltage is generated for the output signals of the adjacent first amplifiers, the stability of the generated intermediate voltage is improved, and the conversion accuracy can be improved.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a circuit diagram showing an embodiment of an A / D converter according to the present invention.
As illustrated, the A / D converter according to the present embodiment includes a reference voltage generation unit 10, a switching unit 20, a comparison unit 30A, and an encoder 40.
[0018]
First, each component of the A / D converter of the present embodiment will be described.
As shown, the reference voltage generator 10 includes a plurality of voltage dividing resistors R connected in series between two terminals to which reference voltages VRT and VRB are respectively applied.₁  , R₂  , ..., R_N  It is constituted by. A plurality of divided voltages (reference voltages) V from the connection midpoint of each voltage dividing resistor_ref1, V_ref2, ..., V_refNIs output. Here, the number N of the voltage dividing resistors corresponds to the conversion data D_out  Is determined by the number of bits n. In general, N = 2ⁿ  Becomes However, in the present embodiment, the N + 1-bit conversion data D is used by using N voltage-dividing resistors._out  Is obtained.
[0019]
As shown in the figure, the switching unit 20 includes a pair of switching elements SW corresponding to the respective reference voltages.₁₁, SW₁₂, SW₂₁, SW₂₂, ..., SW_{N + 1,1}, SW_{N + 1,2}It is constituted by. In each switching element pair, the switching element SW₁₁, SW₂₁, ..., SW_{N + 1,1}Is the signal S_INAnd the first capacitor C₁₁, C₂₁, ..., C_{N + 1,1}And the switching element SW₁₂, SW₂₂, ..., SW_{N + 1,2}Is the reference voltage V_ref1, V_ref2, ..., V_refNIs connected to the middle point of the voltage dividing resistor and the first capacitor C₁₁, C₂₁, ..., C_{N + 1,1}And one of the electrodes.
[0020]
The A / D converter according to the present embodiment shown in FIG. 1 alternately performs a sampling operation and a comparison operation to input an analog signal S._INConversion data D corresponding to_out  Is output. During the sampling period, in each switching element pair, the switching element SW₁₁, SW₂₁, ..., SW_{N + 1,1}Is conducting, switching element SW₁₂, SW₂₂, ..., SW_{N + 1,2}Is controlled to be in a cutoff state. Therefore, during the sampling period, the input signal S_INIs the first capacitor C₁₁, C₂₁, ..., C_{N + 1,1}Is input to one of the electrodes.
[0021]
During the comparison period, the switching element SW₁₁, SW₂₁, ..., SW_{N + 1,1}Is in cutoff state, switching element SW₁₂, SW₂₂, ..., SW_{N + 1,2}Are controlled to be conductive. Therefore, during the comparison period, the reference voltage V_ref1, V_ref2, ..., V_refNIs the first capacitor C₁₁, C₂₁, ..., C_{N + 1,1}Is input to one of the electrodes.
[0022]
The comparison unit 30A includes, as shown in FIG._ref1, V_ref2, ..., V_refN, A first capacitor, a first chopper-type amplifier, a second capacitor, and a second chopper-type amplifier connected in series are provided. Further, two third capacitors are connected in series between the output terminals of the adjacent first chopper type amplifiers, and the input terminal of the third chopper type amplifier is connected to the connection midpoint.
[0023]
In the present embodiment, the first and second chopper amplifiers are configured by a CMOS inverter and a switching element provided between an input terminal and an output terminal of the inverter. When the switching element is conducting, the input terminal and the output terminal of the inverter are connected to the threshold voltage V of the inverter._THIs set to On the other hand, when the switching element is in the cutoff state, the inverter amplifies the signal applied to the input terminal with a negative gain G and outputs the amplified signal to the output terminal.
[0024]
In the comparison unit 30A, a comparison circuit is configured by a chopper type amplifier and a capacitor connected to the input terminal thereof. For example, the first capacitor and the first chopper amplifier allow the input signal S_INAnd reference voltage V_refiA signal obtained by amplifying the difference from (i = 1, 2,..., N) by the gain G1 of the first chopper amplifier is obtained. Therefore, the input signal S depends on the level of the output signal of the first chopper type amplifier._INAnd reference voltage V_refiYou can see the result of comparison with.
[0025]
Further, as shown in FIG. 1, in the A / D converter of the present embodiment, a second capacitor is provided on the output side of a first-stage comparison circuit composed of a first capacitor and a first chopper-type amplifier. And a second-stage comparison circuit comprising a second chopper-type amplifier. The output signal of the first chopper-type amplifier is further inverted and amplified by the second capacitor and the second chopper-type amplifier with the gain G2 of the second chopper-type amplifier, and the result is output to the encoder.
[0026]
As described above, in the A / D converter of the present embodiment, as a result of amplification by the two-stage chopper type amplifier, for example, the input signal S_INAnd reference voltage V_refiEven if there is only a slight difference in the voltage levels of the signals, the difference can be amplified and supplied to the encoder. For this reason, the conversion accuracy and the stability of the conversion result can be improved.
[0027]
FIG. 2 shows a configuration of a partial circuit of the A / D converter of the present embodiment including a part 30a of the comparison unit 30A. Hereinafter, the configuration of the comparison unit of the A / D converter of the present embodiment will be described with reference to FIG.
In the partial circuit shown in FIG. 2, two adjacent reference voltages V_refiAnd V_{refi + 1}Is output. Reference voltage V_refiIs the switching element SW_i2Through the first capacitor C_i1And the reference voltage V_{refi + 1}Is the switching element SW_i2Through the first capacitor C_{i1 + 1}Is entered.
[0028]
In comparison section 30a, reference voltage V_refiCorresponding to the first capacitor C_i1, First chopper amplifier CMP_i1, The second capacitor C_i2And first chopper type amplifier CMP_i2Are connected in series. Similarly, the reference voltage V_{refi + 1}Corresponding to the first capacitor C_{i + 1,1}  , First chopper amplifier CMP_{i + 1,1}  , The second capacitor C_{i + 1,2}  And a second chopper amplifier CMP_{i + 1,2}  Are connected in series.
[0029]
Further, an adjacent first chopper amplifier CMP_i1And CMP_{i + 1,1}  Between the output terminals of the third capacitor C_i3And C_i4Are connected in series. Then, the third capacitor C_i3And C_i4Is connected to a third chopper type amplifier CMP._i3Input terminals are connected.
Third capacitor C_i3, C_i4The third chopper amplifier forms an intermediate voltage generating circuit 30b.
[0030]
Second capacitor C_i2And C_{i + 1,2}  Is the capacitance of the third capacitor C_i3And C_i4Is half of that, that is, C / 2.
For this reason, the second chopper amplifier CMP_i2, CMP_{i + 1,2}  And third chopper amplifier CMP_i3C are all seen from the input terminal of the input terminal.
[0031]
By the comparing section 30A having the above-described configuration, the input signal S_INAnd each reference voltage V generated by the reference voltage generator 10_ref1, V_ref2, ..., V_refNAnd the respective comparison results are output to the encoder 40.
[0032]
The encoder 40 receives the input signal S according to each comparison result input from the comparison unit 30A._INConversion data D corresponding to the voltage level of_out  Is output.
[0033]
In the A / D converter of the present embodiment, the third capacitor (C_i3And C_i4) And a third chopper amplifier CMP_i3The conversion resolution is increased by one bit by generating the intermediate voltage based on the comparison result of two adjacent signals and outputting the intermediate voltage to the encoder 40. That is, as compared with the conventional A / D converter, in the present embodiment, one bit more conversion data can be obtained by generating an intermediate voltage based on the output of the adjacent first chopper type amplifier. For example, N = 2ⁿ  Conventionally, an A / D converter that generates a reference voltage using a plurality of voltage-dividing resistors can obtain only n-bit conversion data. However, according to the A / D converter of the present embodiment, n + 1-bit conversion data D_out  Can be obtained.
[0034]
Next, the operation of the A / D converter of the present embodiment will be described.
As described above, the A / D converter of the present embodiment alternately performs the sampling operation and the comparison operation.
[0035]
During the sampling period, the switching operation of the switching unit 20 causes the input signal S_INIs the first capacitor C of the comparison unit 30A.₁₁, C₂₁, ..., C_{N + 1,1}Is input to one of the electrodes.
On the other hand, at this time, the first chopper amplifier CMP₁₁, CMP₂₁, ..., CMP_{N + 1,1}And second chopper amplifier CMP₁₂, CMP₂₂, ..., CMP_{N + 1,2}In this case, the switching element provided between the input and the output conducts, and both the input terminal and the output terminal are reset. As a result, the input / output terminal becomes, for example, the threshold voltage level V_THIs held. Then, the first capacitor C₁₁, C₂₁, ..., C_{N + 1,1}Has an input signal S_INAnd the threshold voltage V of the first chopper type amplifier_THAnd the difference (S_IN-V_TH) Is accumulated.
[0036]
Following the sampling operation, a comparison operation is performed. During the comparison period, the reference voltage V generated by the reference voltage generator 10 due to the switching operation of the switching unit 20._ref1, V_ref2, ..., V_refNIs the first capacitor C of the comparison unit 30A.₁₁, C₂₁, ..., C_{N + 1,1}Is entered. At this time, in the first and second chopper amplifiers, the switching element between the input terminal and the output terminal is disconnected. Therefore, the first capacitor C₁₁, C₂₁, ..., C_{N + 1,1}Is stored.
[0037]
During the comparison operation, the first chopper amplifier CMP_i1Voltage applied to the input terminal of_inIs the first capacitor C_i1Stored charge and the first capacitor C_i1Reference voltage V input to_refiIt is determined by the following equation.
[0038]
(Equation 1)
V_in= V_refi− (S_IN-V_TH)
= ΔV + V_TH                    … (1)
[0039]
In equation (1), ΔV = V_refi-S_INThat is, the reference voltage V_refiAnd the input signal S_INAnd the voltage difference. As shown in equation (1), during the comparison period, the first chopper amplifier CMP_i1Is connected to the threshold voltage V of the chopper type amplifier._THReference voltage V_refiAnd the input signal S_INIs input. Therefore, the first chopper amplifier CMP_i1, The difference voltage amplified by the gain of the chopper type amplifier is output.
[0040]
FIG. 3 shows the input / output characteristics of the chopper amplifier. In FIG. 3, the horizontal axis represents the input voltage V of the chopper type amplifier._inAnd the vertical axis indicates the output voltage V_out  Is shown. As described above, the chopper type amplifier includes a CMOS inverter. Therefore, the chopper amplifier has the input / output characteristics of the inverter. As shown in FIG. 3, the chopper type amplifier has a threshold voltage V_THIt has a substantially linear gain characteristic in the vicinity. Here, the threshold voltage V_THAssuming that the nearby gain is G, the threshold voltage V_THIn the vicinity, the amplitude ΔV of the input signal is amplified by the gain G. That is, the output signal V of the chopper type amplifier_out  Is ΔV · G.
[0041]
The output signal of the first chopper type amplifier is input to the input terminal of the second chopper type amplifier via the second capacitor. Therefore, the difference voltage ΔV · G amplified by the first chopper type amplifier is further amplified by the second chopper type amplifier and input to the encoder 40.
[0042]
In the A / D converter according to the present embodiment, as shown in FIGS. 1 and 2, the output voltage V_a  And V_c  According to the third capacitor C_i3And C_i4The intermediate voltage V_b  Is generated. Then, the generated intermediate voltage V_b  Is amplified by the third chopper type amplifier, and the output is input to the encoder 40.
[0043]
As shown in FIG. 2, the third capacitor C_i3, C_i4And third chopper amplifier CMP_i3Constitutes the intermediate voltage generation circuit 30b. In the intermediate voltage generating circuit 30b, the third chopper type amplifier CMP_i3Is output from an adjacent second chopper amplifier CMP_i2And CMP_{i + 1,2}  Becomes an intermediate voltage of the output signal.
[0044]
FIG. 4 shows the output signal V of the adjacent first chopper amplifier during the sampling period and the comparison period._a  , V_c  And intermediate voltage V output by intermediate voltage generation circuit 30b_b  FIG. 4 is a signal waveform diagram showing a waveform of FIG. Hereinafter, the operation of the intermediate voltage generating circuit 30b will be described with reference to FIGS.
[0045]
During the sampling period, the third chopper amplifier CMP_i3As in the first and second chopper amplifiers, the switching element provided between the input and output terminals is in a conductive state, and the input terminal and the output terminal are connected to the threshold voltage V._THIs held in. Then, the switching element is disconnected during the comparison period.
[0046]
In FIG. 2, for example, a first chopper type amplifier CMP during a comparison period_i1Output voltage to V_a  , Another adjacent first chopper amplifier CMP_{i + 1,1}  Output voltage to V_c  Then, the third capacitor C_i3And C_i4Are equal, the ND of the connection midpoint is_i  Voltage V_b  Is the voltage V_a  And V_c  Intermediate value (V_a  + V_c  ) / 2.
[0047]
As shown in FIG. 4, for example, during the sampling period, the second chopper amplifier CMP_i2And CMP_{i + 1,2}  Input terminal and third chopper amplifier CMP_i3Are both threshold voltages V_THIs held in. During the comparison period, the first chopper amplifier CMP_i1Output voltage V_a  Is the input signal S_INAnd reference voltage V_refiAnd another adjacent first chopper-type amplifier CMP_{i + 1,1}  Output voltage V_b  Is the input signal S_INAnd reference voltage V_{refi + 1}Confirm based on Then, as shown in FIG. 4, the third capacitor C_i3And C_i4Connection midpoint ND_i  And the intermediate voltage V_b  Appears.
[0048]
Voltage V_a  And V_c  Is a second chopper type amplifier CMP_i2And CMP_{i + 1,2}And the intermediate voltage V_b  Is a third chopper amplifier CMP_i3The outputs of these amplifiers are output to the encoder 40.
As described above, the second capacitor C_i2And C_{i + 1,2}  Of the third capacitor C_i3And C_i4Is C / 2. Therefore, the capacitance values connected to the input terminals of the second chopper type amplifier and the third chopper type amplifier are all equal, and the gain characteristics of these chopper type amplifiers are also equal.
[0049]
As described above, according to the present embodiment, in the comparison unit 30A, two third capacitors are connected in series between the output terminals of the first chopper-type amplifiers corresponding to the adjacent reference voltages. The intermediate terminal of the third capacitor is connected to the input terminal of the third chopper amplifier to form an intermediate voltage generating circuit 30b. As a result, an intermediate voltage between the output voltages of the two adjacent first chopper type amplifiers is output from a connection point between the two third capacitors, and the intermediate voltage is further amplified by the third chopper type amplifier. Since the result is input to the encoder 40 together with the output signal of the second chopper type amplifier, the conversion data D obtained by the encoder 40_out  Is increased by one bit as compared with the case where the intermediate voltage generating circuit 30b is not provided, and the conversion resolution is improved. Further, in the present embodiment, the intermediate voltage generated by the intermediate voltage generating circuit 30b is generated based on the difference voltage amplified by the first capacitor and the first chopper type amplifier, so that the level of the intermediate voltage is stabilized. Thus, the stability of the output data of the encoder can be improved.
[0050]
Second embodiment
FIG. 5 is a circuit diagram showing a second embodiment of the A / D converter according to the present invention. As shown in the figure, the A / D converter according to the present embodiment performs the two-stage comparison using the coarse comparison circuit and the fine comparison circuit to obtain the input signal S._INConversion data D according to_out  , Which is a so-called sub-range type A / D converter.
[0051]
As shown in FIG. 5, the A / D converter according to the present embodiment includes a resistor array 100, fine comparison circuits 110 and 120, a coarse comparison circuit 130, and an error correction circuit 140.
[0052]
Hereinafter, each component of the A / D converter of the present embodiment will be described.
As shown in FIG. 5, the resistor array 100 includes a plurality of resistors arranged in a matrix. For example, the number of resistors constituting the resistor array 100 is M × N. That is, in the resistor array 100, one row has M resistors, and a total of N rows. The M × N resistors in the resistor array 100 are all connected in series as shown in FIG.
Here, in order to simplify the notation, for example, consider a resistor array having the same number of resistors in each row and each column. For example, the resistor array 100 is configured by N × N resistors.
[0053]
The number N of resistors in each row and each column of the resistor array 100 described above is, for example, N = 2ⁿIt is. In this case, the coarse comparison circuit 130 obtains n-bit conversion data, and the fine comparison circuit 110 or 120 generally obtains the same n-bit conversion data. Then, as a result of summing the comparison results of the coarse comparison circuit 130 and the fine comparison circuits 110 and 120 by the error correction circuit 140, 2n-bit conversion data is obtained.
[0054]
In the A / D converter according to the present embodiment, the fine comparison circuits 110 and 120 incorporate the above-described configuration of the first embodiment of the present invention, so that the fine comparison circuits 110 and 120 respectively convert n + 1-bit conversion data. Is obtained. As a result, the A / D converter of the present embodiment shown in FIG._out  Can be obtained.
[0055]
In the present embodiment, the fine comparison circuits 110 and 120 include, for example, the switching unit 20, the comparison unit 30A, and the encoder 40 of the A / D converter according to the first embodiment of the present invention shown in FIG. Reference voltage V input to fine comparison circuit 110_r10  , V_r11  , ..., V_r1N  And the reference voltage V input to the fine comparison circuit 120_r20  , V_r21  , ..., V_r2N  Is a divided voltage obtained by dividing the resistance of one of the resistances of the N rows in the resistance array 100.
[0056]
The coarse comparison circuit 130 includes an A / D converter that outputs normal n-bit conversion data. For example, as an example, the coarse comparison circuit 130 includes the switching unit 20, the comparison unit 30A, and the encoder 40 of the conventional A / D converter shown in FIG.
[0057]
Reference voltage V input to coarse comparison circuit 130_r31  , V_r32  , ..., V_r3N  Is a reference voltage generated in the resistor array 100 with N resistors as one unit of voltage division, as shown in FIG.
The coarse comparison circuit 130 has N input reference voltages V_r31  , V_r32  , ..., V_r3N  And the input signal S_INAnd outputs n-bit conversion data as a result of the comparison.
[0058]
The error correction circuit 140 removes a conversion error based on the n + 1-bit and n-bit conversion data generated by the fine comparison circuits 110 and 120 and the coarse comparison circuit 130, and converts a total of 2n + 1-bit conversion data D_out  Is output.
[0059]
Next, the operation of the A / D converter according to the present embodiment will be described.
As described above, the A / D converter according to the present embodiment performs conversion data D by two-stage comparison operation of coarse comparison and fine comparison._out  Is output. The coarse comparison is performed by the coarse comparison circuit 130._INN-bit conversion data D according to₁  (D_out  (The upper n bits). The fine comparison is performed by the fine comparison circuits 110 and 120._INConversion data D of n + 1 bits according to₂₁And D₂₂(D_out  (The lower n + 1 bits).
[0060]
First, in the rough comparison, the input signal S_IN(That is, VRT-VRB, which is the difference between the reference voltages VRT and VRB), is substantially equal to N._r31  , V_r32  , ..., V_r3N  Is input to the coarse comparison circuit 130. By the coarse comparison circuit 130, the input signal S_INAnd reference voltage V_r31  , V_r32  , ..., V_r3N  And as a result, the conversion data D of n bits₁₁Is obtained.
[0061]
Next, a fine comparison is performed according to the result of the rough comparison. In the fine comparison, based on the result of the coarse comparison, the input signal S_IN, The reference voltage V divided by the resistance of one row of the resistor array 100 corresponding to the sub-range in accordance with which sub-range of the VRT-VRB the voltage level of_r10  , V_r11  , ..., V_r1N  Or V_r20  , V_r21  , ..., V_r2N  And input it to the fine comparison circuit 110 or 120. By the fine comparison circuit 110 or 120, the input signal S_INAnd the input reference voltage, and based on the result of the comparison, n + 1-bit conversion data D₂₁Or D₂₂Is obtained.
[0062]
Then, the n-bit conversion data D obtained by the coarse comparison circuit 130₁₁And n + 1-bit conversion data D obtained by the fine comparison circuit 110 or 120₂₁Or D₂₂Is input to the error correction circuit 140, the error of the conversion data is removed by the error correction circuit 140, and the 2n + 1-bit conversion data D_out  Is output.
[0063]
As described above, in the A / D converter of the present embodiment, the input signal S is obtained by the two-stage comparison operation of the coarse comparison by the coarse comparison circuit 130 and the fine comparison by the fine comparison circuits 110 and 120._IN2n + 1-bit conversion data D according to the voltage level of_out  Can be obtained.
[0064]
In the A / D converter of the present embodiment, two fine comparison circuits 110 and 120 are provided for fine comparison. According to the comparison result of the coarse comparison circuit 130, the fine comparison circuits 110 and 120 operate alternately and output the conversion result of the lower n + 1 bits, thereby improving the conversion speed.
[0065]
Here, the coarse comparison circuit 130 performs the conversion at the conversion period T1, and the higher-order n-bit conversion data D₁  And the fine comparison circuits 110 and 120 perform conversion at a lower speed than the coarse comparison circuit 130, for example, at a conversion period of 2T1, and convert the lower n + 1 bit conversion data D₂₁, D₂₂Output. The output timing of the converted data at this time is, for example, as shown in FIG.
[0066]
As shown in FIG. 6, upon receiving the conversion result of the coarse comparison circuit 130, the fine comparison circuits 110 and 120 alternately perform the conversion operation. As shown in FIG. 6A, the coarse comparison circuit 130 outputs the upper n bits of the conversion results A1, B1, C1, and D1 every conversion period T1. Then, as shown in FIG. 6B, for example, the fine comparison circuit 110 outputs a conversion result A2 of lower n + 1 bits according to the conversion result A1. It takes 2T1 time from when the conversion result A1 of the coarse comparison circuit is determined to when the conversion result A2 of the fine comparison circuit 110 is determined.
[0067]
Next, as shown in FIG. 6C, the conversion result B2 of the lower n + 1 bits is output by the fine comparison circuit 120 in accordance with the conversion result B1 of the coarse comparison circuit 130. It takes 2T1 time from when the conversion result B1 of the coarse comparison circuit is determined to when the conversion result B2 of the fine comparison circuit 110 is determined.
[0068]
As shown in FIG. 6D, according to the n-bit conversion result from the coarse comparison circuit 130 and the n + 1-bit conversion result from the fine comparison circuit 110 or 120, the error correction circuit 140 converts the 2n + 1-bit conversion result. A3, B3, C3 and D3 are sequentially output. Since the fine comparison circuits 110 and 120 alternately operate upon receiving the conversion result of the coarse comparison circuit 130, the conversion results A3, B3, C3 and D3 are finally output in the conversion cycle T1 of the coarse comparison circuit 130.
[0069]
As described above, according to the A / D converter of the present embodiment, the input signal S_IN, The n-bit conversion data D₁  And a conversion data D of lower n + 1 bits according to the conversion result of the coarse comparison circuit 130.₂₁Or D₂₂Is provided, the input signals S_IN, The conversion data D of 2n + 1 bits_out  Is obtained. Further, since the fine comparison circuits 110 and 120 are alternately operated, the conversion data D can be obtained at the conversion cycle of the coarse comparison circuit 130 even in a relatively low-speed conversion circuit._out  Can be obtained. By incorporating the configuration of the A / D converter of the first embodiment of the present invention into the fine comparison circuits 110 and 120, the conversion data D can be obtained without changing the configuration of the resistor array 100._out  And the change resolution can be improved.
[0070]
In the present embodiment, a coarse comparison circuit 130 is provided with N comparators by using a so-called sub-range type A / D converter that performs conversion in two stages by dividing the upper n bits and the lower n + 1 bits to perform a fine comparison. Each of the circuits 110 and 120 is provided with 2N + 1 comparators, and a total of 5N + 2 comparators can obtain a conversion result of 2n + 1 bits. For example, when an A / D converter having a total of 11 bits consisting of the upper 5 bits and the lower 6 bits is 11 bits (n = 5, N = 32), the number of comparators is 162 in total.
[0071]
On the other hand, when a normal flash A / D converter is used without using the sub-range type of the present embodiment, for example, when the configuration of the first embodiment of the present invention is used, the conversion result of 11 bits is calculated. In order to obtain (n = 10, N = 1024), a total of 2N + 1 comparators, ie, 2049 comparators, are required. That is, the number of comparators can be significantly reduced by using the sub-range type A / D converter shown in the second embodiment. Also, by configuring the intermediate voltage generation circuits in the fine comparison circuits 110 and 120, the conversion resolution can be improved by one bit, as in the A / D converter according to the first embodiment of the present invention.
[0072]
【The invention's effect】
As described above, according to the A / D converter of the present invention, an intermediate voltage is generated by a capacitor for an adjacent sampling voltage, and the intermediate voltage is amplified by an amplifier and output to an encoder. The resolution of bits can be improved. As a result, there is an advantage that the conversion resolution can be improved without increasing the number of voltage dividing resistors for generating the reference voltage, and the conversion accuracy and the stability of the conversion characteristics can be improved while suppressing an increase in the circuit scale.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a first embodiment of an A / D converter according to the present invention.
FIG. 2 is a partial circuit diagram showing a configuration of a part of the A / D converter of the embodiment.
FIG. 3 is a diagram illustrating input / output characteristics of a chopper type amplifier.
FIG. 4 is a waveform chart showing an operation of the intermediate voltage generation circuit.
FIG. 5 is a circuit diagram showing a second embodiment of the A / D converter according to the present invention.
FIG. 6 is a waveform chart showing the operation of the second embodiment of the A / D converter of the present invention.
FIG. 7 is a circuit diagram showing a configuration example of a conventional A / D converter.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Reference voltage generation part, 20 ... Switching part, 30, 30A ... Comparison part, 40 ... Encoder, 100 ... Resistor array, 110,120 ... Precision comparison circuit, 130 ... Coarse comparison circuit, 140 ... Error correction circuit.

Claims (4)

A reference voltage generation circuit that is connected in series between two terminals to which the first reference voltage and the second reference voltage are respectively applied and includes a plurality of voltage dividing resistors that generate at least two divided voltages;
A switching circuit for applying an input signal to one electrode of the first capacitor during a sampling period and applying the divided voltage to the one electrode of the first capacitor during a comparison period;
An input terminal is connected to the other electrode of the first capacitor, an output terminal is connected to one electrode of the second capacitor, and the input terminal is held at a predetermined reference voltage during the sampling period. A first comparator that outputs a voltage corresponding to a difference between the divided voltage applied to the input terminal and the input signal,
An input terminal is connected to the other electrode of the second capacitor, the input terminal is held at a predetermined reference voltage during the sampling period, and the input terminal of the first comparator is input to the input terminal during the comparison period. A second comparator that outputs a voltage corresponding to the output voltage;
Two third capacitors, which are connected in series between two output terminals of the first comparator corresponding to the two divided voltages adjacent to each other and have a capacitance value half that of the second capacitor;
An input terminal is connected to a connection midpoint of the two third capacitors, the input terminal is held at a predetermined reference voltage during the sampling period, and a voltage corresponding to an applied voltage of the input terminal is applied during the comparison period. An A / D converter having an output third comparator. 2. The A / D converter according to claim 1, further comprising: an encoder that outputs conversion data according to the input signal according to the outputs of the first, second, and third amplifiers. 2. The A / D converter according to claim 1, wherein said first, second, and third amplifiers are chopper amplifiers. The first, second, and third amplifiers include a CMOS inverter and a switching element connected between an input terminal and an output terminal of the CMOS inverter,
2. The A / D converter according to claim 1, wherein the switching element is held in a conductive state during the sampling period, and the switching element is held in a non-conductive state during the comparison period.

Images