CN203368422U - Chip enabling signal delay control circuit - Google Patents
Chip enabling signal delay control circuit Download PDFInfo
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- CN203368422U CN203368422U CN2013203730223U CN201320373022U CN203368422U CN 203368422 U CN203368422 U CN 203368422U CN 2013203730223 U CN2013203730223 U CN 2013203730223U CN 201320373022 U CN201320373022 U CN 201320373022U CN 203368422 U CN203368422 U CN 203368422U
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- chip
- divider resistance
- delay control
- switching tube
- enable signal
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Abstract
The utility model belongs to the circuit field, and provides a chip enabling signal delay control circuit. The chip enabling signal delay control circuit is connected with a chip U1 and a power supply. The power supply supplies power to the chip U1. The chip enabling signal delay control circuit comprises a delay control module which is connected with the power supply and the chip U1, wherein the delay control module controls delaying of the an enabling signal when the chip is electrified and in power failure. In the chip enabling signal delay control circuit, through delaying enabling signal of the chip in electrification, power failure and a process with instable voltage by the delay control module, a problem of abnormal chip operation caused by operation of the enabling signal in electrification and power failure process of the chip can be settled.
Description
Technical field
The utility model belongs to circuit field, relates in particular to a kind of chip enable signal delay control circuit.
Background technology
Integrated chip is more and more extensive in the use of modern industry, its with high efficiency the use in intelligent system the most outstanding again.
The level that enables of existing integrated chip is generally to produce according to the dividing potential drop of divider resistance, and when input supply voltage shake occurs or falls, enable signal also can be shaken thereupon, and, in the chip normal operation, is to need stable enable signal.In existing a lot of chips, the power supply of power section circuit is what to separate with the power supply of chip autophage, also has the functions such as the control of enabling, the delay control powered on and operating state indication simultaneously.These control signal correlations have just been brought power supply and the problem that enables the priority of control signal.The DC/DC control chip of external MOSFET particularly, the power supply of the power supply of its power section and control chip oneself, enable to control in the situation of all separating more outstanding.
The utility model content
The utility model provides a kind of chip enable signal delay control circuit, be intended to solve existing chip power on and the process of power down spread of voltage in and the enable signal synchronous working causes the abnormal problem of chip operation.
In order to solve the problems of the technologies described above, the utility model is achieved in that a kind of chip enable signal delay control circuit, with chip U1, with power supply, is connected, and described power supply is described chip U1 power supply, and described chip enable signal delay control circuit comprises:
Be connected with described chip U1 with described power supply, the enable signal of inputting described chip U1 carried out the time delay control module of delay process when described chip U1 powers on power down.
Further, described time delay control module comprises:
Divider resistance R1, divider resistance R2, divider resistance R3, divider resistance R4, divider resistance R5, filter capacitor C1, the first switching tube;
The supply voltage input of the first end of described divider resistance R1 and described chip U1 is connected with described power supply respectively, the second end of described divider resistance R1 respectively with the first end of described divider resistance R2, the first end of described filter capacitor C1, the enable signal end of the cold end of described the first switching tube and described chip U1 connects, the hot end of described the first switching tube is connected with the first end of described divider resistance R4, described the first switch controlled end is connected with the first end of described divider resistance R3 with the second end of described divider resistance R5 respectively, the first end of described divider resistance R5 is connected with described power supply, the second end of described divider resistance R2, the second end of described filter capacitor C1, the second end of described divider resistance R3 and the second end of described divider resistance R4 are connected to ground altogether.
Further, described the first switching tube adopts positive-negative-positive triode Q1, the control end that the base stage of described positive-negative-positive triode Q1 is the first switching tube, the current collection of described positive-negative-positive triode Q1 is the hot end of the first switching tube very, and the emission of described positive-negative-positive triode Q1 is the cold end of the first switching tube very.
Further, described the first switching tube adopts P type metal-oxide-semiconductor Q2, the control end that the grid of described P type metal-oxide-semiconductor Q2 is the first switching tube, the hot end that the drain electrode of described P type metal-oxide-semiconductor Q2 is the first switching tube, the cold end that the source electrode of described P type metal-oxide-semiconductor Q2 is the first switching tube.
In the utility model, by time delay control module control chip power on and the process of power down spread of voltage in the enable signal time delay, can solve existing chip power on and the power down process in, enable signal still work causes the abnormal problem of chip operation.
The accompanying drawing explanation
Fig. 1 is the modular structure figure of the chip enable signal delay control circuit that provides of the utility model embodiment;
Fig. 2 is the circuit structure diagram of the chip enable signal delay control circuit that provides of the utility model embodiment;
Fig. 3 is the circuit structure diagram of the chip enable signal delay control circuit that provides of the utility model the first embodiment;
Fig. 4 is the circuit structure diagram of the chip enable signal delay control circuit that provides of the utility model the second embodiment.
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein is only in order to explain the utility model, and be not used in restriction the utility model.
Below in conjunction with specific embodiment, specific implementation of the present utility model is described in detail:
Fig. 1 shows the modular structure of the chip enable signal delay control circuit that utility model embodiment provides, and for convenience of explanation, only enumerates the part relevant to the present embodiment.
As shown in Figure 1, the chip enable signal delay control circuit, be connected with power supply VCC with chip U1, and power supply VCC is chip U1 power supply, and the chip enable signal delay control circuit comprises:
Be connected with chip U1 with power supply VCC, the enable signal of input chip U1 carried out the time delay control module 101 of delay process when chip U1 powers on power down.
As shown in Figure 2, as the utility model one embodiment, the time delay control module comprises:
Divider resistance R1, divider resistance R2, divider resistance R3, divider resistance R4, divider resistance R5, filter capacitor C1, the first switching tube 1011;
The supply voltage input of the first end of divider resistance R1 and chip U1 is connected with power supply VCC respectively, the second end of divider resistance R1 respectively with the first end of divider resistance R2, the first end of filter capacitor C1, the enable signal end of the cold end of the first switching tube 1011 and chip U1 connects, the hot end of the first switching tube 1011 is connected with the first end of divider resistance R4, the first switching tube 1011 control ends are connected with the first end of divider resistance R3 with the second end of divider resistance R5 respectively, the first end of divider resistance R5 is connected with power supply VCC, the second end of divider resistance R2, the second end of filter capacitor C1, the second end of divider resistance R3 and the second end of divider resistance R4 are connected to ground altogether.
embodiment mono-:
Fig. 3 shows the circuit structure of the chip enable signal delay control circuit that first embodiment of the invention provides, and for convenience of explanation, only shows the part relevant to first embodiment of the invention, and details are as follows:
As the utility model one embodiment, the first switching tube 1011 adopts positive-negative-positive triode Q1, the control end that the base stage of positive-negative-positive triode Q1 is the first switching tube 1011, the current collection of positive-negative-positive triode Q1 is the hot end of the first switching tube 1011 very, and the emission of positive-negative-positive triode Q1 is the cold end of the first switching tube 1011 very.
Below the circuit structure that provides with the utility model embodiment the operation principle of chip enable signal delay control circuit is described.
Due to chip, in (opening power) process that powers on, supply voltage always there will be the shake of certain hour.Control by divider resistance R1 and divider resistance R2 the enable signal powered on, after enabling effectively, if shake Huo Die road appears in power supply VCC power supply again, will make chip operation abnormal.In the utility model embodiment, avoid the power end VCC voltage dithering time of chip U1 by the time delay control module, when power down reaches the setting thresholding, allow chip U1 enable signal end ENA far below chip U1 enable effective judgement threshold (as 0.7V), so just solved the impact of the shake of chip power supply in power up on chip enable.Because enable signal only has requirement to level, to differentiating the rate of rise no requirement (NR) of level, therefore can be to carrying out any time delay after powering on, making power on stable after enable signal control chip work more again, the parameter that can change divider resistance R3 and divider resistance R6 is arranged the voltage of the control end of positive-negative-positive triode, be that the user can as required, arrange power supply VCC and fall thresholding.When power supply VCC drops to this thresholding, enable signal just can end, and the enable signal end of chip U1 is without effectively enabling control signal, and chip U1 does not work, and after the normal stable power-supplying of power end of chip U1, enable signal just can conducting drive chip U1 normal operation.
embodiment bis-:
Fig. 4 shows the circuit structure of the chip enable signal delay control circuit that second embodiment of the invention provides, and for convenience of explanation, only shows the part relevant to second embodiment of the invention, and details are as follows:
As the utility model one embodiment, the first switching tube 1011 adopts P type metal-oxide-semiconductor Q2, the control end that the grid of P type metal-oxide-semiconductor Q2 is the first switching tube 1011, the hot end that the drain electrode of P type metal-oxide-semiconductor Q2 is the first switching tube 1011, the cold end that the source electrode of P type metal-oxide-semiconductor Q2 is the first switching tube 1011.
In the utility model, by time delay control module control chip power on and the process of power down spread of voltage in the enable signal time delay, can solve existing chip power on and the power down process in, enable signal still work causes the abnormal problem of chip operation.
The foregoing is only preferred embodiment of the present utility model; not in order to limit the utility model; all any modifications of doing within spirit of the present utility model and principle, be equal to and replace and improvement etc., within all should being included in protection range of the present utility model.
Claims (4)
1. a chip enable signal delay control circuit, be connected with power supply with chip U1, and described power supply is described chip U1 power supply, it is characterized in that, described chip enable signal delay control circuit comprises:
Be connected with described chip U1 with described power supply, the enable signal of inputting described chip U1 carried out the time delay control module of delay process when described chip U1 powers on power down.
2. chip enable signal delay control circuit as claimed in claim 1, is characterized in that, described time delay control module comprises:
Divider resistance R1, divider resistance R2, divider resistance R3, divider resistance R4, divider resistance R5, filter capacitor C1, the first switching tube;
The supply voltage input of the first end of described divider resistance R1 and described chip U1 is connected with described power supply respectively, the second end of described divider resistance R1 respectively with the first end of described divider resistance R2, the first end of described filter capacitor C1, the enable signal end of the cold end of described the first switching tube and described chip U1 connects, the hot end of described the first switching tube is connected with the first end of described divider resistance R4, described the first switch controlled end is connected with the first end of described divider resistance R3 with the second end of described divider resistance R5 respectively, the first end of described divider resistance R5 is connected with described power supply, the second end of described divider resistance R2, the second end of described filter capacitor C1, the second end of described divider resistance R3 and the second end of described divider resistance R4 are connected to ground altogether.
3. chip enable signal delay control circuit as claimed in claim 2, it is characterized in that, described the first switching tube adopts positive-negative-positive triode Q1, the control end that the base stage of described positive-negative-positive triode Q1 is the first switching tube, the current collection of described positive-negative-positive triode Q1 is the hot end of the first switching tube very, and the emission of described positive-negative-positive triode Q1 is the cold end of the first switching tube very.
4. chip enable signal delay control circuit as claimed in claim 2, it is characterized in that, described the first switching tube adopts P type metal-oxide-semiconductor Q2, the control end that the grid of described P type metal-oxide-semiconductor Q2 is the first switching tube, the hot end that the drain electrode of described P type metal-oxide-semiconductor Q2 is the first switching tube, the cold end that the source electrode of described P type metal-oxide-semiconductor Q2 is the first switching tube.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013203730223U CN203368422U (en) | 2013-06-26 | 2013-06-26 | Chip enabling signal delay control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013203730223U CN203368422U (en) | 2013-06-26 | 2013-06-26 | Chip enabling signal delay control circuit |
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| CN203368422U true CN203368422U (en) | 2013-12-25 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2013203730223U Expired - Fee Related CN203368422U (en) | 2013-06-26 | 2013-06-26 | Chip enabling signal delay control circuit |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107505936A (en) * | 2017-09-30 | 2017-12-22 | 中国航天科技集团公司烽火机械厂 | A kind of Testing and emission system |
| CN108155788A (en) * | 2017-12-07 | 2018-06-12 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of adjustable energy supply startup control circuit of voltage threshold |
| CN112583246A (en) * | 2020-12-17 | 2021-03-30 | 英麦科（厦门）微电子科技有限公司 | Chip enabling circuit |
| CN113054835A (en) * | 2021-03-05 | 2021-06-29 | 山东英信计算机技术有限公司 | Delay starting method, system and related device of circuit module |
| CN113741671A (en) * | 2021-10-13 | 2021-12-03 | 瑞芯微电子股份有限公司 | Power supply power-on control method, system, storage medium and device |
| CN114123736A (en) * | 2021-10-29 | 2022-03-01 | 广东汇芯半导体有限公司 | Semiconductor circuit and application device thereof |
-
2013
- 2013-06-26 CN CN2013203730223U patent/CN203368422U/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107505936A (en) * | 2017-09-30 | 2017-12-22 | 中国航天科技集团公司烽火机械厂 | A kind of Testing and emission system |
| CN108155788A (en) * | 2017-12-07 | 2018-06-12 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of adjustable energy supply startup control circuit of voltage threshold |
| CN112583246A (en) * | 2020-12-17 | 2021-03-30 | 英麦科（厦门）微电子科技有限公司 | Chip enabling circuit |
| CN112583246B (en) * | 2020-12-17 | 2024-05-10 | 拓尔微电子股份有限公司 | Chip enabling circuit |
| CN113054835A (en) * | 2021-03-05 | 2021-06-29 | 山东英信计算机技术有限公司 | Delay starting method, system and related device of circuit module |
| CN113741671A (en) * | 2021-10-13 | 2021-12-03 | 瑞芯微电子股份有限公司 | Power supply power-on control method, system, storage medium and device |
| CN114123736A (en) * | 2021-10-29 | 2022-03-01 | 广东汇芯半导体有限公司 | Semiconductor circuit and application device thereof |
| CN114123736B (en) * | 2021-10-29 | 2023-11-24 | 广东汇芯半导体有限公司 | Semiconductor circuit and application device thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20131225 Termination date: 20160626 |
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| CF01 | Termination of patent right due to non-payment of annual fee |