CN103019132B - Chip and method for realizing low-power-consumption mode - Google Patents
Chip and method for realizing low-power-consumption mode Download PDFInfo
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- CN103019132B CN103019132B CN201210479816.8A CN201210479816A CN103019132B CN 103019132 B CN103019132 B CN 103019132B CN 201210479816 A CN201210479816 A CN 201210479816A CN 103019132 B CN103019132 B CN 103019132B
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Abstract
The invention provides a chip for realizing a low-power-consumption mode, comprising a standard reference source circuit capable of outputting appointed electrical level and bias, a power supply voltage low-voltage detection circuit, a low-power-consumption logic control circuit, and a digital logic unit, wherein the power supply voltage low-voltage detection circuit is used for comparing sampled chip current and voltage with the appointed electrical level and outputting a marking signal; the low-power-consumption logic control circuit is used for correspondingly outputting a control signal according to the change of high and low electrical levels of the marking signal; and the digital logic unit receives a control signal of the high electrical level and the chip enters the low-power-consumption mode; under the control of a clock signal, the standard reference source circuit and the power supply voltage low-voltage detection circuit can sample the change of the voltage of a power supply of the chip at regular time; and when the chip is at the low-power-consumption mode, the digital logic unit receives a control signal of the lower electrical level, and the chip quits the low-power-consumption mode. The invention further provides a method for realizing the low-power-consumption mode so as to solve the problem that the time of delaying data keeping time when power is suddenly off and reduce the problem of the possibility of instantly increasing the chip current, caused by spurious triggering.
Description
Technical field
The invention belongs to chip field, particularly relate to a kind of chip and the method that realize low-power consumption mode.
Background technology
Chip requires that power supply could normal work in a voltage range determined usually.For battery VBAT application scenario, usually require that the supply voltage of chip is between 1.8V to 3.6V.When battery VBAT voltage is lower than 1.8V, although system cisco unity malfunction, but user often expects that the significant data being kept at internal RAM in chip operational process is not lost, can also continue to use the data be originally stored in internal RAM after again changing battery.Although the data being stored in internal RAM can be lost, as long as the supply voltage of chip still can keep the data of its inside higher than 0.7V, RAM during the complete power down of chip.In addition; when changing battery VBAT, chip power voltage can not have completely, in order to ensure change battery VBAT during this period of time in chip still have power supply; between outside power vd D and ground VSS, a usual meeting bulky capacitor C1 in parallel is to use as backup battery, as shown in Figure 1.
To be reduced to the time of 0.7V from 1.8V in order to extend cell voltage, this requires that chip consumes as far as possible little electric current during the period, battery applications chip internal structure schematic diagram general at present as shown in Figure 2, usually be made up of following components: supply voltage low-voltage testing circuit 1, for detecting supply voltage, after chip power voltage drops to specified level, namely chip sends reports to the police or performs reset operation; Fiducial reference source circuit 2, for providing biased accurately for supply voltage low-voltage testing circuit 1, makes low voltage reset circuit normally to work; Program storage 3, for the Nonvolatile memery unit of storage execute program, can be flash memories, also can be single program memory cells; Random access memory 4, for storage chip some important informations in operational process, random access memory 4 is volatile memory-elements, when the complete power down of chip, storage unit in random access memory 4 can be lost, when the incomplete power down of chip, random access memory 4 can keep the content in storer within the scope of certain voltage, and this voltage is usually at more than 0.7V; Digital logic unit 5, perform reset operation for controlling low voltage reset circuit to supply voltage low-voltage testing circuit 1 and fiducial reference source circuit 2, digital logic unit 5 comprises the unit such as low voltage reset circuit, central processor unit (CPU), timer, pulse producer.
In prior art, often provide multiple-working mode to control the working current of chip as shown in Figure 2, as standby mode, shutdown mode etc.Although these mode of operations can reduce chip is reduced to 0.7V working current interior during this period of time from 1.8V; but in actual applications; user does not often know that power supply when can power down suddenly; may power down in the normal mode of operation; also may under shutdown mode; therefore, the unexpected power down of power supply has certain uncertainty.When power supply power down in the normal mode of operation, now chip power consumption electric current is often comparatively large, has the power consumption electric current of hundred microampere orders or even milliampere level, and the electricity stored in the dump energy in battery VBAT or electric capacity C1 is given out light rapidly.When power supply is under shutdown mode during power down; power consumption electric current can be very little; the electricity that dump energy in battery VBAT or electric capacity C1 store can maintain significant period of time; but because shutdown mode is easily waken up by external key usually; if surprisingly meet these buttons when practical operation; chip is very fast is transferred to normal mode from shutdown mode, can consume a large amount of electric currents instantaneously, and the electricity stored in the dump energy in battery VBAT or electric capacity C1 can be made equally to give out light rapidly.Particularly in MCU (microprocessor) chip, the unexpected power down of power supply cause RAM data to occur probabilistic situation is particularly outstanding.
Therefore, need to propose a kind of method judging chip power voltage when power down, so that after making the power down of chip generation supply voltage, chip is switched to low power mode of operation at once, reduce the working current of chip, thus extend the failure retention time of internal RAM data, solve the problem causing internal RAM to keep data time short in some cases because power down time is uncertain in prior art, and how to effectively reduce the chip current caused because of false triggering and increase instantaneously, thus reduce the probability problem of RAM data hold time.
Summary of the invention
The object of the present invention is to provide a kind of chip and the method that realize low-power consumption mode, chip power voltage when power down can be judged, and then solve and cause internal RAM may not keep the problem of data because power down time is uncertain, and efficiently reduce the probability problem that chip current that false triggering causes increases instantaneously.
For solving the problem, a kind of chip realizing low-power consumption mode being provided, comprising:
Fiducial reference source circuit, described fiducial reference source circuit exports a specified level and is biased;
The supply voltage low-voltage testing circuit be connected with described fiducial reference source circuit, described supply voltage low-voltage testing circuit receives described specified level and biased and sampling A/D chip supply voltage, and described chip power voltage is compared with specified level, export a marking signal;
The low-power logic control circuit be connected with described supply voltage low-voltage testing circuit and fiducial reference source circuit respectively, described low-power logic control circuit exports a control signal according to described marking signal, and exports the enable bit of the enable bit of a fiducial reference source circuit and supply voltage low-voltage testing circuit to described fiducial reference source circuit and supply voltage low-voltage testing circuit respectively;
The digital logic unit be connected with described low-power logic control circuit, when described digital logic unit judges chip power voltage lower than specified level according to the described control signal received, the enable bit of output reference reference source circuit thus enable fiducial reference source circuit, the enable bit of output supply voltage low-voltage testing circuit thus enable supply voltage low-voltage testing circuit, chip enters low-power consumption mode, under the control of a clock signal, the change of supply voltage low-voltage testing circuit timing sampling chip power voltage; According to the described control signal received, described digital logic unit judges that chip power voltage is higher than specified level, chip exits low-power consumption mode.
Further, when the described chip current voltage sampled is higher than specified level, the marking signal that described supply voltage low-voltage testing circuit exports is high level; When the described chip current voltage sampled is less than specified level, the marking signal that described supply voltage low-voltage testing circuit exports is low level.
Further, when described marking signal is low level by high level saltus step, the control signal that described low-power logic control circuit exports is high level; When described marking signal be low transition is high level, the control signal that described low-power logic control circuit exports is low level.
Further, when the control signal that described digital logic unit receives is high level, chip enters low-power consumption mode; When chip is under described low-power consumption mode, when the control signal that described digital logic unit receives is low level, chip exits described low-power consumption mode.
Further, described low-power logic control circuit comprises:
State machine circuit, the marking signal that described state machine circuit receives is high level when jumping to low level, exports the described control signal of one first enable signal, a voltage sample state, one second enable signal and high level; When chip is under described low-power consumption mode, the marking signal that described state machine circuit receives is low transition when being high level, exports marking signal that one the 3rd enable signal of described DLC (digital logic circuit), one the 4th enable signal and described supply voltage low-voltage testing circuit export and the low level control signal that described low-power logic control circuit exports;
First selector, when the control signal that described first selector receives is high level, selecting to export described first enable signal is the enable bit of fiducial reference source circuit; When the control signal that described first selector receives is low level, selecting to export described 3rd enable signal is the enable bit of fiducial reference source circuit;
Second selector, when the control signal that described second selector receives is high level, selects output voltage sample states as reset signal to described digital logic unit; When the control signal that described second selector receives is low level, select to export described marking signal as reset signal to described digital logic unit;
Third selector, when the control signal that described third selector receives is high level, selects to export the enable bit that described second enable signal is supply voltage low-voltage testing circuit; When the control signal that described third selector receives is low level, select to export the enable bit that described 4th enable signal is supply voltage low-voltage testing circuit.
Further, realize in the chip of low-power consumption mode described above, also comprise the random access memory be connected with described digital logic unit respectively, when the control signal that described digital logic unit receives is high level, controls described random access memory by described digital logic unit and enter described low-power consumption mode; When the control signal that described digital logic unit receives is low level, controls described random access memory by described digital logic unit and exit described low-power consumption mode.
Further, described digital logic unit controls described random access memory duty by reset signal.
Further, realize in the chip of low-power consumption mode described above, also comprise the program storage be connected with described digital logic unit respectively, when the control signal that described digital logic unit receives is high level, controls described program storage by described digital logic unit and enter described low-power consumption mode; When the control signal that described digital logic unit receives is low level, controls described program storage by described digital logic unit and exit described low-power consumption mode.
Further, described digital logic unit controls described program storage duty by reset signal.
Further, realize in the chip of low-power consumption mode described above, also comprise the oscillator with low voltage and low power consumption be connected with described low-power logic control circuit and digital logic unit, described oscillator with low voltage and low power consumption is by described digital logic unit control work and export described clock signal by described low-power logic control circuit to fiducial reference source circuit and supply voltage low-voltage testing circuit.
Further, the external unit of described digital logic unit or described chip exports described clock signal.
Further, realize in the chip of low-power consumption mode described above, described chip is MCU chip.
According to another side of the present invention, the invention provides a kind of method realizing low-power consumption mode, comprising:
When the enable bit of low-power logic control circuit is not enable, described low-power logic control circuit exports a control signal, chip enters low-power consumption mode illegal state, and fiducial reference source circuit and supply voltage low-voltage testing circuit receive one the 3rd enable signal and one the 4th enable signal of digital logic unit output respectively;
When described 3rd enable signal and the 4th enable signal effective time, enable described low-power logic control circuit, enters low-power consumption mode enabled state to make chip;
The same specified level of a chip power voltage sampled by described supply voltage low-voltage testing circuit compares, and exports a marking signal;
Described low-power logic control circuit exports described control signal according to the described marking signal received;
Described digital logic unit judges when described chip power voltage is lower than specified level according to the described control signal received, the described enable bit of digital logic unit output reference reference source circuit thus the enable bit of enable fiducial reference source circuit and output supply voltage low-voltage testing circuit thus enable supply voltage low-voltage testing circuit, chip enters low-power consumption mode, described fiducial reference source circuit and supply voltage low-voltage testing circuit receive one first enable signal and one first enable signal of the output of described low-power logic control circuit respectively, under the control of a clock signal, the change of described supply voltage low-voltage testing circuit timing sampling chip power voltage, when described supply voltage low-voltage testing circuit detects that chip power voltage is higher than specified level, chip exits low-power consumption mode.
Further, when the described chip current voltage sampled is higher than specified level, the marking signal that described supply voltage low-voltage testing circuit exports is high level; When the described chip current voltage sampled is less than specified level, the marking signal that described supply voltage low-voltage testing circuit exports is low level.
Further, when described marking signal is low level by high level saltus step, the control signal that described low-power logic control circuit exports is high level; When described marking signal be low transition is high level, the control signal that described low-power logic control circuit exports is low level.
Further, when the control signal that described digital logic unit receives is high level, chip enters low-power consumption mode; When chip is under described low-power consumption mode, when the control signal that described digital logic unit receives is low level, chip exits described low-power consumption mode.
Further, described low-power logic control circuit comprises when state machine circuit, first selector, second selector and third selector,
The described marking signal that described state machine circuit receives is high level when jumping to low level, exports the control signal of a voltage sample state, described first enable signal, the second enable signal and high level; When chip is under described low-power consumption mode, the described marking signal that described state machine circuit receives is low transition when arriving high level, exports described 3rd enable signal, the 4th enable signal and marking signal and low level control signal;
When the described control signal that described first selector receives is high level, the first enable signal received is delivered to fiducial reference source circuit by described first selector; When the described control signal that described first selector receives is low level, the 3rd enable signal received is delivered to fiducial reference source circuit by described first selector;
When the described control signal that described second selector receives is high level, the voltage sample state received is delivered to described digital logic unit by described second selector; When the described control signal that described second selector receives is low level, the described marking signal received is delivered to described digital logic unit by described second selector;
When the described control signal that described third selector receives is high level, the second enable signal received is delivered to supply voltage low-voltage testing circuit by described third selector; When the described control signal that described third selector receives is low level, the 4th enable signal received is delivered to supply voltage low-voltage testing circuit by described third selector.
Further, realize in the method for low-power consumption mode described above, when also to comprise control signal that described digital logic unit receives be high level, described digital logic unit controls a random access memory by described voltage sample state and enters described low-power consumption mode; When the control signal that described digital logic unit receives is low level, described digital logic unit controls described random access memory by described marking signal and exits described low-power consumption mode.
Further, realize in the method for low-power consumption mode described above, when also to comprise control signal that described digital logic unit receives be high level, described digital logic unit controls a program storage by described voltage sample state and enters described low-power consumption mode; When the control signal that described digital logic unit receives is low level, described digital logic unit controls described program storage by described marking signal and exits described low-power consumption mode.
Further, realize in the method for low-power consumption mode described above, also comprise described digital logic unit and control an oscillator with low voltage and low power consumption job, and make described oscillator with low voltage and low power consumption export described clock signal by described low-power logic control circuit to described fiducial reference source circuit and supply voltage low-voltage testing circuit.
Further, the external unit of described digital logic unit or described chip exports described clock signal.
Compared with prior art, the present invention passes through at supply voltage low pressure sample circuit, increases by a low-power logic control circuit between fiducial reference source circuit and digital logic unit, realize the chip of a low-power consumption mode, when the chip of described low-power consumption mode enters a low-power consumption mode, under the control of a clock signal, the change of described low-power logic control circuit enable supply voltage low pressure sample circuit and fiducial reference source circuit timing sampling chip power voltage, to reduce the action current of chip.Therefore, when chip is in normal mode of operation, during unexpected generation chip power voltage power down, chip works under being switched to low-power consumption mode at once, extend the data failure retention time of internal RAM, solve in prior art the problem causing because power down time is uncertain RAM may not keep data in some cases.In addition, because the chip power voltage of described low-power consumption mode in sampling rises to and just can wake up, efficiently reduce the probability that false triggering causes chip current to increase instantaneously, enhance the reliability of system.
In addition, when working under chip enters low-power consumption mode, can by the described digital logic unit of configuration, to control Digital Logic and the correlation module state of described digital logic unit, as controlled the duty of connected program storage and random access memory, described program storage and random access memory are resetted, to reduce the issuable leakage current of chip further.
Accompanying drawing explanation
Fig. 1 is the schematic diagram keeping chip internal RAM data external capacitor in prior art;
Fig. 2 is the structural representation of battery applications chip internal in prior art;
Fig. 3 is the structural representation of battery applications chip internal in the embodiment of the present invention;
Fig. 4 is the structural representation of low-power logic control circuit inside in the embodiment of the present invention;
Fig. 5 is the workflow schematic diagram of the low-power logic control circuit realized in the embodiment of the present invention in the method for low-power consumption mode;
Fig. 6 is the signal waveform schematic diagram of the low-power logic control circuit timing detection chip supply voltage in Fig. 5.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth a lot of detail in the following description so that fully understand the present invention.But the present invention can be much different from alternate manner described here to implement, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention, therefore the present invention is by the restriction of following public concrete enforcement.
As shown in Figure 3, in conjunction with 4, be described in detail to the invention provides a kind of chip realizing low-power consumption mode.The described chip realizing low-power consumption mode comprises: fiducial reference source circuit 100, supply voltage low pressure sample circuit 102, low-power logic control circuit 104 and digital logic unit 106.
Concrete, described fiducial reference source circuit 100 is for exporting a specified level and being biased.The output voltage of described fiducial reference source circuit 100 is very little with the change of temperature and chip power voltage VDD.
Concrete, described supply voltage low-voltage testing circuit 102 is connected with described fiducial reference source circuit 100, described supply voltage low-voltage testing circuit 102 is for receiving described specified level and biased and sampling A/D chip current/voltage VDD, and according to when the described chip current voltage VDD sampled is higher than specified level, clear flag signal EXT_DET, output identification signal EXT_DET is high level again; When the described chip current voltage VDD sampled is less than specified level, clear flag signal EXT_DET, output identification signal EXT_DET is low level again.In conventional chip, preferably, described supply voltage low pressure sample circuit 102 is low-voltage reset circuit or low-voltage sample circuit.Because the output voltage of described fiducial reference source circuit 100 is very little with the change of temperature and chip power voltage VDD, described fiducial reference source circuit 100 provides specified level and biased accurately to supply voltage low pressure sample circuit 102.
Concrete, described low-power logic control circuit 104 is connected with described fiducial reference source circuit 100 and supply voltage low pressure sample circuit 102, namely described supply voltage low-voltage testing circuit 102 enable bit VBGEN and fiducial reference source circuit 100 enable bit DETEN is provided by low-power logic control circuit 104, and described supply voltage low-voltage testing circuit 102 is to low-power logic control circuit 104 output identification signal.Described low-power logic control circuit 104 exports a control signal MODE for basis when described marking signal EXT_DET is low level by high level saltus step be high level; Exporting described control signal MODE when described marking signal EXT_DET be low transition is high level is low level.
Concrete, described digital logic unit 106 is connected with low-power logic control circuit, described digital logic unit 106 is for according to when receiving described control signal MODE and being high level, chip is made to enter low-power consumption mode, under the control of a clock signal clk, and control the change of fiducial reference source circuit 100 and supply voltage low pressure sample circuit 102 timing sampling chip power voltage VDD by controlling described low-power logic control circuit 104; When chip is under described low-power consumption mode, for according to when receiving described control signal MODE and being low level, chip is made to exit described low-power consumption mode.Described digital logic unit 106 is Digital Logic cores of chip, mainly comprise CPU (central processing unit) (CPU) module and other modules etc., other modules described comprise as modules such as timer, pulse producer, serial communication logic, input/output port control and clock generating.
Concrete, see Fig. 4, described low-power logic control circuit 102 comprises state machine circuit 202, first selector 204, second selector 206 and third selector 208, and its concrete analysis is as follows:
Described state machine circuit 202, for according to when the described marking signal EXT_DET received be high level jump to low level time, export one first enable signal INT_VBGEN, one second enable signal INT_DETEN, a voltage sample state I NT_DET and described control signal MODE is set to high level (namely low-power consumption mode is enable) output; When chip is under described low-power consumption mode, for according to when the described marking signal EXT_DET received be low transition is high level, one the 3rd enable signal EXT_VBGEN of described DLC (digital logic circuit) 106, one the 4th enable signal EXT_DETEN is exported and the marking signal EXT_DET of described supply voltage low-voltage testing circuit 103 is exported and the control signal MODE that described low-power logic control circuit exports is set to low level (namely low-power consumption mode is not enable) output.
Described first selector 204, for according to when the described control signal MODE received is high level, selects the described first enable signal INT_VBGEN of output to be that the enable bit of fiducial reference source circuit is to fiducial reference source circuit 100; When the described control signal MODE received is low level, selecting to export described 3rd enable signal EXT_VBGEN is that the enable bit of fiducial reference source circuit is to fiducial reference source circuit.In the present embodiment, for fitting into the enable work under low-power consumption mode and the enable work under not entering low-power consumption mode respectively, the enable bit VBGEN of described fiducial reference source circuit 100 is enable according to the described first enable signal INT_VBGEN received or the 3rd enable signal EXT_VBGEN respectively.
Described second selector 206, for according to when the described control signal MODE received is high level, selects output voltage sample states INT_DET as reset signal VDET to described digital logic unit 106; When the described control signal MODE received is low level, select to export described marking signal EXT_DET as reset signal VDET to described digital logic unit 106.In the present embodiment, for fitting into the enable work under low-power consumption mode and the enable work under not entering low-power consumption mode respectively, described digital logic unit to reset each digital logic module included by it and correlation module state according to the described voltage sample state I NT_DET that receives or marking signal EXT_DET respectively.
Described third selector 208, for according to when the described control signal MODE received is high level, selects the described second enable signal INT_DETEN of output to be that the enable bit of supply voltage low-voltage testing circuit is to supply voltage low-voltage testing circuit 102; When the described control signal MODE received is low level, selecting to export described 4th enable signal EXT_DETEN is that the enable bit of supply voltage low-voltage testing circuit is to supply voltage low-voltage testing circuit.In the present embodiment, for fitting into the enable work under low-power consumption mode and the enable work under not entering low-power consumption mode respectively, the enable bit DETEN of described supply voltage low-voltage testing circuit 102 is enable according to the described second enable signal INT_DETEN received or the 4th enable signal EXT_DETEN respectively.
In addition, in the chip of described low-power consumption mode, the program storage 108 be connected with described digital logic unit 106 is also comprised.Wherein, the program code that described program storage 108 runs for storage chip, and can be electricallyerasable ROM (EEROM) (EEPROM), single programmable memory (OTP) or flash memory (FLASH).When to receive described control signal MODE be high level to described digital logic unit 106, control described program storage 108 by described digital logic unit 106 and enter described low-power consumption mode; When to receive described control signal MODE be low level to described digital logic unit 106, control described program storage 108 by described digital logic unit 106 and exit described low-power consumption mode.Further, described digital logic unit 106 controls described program storage 108 duty by reset signal VDET.
In addition, in the chip of described low-power consumption mode, the random access memory 110 be connected with described digital logic unit 106 can also be comprised.Wherein, the significant data result produced when described random access memory 110 is run for storage chip or the duty of chip.When to receive described control signal MODE be high level to described digital logic unit 106, control described random access memory 110 by described digital logic unit 106 and enter described low-power consumption mode; When to receive described control signal MODE be low level to described digital logic unit 106, control described random access memory 110 by described digital logic unit 106 and exit described low-power consumption mode.Further, described digital logic unit 106 controls described random access memory 110 duty by reset signal VDET.
In addition, in the chip of described low-power consumption mode, the program storage 108 and random access memory 110 that are connected with described digital logic unit 106 respectively is also comprised.Wherein, the program code that described program storage 108 runs for storage chip, and can be electricallyerasable ROM (EEROM) (EEPROM), single programmable memory (OTP) or flash memory (FLASH); The significant data result produced when described random access memory 110 is run for storage chip or the duty of chip.When to receive described control signal MODE be high level to described digital logic unit 106, control described program storage 108 by described digital logic unit 106 and random access memory 110 enters described low-power consumption mode; When to receive described control signal MODE be low level to described digital logic unit 106, control described program storage 108 by described digital logic unit 106 and random access memory 110 exits described low-power consumption mode.Further, described digital logic unit 106 controls described program storage 108 and random access memory 110 duty by reset signal VDET.
Further, chip enters low-power consumption mode, described clock signal is exported to described low-power logic control circuit 104 by described digital logic unit or is provided to described low-power logic control circuit 104 by described chip exterior, described clock signal clk is exported to described supply voltage low-voltage testing circuit 102 by described low-power logic control circuit 104, described supply voltage low-voltage testing circuit 102 under the control of described clock signal clk, the change of timing sampling chip power voltage.Or described clock signal clk also can be provided by an oscillator with low voltage and low power consumption 112.Described oscillator with low voltage and low power consumption 112 is connected with described low-power logic control circuit 104 and digital logic unit 106 respectively, when to receive described control signal MODE be high level to described digital logic unit 106, provide Clock enable enable signal CLKEN enable to oscillator with low voltage and low power consumption 112.Described oscillator with low voltage and low power consumption 112 is the integrated CMOS oscillatory circuits of chip internal, when after enable described oscillator with low voltage and low power consumption 112, for providing clock signal clk to described low-power logic control circuit 104, and in conjunction with described first enable signal INT_VBGEN and the second enable signal INT_DETEN can fiducial reference source circuit 100 described in time opening and supply voltage low-voltage testing circuit 102 timing logic.In the present embodiment, by described state machine circuit 202 receive clock signal CLK; Described oscillator with low voltage and low power consumption 112 also can in the chip exterior of described low-power consumption mode, and the oscillation frequency of described oscillator with low voltage and low power consumption 112 is about 20KHZ (KHz), and static current of lcd is less than 1 microampere.After the chip of low-power consumption mode enters low-power consumption mode, described oscillator with low voltage and low power consumption 112 can work, till exiting low-power consumption mode always.
In the present embodiment, the described chip realizing low-power consumption mode is MCU chip.
Described low-power logic control circuit 104 enters low-power consumption mode for the chip controlling low-power consumption mode according to the low and high level change of described marking signal EXT_DET and exits low-power consumption mode, described low-power logic control circuit 104 has inner enable bit or disable bit, those of ordinary skill in the art it should be understood that described enable bit or disable bit realize by application configuration internal register.And described digital logic unit 106 controls Digital Logic and the correlation module state of described digital logic unit 106 according to the described control signal MODE received or reset signal VDET, as the duty of program storage 108 as described in controlling and random access memory 110; As forbid clock generating module make whole as described in digital logic unit 106 all no longer action, to reduce the dynamic current of chip; Be the leakage problem etc. that input channel and output channel close to reduce may cause because of input signal floating completely as configured input/output port control module, that is: in the present embodiment, after the chip of low-power consumption mode enters low-power consumption mode, except described low-power logic control circuit 104 works always, and outside described fiducial reference source circuit 100 and supply voltage low-voltage testing circuit 102 time opening, the input/output port control module configuring described digital logic unit 106 be input and output not enabled state to reduce the issuable leakage current of chip.
See Fig. 3, composition graphs 5 and Fig. 6, carry out labor to a kind of method realizing low-power consumption mode provided by the invention.The described method realizing low-power consumption mode comprises:
As shown in Figure 3, provide the chip that realizes low-power consumption mode, easy in order to describe, the described chip realizing low-power consumption mode is called for short chip.Refer to Fig. 5, when the inside enable bit of low-power logic control circuit 104 is not enable, the control signal MODE that described low-power logic control circuit 104 exports is set to low level, and described chip is in low-power consumption mode illegal state 301, and described chip can not enter low-power consumption mode.The described control signal MODE that digital logic unit 106 receives is after low level, and described digital logic unit 106 exports one the 3rd enable signal EXT_VBGEN to the enable bit DETEN of supply voltage low-voltage testing circuit 102 and exports one the 4th enable signal EXT_DETEN to the enable bit VBGEN of fiducial reference source circuit 100.
Export as high level when described digital logic unit 106 configures described 3rd enable signal EXT_VBGEN and the 4th enable signal EXT_DETEN, simultaneously during enable described low-power logic control circuit 102, in the above-described state, described supply voltage low-voltage testing circuit 102 incites somebody to action sampling A/D chip supply voltage VDD always, and described chip enters low-power consumption mode enabled state 302.When described supply voltage low-voltage testing circuit 102 samples chip power voltage VDD lower than specified level, described control signal MODE is set to high level, when described supply voltage low-voltage testing circuit 102 does not sample chip power voltage VDD lower than specified level, described control signal MODE remains low level always.As described in low-power logic control circuit 102 export as described in control signal MODE be high level time, described chip will enter low-power consumption mode, under described low-power consumption mode, described fiducial reference source circuit 100 provides specified level to supply voltage low-voltage testing circuit 102 and is biased, and the change of described supply voltage low-voltage testing circuit 102 timing sampling chip power voltage VDD.
Described low-power consumption mode enabled state 302 times, the change of described 3rd enable signal EXT_VBGEN and the 4th enable signal EXT_DETEN enable described fiducial reference source circuit 100 and supply voltage low-voltage testing circuit 102 chip monitoring supply voltage VDD always respectively.According to chip power voltage VDD result compared with described given voltage that described supply voltage low-voltage testing circuit 102 is sampled, judge that the marking signal EXT_DET that described supply voltage low-voltage testing circuit 102 exports is high level or low level, that is: if the described chip power voltage VDD that samples of described supply voltage low-voltage testing circuit 102 is from when dropping to lower than specified level higher than specified level, described supply voltage low-voltage testing circuit 102 output identification signal is low level; If the described chip power voltage VDD that described supply voltage low-voltage testing circuit 102 samples is from when rising to higher than specified level lower than specified level, described supply voltage low-voltage testing circuit 102 output identification signal is high level.
And, judge whether the described chip realizing low-power consumption mode enters described low-power consumption mode according to the change 303 of the low and high level of described marking signal EXT_DET, that is: if the marking signal EXT_DET that described supply voltage low-voltage testing circuit 102 exports maintains high level always, described chip rests on described low-power consumption mode enabled state 302 times all the time; When described low-power logic control circuit 104 detects that described marking signal EXT_DET jumps to low level (i.e. EXT_DET=1 ' b0) by high level, the control signal MODE that described digital logic unit 106 exports according to described low-power logic control circuit 104 is high level, makes described chip enter described low-power consumption mode 304; In described low-power consumption mode 304, when described low-power logic control circuit 104 detect described marking signal MODE for by low transition to high level (i.e. EXT_DET=1 ' b1) time, the control signal MODE that described digital logic unit 106 exports according to described low-power logic control circuit 104 is low level, makes described chip exit described low-power consumption mode.
Concrete, under the control of a clock signal clk, state machine circuit 202 in described low-power logic control circuit 102, according to the low and high level change 303 of described marking signal EXT_DET, controls the enable bit VBGEN of described the fiducial reference source circuit 100 and enable bit DETEN of supply voltage low-voltage testing circuit 102 to realize timing sampling chip power voltage VDD; According to the low and high level change 303 of described marking signal EXT_DET, described low power consumption control logical one 04 exports corresponding control signal MODE, according to the height of described control signal MODE, the first selector 204 in described low power consumption control logical one 02 selects the first enable signal INT_VBGEN (the enable bit VBGEN of the fiducial reference source circuit 100 after namely entering low-power consumption mode) or the 3rd enable signal EXT_VBGEN (the fiducial reference source circuit 100 enable bit VBGEN before namely entering low-power consumption mode); Second selector 206 in described low power consumption control logical one 02 selects voltage sample state I NT_DET (reset signal after namely entering low-power consumption mode) or marking signal EXT_DET, and (reset signal before namely entering low-power consumption mode is as reset signal VDET; Third selector 208 in described low power consumption control logical one 02 selects the second enable signal INT_DETEN (the enable bit DETEN of the supply voltage low-voltage testing circuit 102 after namely entering low-power consumption mode) or the 4th enable signal EXT_DETEN (the enable bit DETEN of the supply voltage low-voltage testing circuit 102 before namely entering low-power consumption mode).
In this example, that is, when described state machine circuit 202 detects that described marking signal EXT_DET jumps to low level (i.e. EXT_DET=1 ' b0) by high level, described state machine circuit 202 exports the control signal of high level, then enter low-power consumption mode, now, described first selector, second selector and third selector are under described control signal MODE is the control of high level, the the first enable signal INT_VBGEN respectively described state machine circuit 202 produced, voltage sample state I NT_DET, and second enable signal INT_DETEN select export.Enable enter low-power consumption mode after, if when described state machine circuit 202 detects described marking signal EXT_DET from low transition to high level, the control signal of described state machine circuit 202 output low level, then enablely exit low-power consumption mode, then described first selector, second selector and third selector are under described control signal MODE is low level control, respectively by the 3rd enable signal EXT_VBGEN that described digital logic unit 106 exports by described state machine circuit 202, marking signal EXT_DET, and the 4th enable signal EXT_DETEN select export.
In the present embodiment, described digital logic unit 106 program code read from a program storage 114 carries out program operation, the described method realizing low-power consumption mode also comprises: when the described control signal MODE that described digital logic unit 106 receives is high level, and described digital logic unit 106 controls described program storage 108 by described voltage sample state I NT_DET and enters described low-power consumption mode; When the described control signal MODE that receives of described digital logic unit 106 be low level time, described digital logic unit 106 controls described program storage 108 by described marking signal EXT_DET and exits described low-power consumption mode.
In the present embodiment, described digital logic unit 106 can also operate to a random access memory 116 significant data preserved in the course of work, the described method realizing low-power consumption mode can also comprise: when the described control signal MODE that described digital logic unit 106 receives is high level, and described digital logic unit 106 controls described random access memory 110 by described voltage sample state I NT_DET and enters described low-power consumption mode; When the described control signal MODE that receives of described digital logic unit 106 be low level time, described digital logic unit 106 controls described random access memory 110 by described marking signal EXT_DET and exits described low-power consumption mode.
In the present embodiment, described realization also comprises in the method for low-power consumption mode: export described clock signal clk by described digital logic unit 106 to described low-power logic control circuit, or provides described clock signal clk by described chip exterior to described low-power logic control circuit.Or, describedly realize in the method for low-power consumption mode, by the enable oscillator with low voltage and low power consumption 112 of described digital logic unit 106 to make described oscillator with low voltage and low power consumption 112 to low-power logic control circuit clock signal CLK.Specifically, refer to Fig. 6, described oscillator with low voltage and low power consumption 112 inside is arranged, described oscillator with low voltage and low power consumption can be made sampling should be carried out in 128 clock period described marking signal EXT_DET, within the sampling time, as when the 124th clock period, enable fiducial reference source circuit (namely the enable bit VBGEN of fiducial reference source circuit 100 is high level), when the 126th clock period, enable supply voltage low-voltage testing circuit (namely the enable bit DETEN of supply voltage low-voltage testing circuit 102 is high level), now, described chip enters low-power consumption mode enabled state 302, to sample when the 127th clock period the result of described marking signal EXT_DET, if the marking signal EXT_DET that supply voltage low-voltage testing circuit 102 exports is high level, represent that chip power voltage VDD is higher than specified level, then described chip exits low power mode of operation and reenters low-power consumption mode enabled state 302, if the marking signal EXT_DET that supply voltage low-voltage testing circuit exports is low level, represent that chip power voltage VDD is still lower than specified level, then described chip still remains on low-power consumption mode 304 times, 128th clock period removes the enable bit VBGEN of the fiducial reference source circuit 100 and enable bit DETEN (only having 4 clock period enable supply voltage low-voltage testing circuits and fiducial reference source circuit) of supply voltage low-voltage testing circuit 102.And when described chip is in low-power consumption mode illegal state 301, described supply voltage low-voltage testing circuit 102 real-time sampling chip power voltage VDD.
Described low-power consumption mode 304 times, described chip works under entering low-power consumption mode, by described control signal MODE to each Digital Logic in described DLC (digital logic circuit) 106 and correlation module state, as the duty of program storage 108 as described in controlling and random access memory 110; As forbid clock generating module make whole as described in digital logic unit 106 all no longer action, to reduce the dynamic current of described chip; Be that input channel and output channel close to reduce the leakage problem etc. that may cause because of input signal floating completely as configured input/output port control module, that is: by the described oscillator with low voltage and low power consumption 112 enable described fiducial reference source circuit 100 of timing and supply voltage low-voltage testing circuit 102 to reduce the average power consumption of system.This is because for total quiescent current of the described fiducial reference source circuit 100 under described low-power consumption mode illegal state 301 and supply voltage low-voltage testing circuit 102, as as described in fiducial reference source circuit 100 work time current sinking 16 microamperes, current sinking 32 microamperes when described supply voltage low-voltage testing circuit 102 works, when then working, described total quiescent current is 48 microamperes, and chip of the present invention is within 128 clock period, described fiducial reference source circuit 100 only has 4 clock period enable, described supply voltage low-voltage testing circuit 102 only has 2 clock period enable, its long average current is 1 microampere (32/128*2+16/128*4), greatly reduce system power dissipation.
Compared with prior art, the present invention passes through at supply voltage low pressure sample circuit, increases by a low-power logic control circuit between fiducial reference source circuit and digital logic unit, realize the chip of a low-power consumption mode, when the chip of described low-power consumption mode enters a low-power consumption mode, under the control of a clock signal clk, the change of described low-power logic control circuit enable supply voltage low pressure sample circuit and fiducial reference source circuit timing sampling chip power voltage, to reduce the action current of chip.Therefore, when chip is in normal mode of operation, during unexpected generation chip power voltage power down, chip works under being switched to low-power consumption mode at once, extend the data failure retention time of internal RAM, solve in prior art the problem causing because power down time is uncertain RAM may not keep data in some cases.In addition, because the chip power voltage of described low-power consumption mode in sampling rises to and just can wake up, efficiently reduce the probability that false triggering causes chip current to increase instantaneously, enhance the reliability of system.
In addition, when working under chip enters low-power consumption mode, can by the described digital logic unit of configuration, to control Digital Logic and the correlation module state of described digital logic unit, as controlled the duty of connected program storage and random access memory, described program storage and random access memory are resetted, to reduce the issuable leakage current of chip further.
Although the present invention with preferred embodiment openly as above; but it is not for limiting claim; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible variation and amendment, the scope that therefore protection scope of the present invention should define with the claims in the present invention is as the criterion.
Claims (21)
1. realize a chip for low-power consumption mode, comprising:
Fiducial reference source circuit, described fiducial reference source circuit exports a specified level and is biased;
The supply voltage low-voltage testing circuit be connected with described fiducial reference source circuit, described supply voltage low-voltage testing circuit receives described specified level and biased and sampling A/D chip supply voltage, and described chip power voltage is compared with specified level, export a marking signal;
The low-power logic control circuit be connected with described supply voltage low-voltage testing circuit and fiducial reference source circuit respectively, described low-power logic control circuit exports a control signal according to described marking signal, and exports the enable bit of the enable bit of a fiducial reference source circuit and supply voltage low-voltage testing circuit to described fiducial reference source circuit and supply voltage low-voltage testing circuit respectively;
The digital logic unit be connected with described low-power logic control circuit, when described digital logic unit judges chip power voltage lower than specified level according to the described control signal received, the enable bit of output reference reference source circuit thus enable fiducial reference source circuit, the enable bit of output supply voltage low-voltage testing circuit thus enable supply voltage low-voltage testing circuit, chip enters low-power consumption mode, under the control of a clock signal, the change of supply voltage low-voltage testing circuit timing sampling chip power voltage; According to the described control signal received, described digital logic unit judges that chip power voltage is higher than specified level, chip exits low-power consumption mode.
2. realize the chip of low-power consumption mode as claimed in claim 1, it is characterized in that, when the described chip current voltage sampled is higher than specified level, the marking signal that described supply voltage low-voltage testing circuit exports is high level; When the described chip current voltage sampled is less than specified level, the marking signal that described supply voltage low-voltage testing circuit exports is low level.
3. realize the chip of low-power consumption mode as claimed in claim 2, it is characterized in that, when described marking signal is low level by high level saltus step, the control signal that described low-power logic control circuit exports is high level; When described marking signal be low transition is high level, the control signal that described low-power logic control circuit exports is low level.
4. realize the chip of low-power consumption mode as claimed in claim 3, it is characterized in that, when the control signal that described digital logic unit receives is high level, chip enters low-power consumption mode; When chip is under described low-power consumption mode, when the control signal that described digital logic unit receives is low level, chip exits described low-power consumption mode.
5. realize the chip of low-power consumption mode as claimed in claim 3, it is characterized in that, described low-power logic control circuit comprises:
State machine circuit, the marking signal that described state machine circuit receives is high level when jumping to low level, exports the described control signal of one first enable signal, a voltage sample state, one second enable signal and high level; When chip is under described low-power consumption mode, the marking signal that described state machine circuit receives is low transition when being high level, exports marking signal that one the 3rd enable signal of described DLC (digital logic circuit), one the 4th enable signal and described supply voltage low-voltage testing circuit export and the low level control signal that described low-power logic control circuit exports;
First selector, when the control signal that described first selector receives is high level, selecting to export described first enable signal is the enable bit of fiducial reference source circuit; When the control signal that described first selector receives is low level, selecting to export described 3rd enable signal is the enable bit of fiducial reference source circuit;
Second selector, when the control signal that described second selector receives is high level, selects output voltage sample states as reset signal to described digital logic unit; When the control signal that described second selector receives is low level, select to export described marking signal as reset signal to described digital logic unit;
Third selector, when the control signal that described third selector receives is high level, selects to export the enable bit that described second enable signal is supply voltage low-voltage testing circuit; When the control signal that described third selector receives is low level, select to export the enable bit that described 4th enable signal is supply voltage low-voltage testing circuit.
6. realize the chip of low-power consumption mode as claimed in claim 3, it is characterized in that, also comprise the random access memory be connected with described digital logic unit respectively, when the control signal that described digital logic unit receives is high level, controls described random access memory by described digital logic unit and enter described low-power consumption mode; When the control signal that described digital logic unit receives is low level, controls described random access memory by described digital logic unit and exit described low-power consumption mode.
7. realize the chip of low-power consumption mode as claimed in claim 6, it is characterized in that, described digital logic unit controls described random access memory duty by reset signal.
8. realize the chip of low-power consumption mode as claimed in claim 3, it is characterized in that, also comprise the program storage be connected with described digital logic unit respectively, when the control signal that described digital logic unit receives is high level, controls described program storage by described digital logic unit and enter described low-power consumption mode; When the control signal that described digital logic unit receives is low level, controls described program storage by described digital logic unit and exit described low-power consumption mode.
9. realize the chip of low-power consumption mode as claimed in claim 8, it is characterized in that, described digital logic unit controls described program storage duty by reset signal.
10. realize the chip of low-power consumption mode as claimed in claim 1, it is characterized in that, also comprise the oscillator with low voltage and low power consumption be connected with described low-power logic control circuit and digital logic unit, described oscillator with low voltage and low power consumption is by described digital logic unit control work and export described clock signal by described low-power logic control circuit to fiducial reference source circuit and supply voltage low-voltage testing circuit.
11. chips realizing low-power consumption mode as claimed in claim 1, it is characterized in that, the external unit of described digital logic unit or described chip exports described clock signal.
12., as the chip realizing low-power consumption mode in claim 1 to 11 as described in any one, is characterized in that, described chip is MCU chip.
13. 1 kinds of methods realizing low-power consumption mode, comprising:
When the enable bit of low-power logic control circuit is not enable, described low-power logic control circuit exports a control signal, chip enters low-power consumption mode illegal state, and fiducial reference source circuit and supply voltage low-voltage testing circuit receive one the 3rd enable signal and one the 4th enable signal of digital logic unit output respectively;
When described 3rd enable signal and the 4th enable signal effective time, enable described low-power logic control circuit, enters low-power consumption mode enabled state to make chip;
The same specified level of a chip power voltage sampled by described supply voltage low-voltage testing circuit compares, and exports a marking signal;
Described low-power logic control circuit exports described control signal according to the described marking signal received;
Described digital logic unit judges when described chip power voltage is lower than specified level according to the described control signal received, the described enable bit of digital logic unit output reference reference source circuit thus the enable bit of enable fiducial reference source circuit and output supply voltage low-voltage testing circuit thus enable supply voltage low-voltage testing circuit, chip enters low-power consumption mode, described fiducial reference source circuit and supply voltage low-voltage testing circuit receive one first enable signal and one first enable signal of the output of described low-power logic control circuit respectively, under the control of a clock signal, the change of described supply voltage low-voltage testing circuit timing sampling chip power voltage, when described supply voltage low-voltage testing circuit detects that chip power voltage is higher than specified level, chip exits low-power consumption mode.
14. methods realizing low-power consumption mode as claimed in claim 13, is characterized in that, when the described chip current voltage sampled is higher than specified level, the marking signal that described supply voltage low-voltage testing circuit exports is high level; When the described chip current voltage sampled is less than specified level, the marking signal that described supply voltage low-voltage testing circuit exports is low level.
15. methods realizing low-power consumption mode as claimed in claim 14, is characterized in that, when described marking signal is low level by high level saltus step, the control signal that described low-power logic control circuit exports is high level; When described marking signal be low transition is high level, the control signal that described low-power logic control circuit exports is low level.
16. methods realizing low-power consumption mode as claimed in claim 15, it is characterized in that, when the control signal that described digital logic unit receives is high level, chip enters low-power consumption mode; When chip is under described low-power consumption mode, what described digital logic unit received states control signal when being low level, and chip exits described low-power consumption mode.
17. methods realizing low-power consumption mode as claimed in claim 15, it is characterized in that, described low-power logic control circuit comprises when state machine circuit, first selector, second selector and third selector,
The described marking signal that described state machine circuit receives is high level when jumping to low level, exports the control signal of a voltage sample state, described first enable signal, the second enable signal and high level; When chip is under described low-power consumption mode, the described marking signal that described state machine circuit receives is low transition when arriving high level, exports described 3rd enable signal, the 4th enable signal and marking signal and low level control signal;
When the described control signal that described first selector receives is high level, the first enable signal received is delivered to fiducial reference source circuit by described first selector; When the described control signal that described first selector receives is low level, the 3rd enable signal received is delivered to fiducial reference source circuit by described first selector;
When the described control signal that described second selector receives is high level, the voltage sample state received is delivered to described digital logic unit by described second selector; When the described control signal that described second selector receives is low level, the described marking signal received is delivered to described digital logic unit by described second selector;
When the described control signal that described third selector receives is high level, the second enable signal received is delivered to supply voltage low-voltage testing circuit by described third selector; When the described control signal that described third selector receives is low level, the 4th enable signal received is delivered to supply voltage low-voltage testing circuit by described third selector.
18. methods realizing low-power consumption mode as claimed in claim 15, it is characterized in that, when also to comprise control signal that described digital logic unit receives be high level, described digital logic unit controls a random access memory by described voltage sample state and enters described low-power consumption mode; When the control signal that described digital logic unit receives is low level, described digital logic unit controls described random access memory by described marking signal and exits described low-power consumption mode.
19. methods realizing low-power consumption mode as claimed in claim 15, it is characterized in that, when also to comprise control signal that described digital logic unit receives be high level, described digital logic unit controls a program storage by described voltage sample state and enters described low-power consumption mode; When the control signal that described digital logic unit receives is low level, described digital logic unit controls described program storage by described marking signal and exits described low-power consumption mode.
20. methods realizing low-power consumption mode as claimed in claim 13, it is characterized in that, also comprise and control an oscillator with low voltage and low power consumption job by described digital logic unit, and make described oscillator with low voltage and low power consumption export described clock signal by described low-power logic control circuit to described fiducial reference source circuit and supply voltage low-voltage testing circuit.
21. methods realizing low-power consumption mode as claimed in claim 13, it is characterized in that, the external unit of described digital logic unit or described chip exports described clock signal.
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| CN103445726A (en) * | 2013-08-30 | 2013-12-18 | 郑玉杰 | High-efficiency low-power consumption electronic controller used for dust collector |
| CN104777760B (en) * | 2014-01-13 | 2017-12-19 | 上海华虹集成电路有限责任公司 | Super low-power consumption MCU safe starting method and circuit |
| CN105827327B (en) * | 2016-04-15 | 2018-06-15 | 深圳市极致兴通科技有限公司 | A kind of efficient method for handover control for realizing QSFP module low-power consumption modes |
| CN107066250A (en) * | 2017-01-05 | 2017-08-18 | 珠海格力电器股份有限公司 | Power control circuit, electric equipment and power consumption control method |
| CN108923779B (en) * | 2018-07-09 | 2020-08-11 | 威创集团股份有限公司 | Signal multiplexing circuit and method |
| CN112150976A (en) * | 2019-06-28 | 2020-12-29 | 格科微电子（上海）有限公司 | Power-down screen cleaning method for liquid crystal display screen |
| CN113258764B (en) * | 2021-06-22 | 2021-11-09 | 浙江大学 | High-voltage driving circuit and power module |
| CN113644935B (en) * | 2021-08-09 | 2024-04-12 | 群联电子股份有限公司 | Signal redrive device, data storage system and mode control method |
| CN114217661B (en) * | 2021-11-02 | 2023-07-04 | 深圳市创芯微微电子股份有限公司 | Ultra-low power consumption voltage reference circuit and electronic equipment |
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