CN114302305B - Power supply reset circuit, ASIC chip and microphone - Google Patents
Power supply reset circuit, ASIC chip and microphone Download PDFInfo
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Abstract
The invention discloses a power supply resetting circuit, an ASIC chip and a microphone, wherein the power supply resetting circuit comprises: the power supply input end is used for accessing power supply voltage; the detection end of the front-stage power supply detection circuit is connected with the power supply input end; the pre-stage power supply detection circuit is used for outputting a reset trigger signal when the power supply voltage is detected to be larger than a preset voltage threshold value and the maintenance time of the power supply voltage larger than the preset voltage threshold value is larger than or equal to the preset time; the controlled end of the rear-stage power supply reset circuit is connected with the output end of the front-stage power supply detection circuit, and the input end of the rear-stage power supply reset circuit is connected with the power supply input end; the post-stage power supply reset circuit is used for converting the accessed power supply voltage into a delay input voltage when receiving a reset trigger signal and outputting a power supply reset signal when the delay input voltage is greater than or equal to a preset critical voltage. The invention solves the problem of false triggering of the power reset circuit.
Description
Technical Field
The present invention relates to the field of electronic circuits, and in particular, to a power supply reset circuit, an ASIC chip, and a microphone.
Background
In a sensor microphone chip, a reset (reset) mechanism is usually added to the circuit, so that the designed electronic circuit can be restored to an initial state when needed. In particular, at the beginning of powering on (powering on) an electronic circuit, components (e.g., registers) in the circuit are in an uncertain state, and at this time, the circuit components need to be reset to set the components in the circuit to an initial state, however, the reset circuit is easily subjected to an interference signal, and thus false triggering is caused, so that setting errors of initial values of related modules are caused.
Disclosure of Invention
The invention mainly aims to provide a power supply reset circuit, an ASIC chip and a microphone, and aims to solve the problem of false triggering of the power supply reset circuit.
To achieve the above object, the present invention provides a power supply reset circuit including:
the power supply input end is used for accessing power supply voltage;
the detection end of the front-stage power supply detection circuit is connected with the power supply input end; the pre-stage power supply detection circuit is used for outputting a reset trigger signal when the power supply voltage which is connected is detected to be larger than a preset voltage threshold value and the maintenance time of the power supply voltage which is larger than the preset voltage threshold value is larger than or is preset;
the controlled end of the rear-stage power supply reset circuit is connected with the output end of the front-stage power supply detection circuit, and the input end of the rear-stage power supply reset circuit is connected with the power supply input end; the post-stage power supply reset circuit is used for converting the accessed power supply voltage into a delay input voltage when receiving the reset trigger signal, and outputting a power supply reset signal when the delay input voltage is greater than or equal to a preset critical voltage.
Optionally, the pre-stage power supply detection circuit is further configured to not output a reset trigger signal when it is detected that the power supply voltage is connected to the power supply circuit and is smaller than a preset voltage threshold, or when a maintenance time when the power supply voltage is larger than the preset voltage threshold is smaller than a preset time.
Optionally, the pre-stage power supply detection circuit includes a delay trigger circuit and a switch circuit, a detection end of the delay trigger circuit is a detection end of the pre-stage power supply detection circuit, an output end of the delay trigger circuit is connected with a controlled end of the switch circuit, and an output end of the switch circuit is an output end of the pre-stage power supply detection circuit.
Optionally, the delay trigger circuit includes a first switch tube, a first capacitor and a first trigger, an input end of the first switch tube is an input end of the delay trigger circuit, an output end of the first switch tube is interconnected with a first end of the first capacitor and an input end of the first trigger, a second end of the first capacitor is grounded, and an output end of the first trigger is an output end of the delay trigger circuit.
Optionally, the switching circuit includes a second switching tube, a controlled end of the second switching tube is a controlled end of the switching circuit, an input end of the second switching tube is grounded, and an output end of the second switching tube is an output end of the switching circuit.
Optionally, the post-stage power source reset circuit includes a third switch tube, a second capacitor and a second trigger, an input end of the third switch tube is an input end of the post-stage power source reset circuit, an output end of the third switch tube is interconnected with a first end of the second capacitor and an input end of the first trigger, a second end of the second capacitor is grounded, and an output end of the second trigger is used for outputting the power source reset signal.
Optionally, the post-stage power supply reset circuit further includes an inverter, an input end of the inverter is connected with an output end of the second flip-flop, and an output end of the inverter is used for outputting the power supply reset signal after inversion.
The invention also proposes an ASIC chip comprising a power reset circuit as described above.
Optionally, the ASIC chip further includes:
the input end of the bias voltage generating circuit is used for being connected with a power supply voltage, and the output end of the bias voltage generating circuit is connected with the power supply end of the MEMS sensor; the bias voltage generating circuit is used for generating bias voltage according to the accessed power supply voltage and outputting the bias voltage to the MEMS sensor;
the signal processing circuit is connected with the output end of the MEMS sensor; and the signal processing circuit is used for carrying out signal processing on the detection signal output by the MEMS sensor and outputting the detection signal.
The invention also provides a microphone, which comprises an MEMS sensor and the power supply resetting circuit;
or alternatively, an ASIC chip as described above.
According to the invention, through the pre-stage power supply detection circuit, when the power supply voltage is detected to be larger than the preset voltage threshold value and the maintenance time of the power supply voltage larger than the preset voltage threshold value is larger than or equal to the preset time, a reset trigger signal is output, and when the power supply voltage is detected to be smaller than the preset voltage threshold value or the maintenance time of the power supply voltage larger than the preset voltage threshold value is detected to be smaller than the preset time, the reset trigger signal is not output. And when the delay input voltage is larger than or equal to a preset critical voltage, outputting a power reset signal to a related module. The invention provides a Power reset circuit with a Pre-detection function for a sensor microphone chip, wherein a Pre-detection (Pre-Detect) circuit can Filter interference unstable signals such as Filter spurs (Glitch) when the chip starts to be powered ON (Power ON) by utilizing a Pre-reset trigger circuit, so that erroneous judgment of jitter interference of a reference point during Power ON can be eliminated, and a reset trigger signal is output after the Power is stable, so that a post-Power reset circuit is triggered to output a Power reset signal. The invention can eliminate the erroneous judgment of short-term unstable jitter interference caused by the Ground (group) signal during power-on by utilizing a twice detection mode, so that the product obtains the correct initial value setting. The invention is beneficial to increasing the Yield (Yield) of the product in Mass Production (Mass Production) so as to reduce the optimal design of the Production Cost (Cost).
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic circuit diagram of a power reset circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a power reset circuit applied to an ASIC chip;
FIG. 3 is a timing diagram of each node of the power reset circuit according to the present invention following a power voltage change;
fig. 4 is a schematic functional block diagram of a microphone according to an embodiment of the invention.
Reference numerals illustrate:
| reference numerals | Name of the name | Reference numerals | Name of the name |
| 10 | Front stage power supply detection circuit | PM1 | First switch tube |
| 11 | Delay trigger circuit | CAP1 | First capacitor |
| 12 | Switching circuit | ST1 | First trigger |
| 20 | Post-stage power supply reset circuit | NM1 | Second switch tube |
| 100 | Power supply reset circuit | PM2 | Third switch tube |
| 200 | Bias voltage generating circuit | CAP2 | Second capacitor |
| 300 | Signal processing circuit | ST2 | Second trigger |
| 210 | Charge pump circuit | U1 | MEMS sensor |
| 220 | Clock pulse generator | U2 | ASIC chip |
| 230 | Reference voltage generator | VDD | Power supply input terminal |
The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, if directional indications (such as up, down, left, right, front, and rear … …) are included in the embodiments of the present invention, the directional indications are merely used to explain the relative positional relationship, movement conditions, etc. between the components in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indications are correspondingly changed.
In addition, if there is a description of "first", "second", etc. in the embodiments of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.
The term "and/or" is herein merely an association relationship describing an associated object, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.
The invention provides a Power Reset circuit (POR-Power ON Reset) for use in an ASIC chip.
Based on modern smart phones, TWS smart headphones and smart home consumer markets are widely used, so the sensor microphone chip (MEMS ASIC-Micro Electro Mechanical System Application Specific Integrated Circuit) needs to be increased relatively greatly. The Sensor is packaged (bound) together with a Chip (Chip) inside the Sensor microphone, the Sensor is responsible for receiving sound (operational) and converting the sound into Weak Voltage (Voltage) signals, the Chip (ASIC) is responsible for impedance conversion (Impedance transfer) and converting the Weak (Weak) Voltage signals into Voltage signals with Driving force (Driving) to be output (if the Weak Voltage signals of the Sensor are subjected to non-impedance conversion processing, the signals are attenuated (Attenuation) by parasitic capacitance, loading of a rear-stage circuit and the like, and abnormal output is caused). Nowadays, the Quality (Quality) of intelligent products is improved, and the Performance of the chip is required to be more strict (Specification & Performance), so that the chip circuit is increased compared with the chip circuit by using the reciprocating Complexity (Complexity), for example, a Function Calibration (Calibration) circuit is used to make the high-voltage output by a Charge Pump (Charge Pump) more accurate for use by a sensor, the Charge Pump is required to provide a correct Clock operating Frequency (Frequency) by a Clock (Clock) generator, the modules use a Digital Register (Digital Register) component, and an Initial Setting (Initial Setting) of a Reset (Reset) is required before the circuit works, so that the Function (Function) and the Performance of the related module can work normally, for example, the power on of the chip is not Reset, the Clock Frequency Setting or the Calibration Code (Code) stored in the buffer in the Calibration circuit can be in a Random state (Random state) so that the Charge Pump output voltage is required to make the buffer store, and thus the whole sensor can not obtain the Bias voltage (Sensitivity) of the abnormal signal (Sensitivity); in addition to the initial reset required by the digital circuits, some Analog circuits also need to perform an initial reset when the chip starts (Start-up) power-up operation, such as Band-gap Reference Voltage Generator circuits, and if the power-up reset is not performed, the reference voltage may be output as 0V, and the Bias voltage cannot be normally provided. The Power Reset module (POR-Power ON Reset) is used for providing the detection Power ON and the initial Reset signal to the related module, when the detection Power ON is at the minimum required level (VD) for the circuit to work, the Power Reset signal VPOR is changed from the low level to the high level, and the related module circuit is relatively and initially set according to the voltage change of the VPOR and starts to work. When the conventional sensor microphone chip is powered up (Start-up), the POR module generates a reset signal, and when the detection power source is at the VD level, the power reset signal VPOR is changed from the low level to the high level. However, in Mass Production (Mass Production), probes (probes) for providing Ground (group) signals ON a Production line are all continuously powered up and kept at 0V, and when one group of objects to be tested (DUT-Device Under Test) is tested (Finish), the probes are directly moved to the next group of DUTs to continue testing, so as to reduce the testing time, reduce the repeated power-ON and power-OFF (Repeat) operation time of the probes, and reduce the continuous use (ON-OFF) of a Relay (Relay as a mechanical switch) for reducing component wear. However, in such a test mode, when the Ground (group) signal of the machine probe is extended out and is electrified, the Ground (group) signal is temporarily unstable due to factors such as parasitic capacitance of the equipment and poor contact of the probe at the moment of contacting the next group of products, and the POR module sends out the abnormal VPOR Reset (Reset) signal, so that the initial value setting of the relevant module is wrong, resulting in misjudgment of poor product yield.
In order to solve the above problems, the present invention provides a power reset circuit 100, which uses the power reset circuit 100 having a pre-detection function for power supply to provide a sensor microphone chip, and can eliminate erroneous judgment of short-term unstable jitter interference due to a Ground (Ground) signal during power-up by using a two-time detection method, so that a product can obtain a correct initial value setting. And the Yield (Yield) of the product in Mass Production (Mass Production) is increased, so that the optimal design of the Production Cost (Cost) is reduced. Referring to fig. 1 to 3, in an embodiment of the present invention, the power reset circuit 100 includes:
a power supply input end VDD for accessing a power supply voltage;
a pre-stage power supply detection circuit 10, the detection end of which is connected with the power supply input end VDD; the pre-stage power supply detection circuit 10 is configured to output a reset trigger signal when it is detected that the power supply voltage is greater than a preset voltage threshold, and a maintenance time when the power supply voltage is greater than the preset voltage threshold is greater than or equal to a preset time;
a post-stage power source reset circuit 20, wherein a controlled end of the post-stage power source reset circuit 20 is connected with an output end of the pre-stage power source detection circuit 10, and an input end of the post-stage power source reset circuit 20 is connected with the power source input end VDD; the post-stage power reset circuit 20 is configured to convert the power supply voltage into a delayed input voltage when the reset trigger signal is received, and output a power supply reset signal when the delayed input voltage is greater than or equal to a preset threshold voltage; and when the power supply voltage which is connected is detected to be smaller than a preset voltage threshold value or the maintenance time when the power supply voltage is larger than the preset voltage threshold value is detected to be smaller than the preset time, a reset trigger signal is not output.
It will be appreciated that at the beginning of power-up, the supply voltage slowly rises from low (0V) to high (VDD) to a plateau. In this embodiment, the front stage power supply detection circuit 10 is configured to determine whether to generate a reset trigger signal according to a high-low voltage value of a power supply voltage to which the power supply input terminal VDD is connected and a duration of the high voltage, that is, determine whether to trigger the operation of the rear stage power supply reset circuit 20, when the rear stage power supply reset circuit 20 is triggered to normally operate, the rear stage power supply reset circuit 20 may generate a high-level power supply reset signal, and when the rear stage power supply reset circuit 20 is triggered to not operate, the level of the output terminal of the rear stage power supply reset circuit 20 is low, that is, the power supply reset signal is not output. Of course, in other embodiments, the power reset signal may be low, and the level of the output terminal of the post power reset circuit 20 is high when the post power reset circuit 20 is not operating.
Specifically, as shown in fig. 3, fig. 3 is a timing diagram of each node in the power reset circuit following the power voltage variation. When the power supply voltage is just started to be powered Up (Start-Up), the detection terminal of the front stage power supply detection circuit 10 detects that the power supply voltage is smaller than the threshold voltage ST1, the front stage power supply detection circuit 10 does not generate a reset trigger signal, and the rear stage power supply reset circuit 20 does not receive the reset trigger signal and does not operate, so that a power supply reset signal is not generated. In the process of continuing power-up of the power supply, the Ground terminal group is disturbed to generate a spike a (Glitch-a) signal, so that when the power supply voltage detected by the detection terminal (node a) of the front stage power supply detection circuit 10 is raised more than the critical voltage ST1, the front stage power supply detection circuit 10 starts to generate a reset trigger signal from low to high, so that the voltage at the controlled terminal (node C) of the rear stage power supply reset circuit 20 is gradually raised from low voltage charge, but the voltage at the node C is still less than the critical voltage ST2 at which the rear stage power supply reset circuit 20 starts to operate, and therefore the power supply reset signal VPOR is still kept at low voltage. The power supply is continuously powered up, and since the disturbance signal is usually a discontinuous spike, its short spike a (Glitch-a) signal disappears, and the voltage recovery is smaller than the threshold voltage ST1 of the reset trigger signal, so that the voltage at the node C is pulled down again to a low voltage, and thus the power supply reset signal VPOR continues to be a low voltage. During the power-up process, the Ground group is continuously disturbed to generate a spike B (Glitch-B) signal, and the power reset signal VPOR is maintained at a low voltage as described in the second and third steps. When the power supply is powered up to the minimum required level (VD) at which the circuit can operate, when the microphone chip is tested, it may also indicate that the probe is completely contacted, after the short transient instability phenomenon of the Ground (group) signal is eliminated, the voltage of the node a is always greater than the critical voltage ST1, at this time, the front stage power supply detection circuit 10 outputs a reset trigger signal to the rear stage power supply reset circuit 20, so as to trigger the rear stage power supply reset circuit 20 to operate, that is, the node C is charged to be greater than the critical voltage at which the rear stage power supply reset circuit 20 starts to operate, that is, when the reset trigger signal is received, the rear stage power supply reset circuit 20 converts the power supply voltage which is connected into a delay input voltage, and outputs a power supply reset signal when the delay input voltage is greater than or equal to a preset critical voltage. In this process, the power reset signal VPOR is changed from low voltage to high voltage, so as to complete the determination and output of the correct reset signal, and thus the relevant module circuit can be provided for initial value setting.
According to the invention, through the pre-stage power supply detection circuit 10, when the power supply voltage is detected to be larger than a preset voltage threshold value and the maintenance time of the power supply voltage larger than the preset voltage threshold value is larger than or equal to the preset time, a reset trigger signal is output, and when the power supply voltage is detected to be smaller than the preset voltage threshold value or the maintenance time of the power supply voltage larger than the preset voltage threshold value is detected to be smaller than the preset time, the reset trigger signal is not output. The post-stage power reset circuit 20 converts the power voltage into a delayed input voltage when receiving the reset trigger signal, and outputs a power reset signal to the related module when the delayed input voltage is greater than or equal to a preset threshold voltage. The invention provides a Power reset circuit 100 with a Pre-detection function for a sensor microphone chip, wherein a Pre-detection (Pre-Detect) circuit can Filter interference unstable signals such as a Filter spike (Glitch) when the chip starts to be powered ON (Power ON) by utilizing a Pre-reset trigger circuit, so that erroneous judgment of reference point jitter interference during Power ON can be eliminated, and a reset trigger signal is output after the Power is stable, so that a post-Power reset circuit 20 is triggered to output a Power reset signal. The invention can eliminate the erroneous judgment of short-term unstable jitter interference caused by the Ground (group) signal during power-on by utilizing a twice detection mode, so that the product obtains the correct initial value setting. The invention is beneficial to increasing the Yield (Yield) of the product in Mass Production (Mass Production) so as to reduce the optimal design of the Production Cost (Cost).
Referring to fig. 1 to 3, in an embodiment, the pre-stage power source detection circuit 10 includes a delay trigger circuit 11 and a switch circuit 12, a detection end of the delay trigger circuit 11 is a detection end of the pre-stage power source detection circuit 10, an output end of the delay trigger circuit 11 is connected to a controlled end of the switch circuit 12, and an output end of the switch circuit 12 is connected to an output end of the pre-stage power source detection circuit 10.
In this embodiment, when the power supply (VDD) is just started to power Up (Start-Up), the voltage at the detection end (node a) of the delay trigger circuit 11 is smaller than the threshold voltage of ST1, the node B is high voltage and turns on the switch circuit 12, so that the voltage at the node C is pulled down (Pull-low) to be low, and the power reset signal VPOR is low. During the power-on process, the Ground group is disturbed to generate a spike A (Glitch-A) signal, which causes the voltage at node A to be raised upwards by more than the threshold voltage of ST1, so that node B becomes low voltage to turn off the switch circuit 12, and the power voltage starts to charge node C, so that the voltage at node C is gradually pulled up by the low voltage charge, but the voltage at node C is still less than the threshold voltage of the later power reset circuit 20, and thus the power reset signal VPOR is kept low. The power supply is continuously powered up, the short spike A (Glitch-A) signal disappears, the voltage of the node A is recovered to be smaller than the critical voltage of the pre-reset trigger circuit, the voltage of the node B is changed to be high, the switch circuit 12 is turned on again, the voltage of the node C is pulled down to be low again, and therefore the power reset signal VPOR is continuously low. During the power-up process, the Ground group is disturbed to generate a spike B (Glitch-B) signal, and the power reset signal VPOR is kept low. When the power-on reaches the minimum required level (VD) for the circuit to work, after the short transient instability of the Ground (Ground) signal is eliminated, the voltage of the node a is charged and remains greater than the critical voltage of ST1, the low voltage of the node B turns off the switch circuit 12, so that when the node C is charged to be greater than the critical voltage of the smitt trigger (ST 2) circuit, the change of the power reset signal VPOR is converted from the low voltage to the high voltage, and the determination and output of the correct reset signal are completed, thereby providing the relevant module circuit for initial value setting. The present invention provides a power reset circuit 100 with a pre-detection function for a power supply, which can eliminate erroneous judgment of short-term unstable jitter interference due to a Ground (group) signal during power-up by using a twice detection method, so that a product can obtain a correct initial value setting. And the Yield (Yield) of the product in Mass Production (Mass Production) is increased, so that the optimal design of the Production Cost (Cost) is reduced.
Referring to fig. 1 to 3, in an embodiment, the delay trigger circuit 11 includes a first switch tube PM1, a first capacitor CAP1, and a first trigger ST1, where an input end of the first switch tube PM1 is an input end of the delay trigger circuit 11, an output end of the first switch tube PM1 is interconnected with a first end of the first capacitor CAP1 and an input end of the first trigger ST1, a second end of the first capacitor CAP1 is grounded, and an output end of the first trigger ST1 is an output end of the delay trigger circuit 11.
In this embodiment, the first switch tube PM1 may be implemented by a PMOS tube, where the controlled end of the first switch tube PM1 is connected to the P-tube regulated voltage VBIASP as a current source, and provides an IP1 current to charge the first capacitor CAP1 to generate the voltage of the node a. When the power source starts to power up, the voltage of the contact a is pulled down by the first capacitor CAP1, and then starts to rise from small to large until the threshold voltage of the first trigger ST1 is raised. The first flip-flop ST1 is a smitt flip-flop, and the first flip-flop ST1 sets the switching circuit 12 according to the comparison (complex) between the voltage at the node a and the threshold voltage (Threshold Voltage) of the first flip-flop ST 1:
v (Node-a) < V (Threshold-ST 1) output signal V (Node-B) =high (High level), and switch circuit 12 is turned on, V (Node-a) > V (Threshold-ST 1) output signal V (Node-B) =low (Low level). The switching circuit 12 is closed; wherein Node-A is Node A, i.e. the input terminal of the first trigger ST1, threshold-ST1 is the Threshold voltage of the first trigger ST1, and Node-B is Node B, i.e. the output terminal of the first trigger ST 1.
Referring to fig. 1 to 3, in an embodiment, the switching circuit 12 includes a second switching tube NM1, a controlled end of the second switching tube NM1 is a controlled end of the switching circuit 12, an input end of the second switching tube NM1 is grounded, and an output end of the second switching tube NM1 is an output end of the switching circuit 12.
In this embodiment, the second switching tube NM1 may be implemented by an NMOS tube, where the second switching tube NM1 is controlled by the delay trigger circuit 11, and is turned on when receiving a high-level trigger signal, and when the second switching tube NM1 is turned on, the voltage at the input end of the post-stage power reset circuit 20 is pulled down, that is, clamped, and at this time, no matter what the power voltage value input by the power input end VDD is, the average power level at the output end of the post-stage power reset circuit 20 is low, that is, no power reset signal is output, or the power reset signal is low. When the second switching tube NM1 is turned off, the input terminal of the post-stage power reset circuit 20 is connected to the power voltage input by the power input terminal VDD, and the post-stage power reset circuit 20 may output no power reset signal or the power reset signal is at a low level according to the level of the output terminal.
Referring to fig. 1 to 3, in an embodiment, the post-stage power reset circuit 20 includes a third switch tube PM2, a second capacitor CAP2, and a second trigger ST2, wherein an input end of the third switch tube PM2 is an input end of the post-stage power reset circuit 20, an output end of the third switch tube PM2 is interconnected with a first end of the second capacitor CAP2 and an input end of the first trigger ST1, a second end of the second capacitor CAP2 is grounded, and an output end of the second trigger ST2 is used for outputting the power reset signal.
In this embodiment, the third switch tube PM2 may be implemented by a PMOS tube, where the controlled end of the third switch tube PM2 is connected to the P-tube regulated voltage VBIASP as a current source, the PM2 current source is implemented to provide the IP2 current to charge and not charge the second capacitor CAP2, and generate the node C voltage, the second trigger ST2 is a smitt trigger, and the second trigger ST2 sets the VPOR reset signal according to the comparison (Compare) between the node C voltage and the threshold voltage (Threshold Voltage) of the second trigger ST 2:
the current stage reset trigger circuit outputs a reset trigger signal of Low level, that is, the switching circuit 12 is turned ON (turnon), i.e., the second capacitor CAP2 of the later stage power source reset circuit 20 is not charged, the power source reset signal vpor=low (Low level);
when the switching circuit 12 is turned OFF (turnoff), the second capacitor CAP2 of the rear-stage power supply reset circuit 20 is charged, and the power supply reset signal vpor=low to High (change from Low level to High level). The post-stage power Reset circuit 20 of the present embodiment uses a current source circuit and a capacitor to form a stored Charge (Store Charge) device, when the chip is powered on, the current source starts to generate a current, and when the voltage of the equal node C exceeds the threshold voltage (Threshold Voltage) of the Schmitt Trigger circuit, the power Reset signal VPOR is changed from low voltage to high voltage, which indicates that the chip power has met the circuit specification, and the related module performs a Reset (Reset) operation when receiving the power Reset signal VPOR change Trigger (Trigger) to complete the initialization Setting (Initial Setting).
Specifically, when the power supply (VDD) is just started to be powered Up (Start-Up), the voltage at the detection end (node a) of the delay trigger circuit 11 is smaller than the threshold voltage of ST1, the node B is high voltage and turns on the switch circuit 12, the two ends of the second capacitor CAP2 are Short-circuited (Short) by the switch circuit 12, and the charge cannot be stored and charged, i.e. the voltage at the node C is pulled down (Pull-low) to be low voltage, so that the power reset signal VPOR is low voltage. In the power-on process, the Ground end group is disturbed to generate a spike a (Glitch-a) signal, so that the voltage of the node a is raised more than the critical voltage of ST1, and therefore the node B becomes low voltage to turn off the switch circuit 12, so that the two ends of the second capacitor CAP2 are opened (Open), the power voltage of the third switch tube PM2 starts to charge the second capacitor CAP2, and therefore the voltage of the node C is gradually raised from low voltage charging, but the voltage of the node C is still less than the critical voltage of the later power reset circuit 20, and therefore the power reset signal VPOR is kept low. The power supply is continuously powered up, the short spike A (Glitch-A) signal disappears, the voltage of the node A is recovered to be smaller than the critical voltage of the pre-reset trigger circuit, the voltage of the node B is changed to be high voltage, the switch circuit 12 is turned on again, the two ends of the second capacitor CAP2 are short-circuited again and cannot be charged, the voltage of the node C is pulled down to be low voltage again, and therefore the power reset signal VPOR is continuously low voltage. During the power-up process, the Ground group is disturbed to generate a spike B (Glitch-B) signal, and the power reset signal VPOR is kept low. When the power-on reaches the minimum required level (VD) for the circuit to work, after the short transient instability of the Ground (Ground) signal is eliminated, the voltage of the node a is charged and remains greater than the critical voltage of ST1, the low voltage of the node B turns off the switch circuit 12, so that the two ends of the second capacitor CAP2 are opened (Open), when the node C starts to be charged to be greater than the critical voltage of the smitt trigger (ST 2) circuit, the power reset signal VPOR is changed from the low voltage to the high voltage, and the determination and output of the correct reset signal are completed, so that the relevant module circuit can be provided for initial value setting. The present invention provides a power reset circuit 100 with a pre-detection function for a power supply, which can eliminate erroneous judgment of short-term unstable jitter interference due to a Ground (group) signal during power-up by using a twice detection method, so that a product can obtain a correct initial value setting. And the Yield (Yield) of the product in Mass Production (Mass Production) is increased, so that the optimal design of the Production Cost (Cost) is reduced.
According to the formula of Q=CxV=IxT, the current value and the capacitance of the current source are designed, the voltage charging speed of the node C can be controlled (for example, the charging time is required to be longer when the current source is designed to output small current to charge a large capacitance), and the problem that when the ground voltage of the sensor microphone chip power supply reset module is interfered to generate jitter, VPOR continuous Random (Random) output spike (Glitch) signals are easy to cause setting errors of related modules can be solved.
Referring to fig. 1 to 3, in an embodiment, the post-stage power reset circuit 20 further includes an inverter A1, an input terminal of the inverter A1 is connected to an output terminal of the second flip-flop ST2, and an output terminal of the inverter A1 is configured to output the power reset signal after inversion.
In this embodiment, when the pre-stage power reset circuit 100 outputs the reset trigger signal, the voltage at the input end of the schmitt trigger gradually rises under the charging action of the second capacitor CAP2, the level of the power reset signal VPOR also gradually rises along with the power voltage VDD, and when the voltage on the second capacitor CAP2 is charged to the first critical level, the second trigger ST2 outputs the low-level power reset signal according to the voltage at the input end (i.e. the voltage on the second capacitor CAP2C 3), and then the Inverter A1 (Inverter) converts the change of the power reset signal VPOR signal from the low voltage to the high voltage, so as to complete the determination and output of the correct reset signal, thereby providing the relevant module circuit for initial value setting.
The invention also proposes a ASIC (Application Specific Integrated Circuit) chip comprising a power reset circuit 100 as described above. The detailed structure of the power reset circuit 100 can refer to the above embodiments, and will not be described herein again; it can be understood that, since the power reset circuit 100 is used in the ASIC chip of the present invention, the embodiments of the ASIC chip of the present invention include all the technical solutions of all the embodiments of the power reset circuit 100, and the achieved technical effects are identical, and are not described herein again.
Referring to fig. 1 to 3, in an embodiment, the ASIC chip further includes:
the input end of the bias voltage generating circuit 200 is used for being connected with a power supply voltage, and the output end of the bias voltage generating circuit 200 is connected with the power supply end of the MEMS sensor; the bias voltage generating circuit 200 is configured to generate a bias voltage according to the accessed power supply voltage and output the bias voltage to the MEMS sensor;
the signal processing circuit 300 is connected with the output end of the MEMS sensor; the signal processing circuit 300 is configured to perform signal processing on a detection signal output by the MEMS sensor and output the signal.
In this embodiment, the bias voltage generating circuit 200 includes a Charge Pump (Charge Pump) 210, a Clock Generator (Clock Generator) 220, and a reference voltage Generator (voltage) 230, wherein the reference voltage Generator 230 is implemented by a bandgap reference voltage source, and the bandgap reference voltage source can generate voltage drops insensitive to temperature and voltage variations, and in this embodiment, generate two reference voltages and provide an initial voltage (standard voltage) to the Charge Pump circuit 210. The input terminal of the clock pulse generator 220 is connected to the control signal, and generates a clock signal according to the connected control signal. It will be appreciated that the control signal received by the clock generator 220 and thus the clock signal generated will be different depending on the requirements of the MEMS drive voltage. The charge pump circuit 210 boosts the power supply voltage according to the received reference voltage and clock signal to generate a voltage value with a corresponding magnitude and outputs the voltage value to the MEMS sensor U1, thereby providing a bias voltage required by the sensor. The clock generator 220 and the reference voltage generator 230 are respectively connected to the power reset circuit 100, and the power reset circuit 100 provides a power reset signal to the clock generator 220 and the reference voltage generator 230 when the power reset circuit is connected to the power voltage, so as to realize the initial setting of the clock generator 220 and the reference voltage generator 230 and start working. The signal processing circuit 300 is used for outputting weak voltage signals provided by the sensor after data calculation, amplification, analog-to-digital conversion and other processes. The signal processing circuit comprises an amplifying circuit (AMP) and a band gap reference source circuit (BGR BIAS). The bandgap reference voltage source is implemented, and the bandgap reference voltage source can generate a voltage drop insensitive to temperature and voltage changes, and in this embodiment, the bandgap reference voltage source circuit is used to provide an initial voltage to the amplifying circuit (AMP) so that the amplifying circuit can convert a Weak (Weak) voltage signal into a voltage signal output with a Driving force (Driving).
The invention also provides a microphone.
Referring to fig. 4, the microphone includes a MEMS sensor U1 and a power reset circuit 100 as described above;
alternatively, an ASIC chip U2 as described above is included;
the MEMS sensor U1 is connected to the ASIC chip U2.
The microphone includes a MEMS sensor and power supply reset circuit 100 as described above. The detailed structure of the power reset circuit 100 can refer to the above embodiments, and will not be described herein again; it can be understood that, since the power reset circuit 100 is used in the microphone of the present invention, the embodiments of the microphone of the present invention include all the technical solutions of all the embodiments of the power reset circuit 100, and the achieved technical effects are identical, and are not described herein again.
In this embodiment, when the MEMS sensor U1 receives external air pressure or receives other external forces according to the BIAS voltage (BIAS voltage) output by the ASIC chip U2, the variable capacitance value in the MEMS will change correspondingly, and after the variable capacitance value is finally converted into a voltage signal, the voltage signal enters the ASIC chip U2 through the pin VIN of the ASIC chip to perform air pressure data calculation, amplification, analog-to-digital conversion and other processes, and after the voltage signal is processed, the ASIC chip U2 can transmit the voltage signal to the main controller MCU of the electronic device through the I2C or SPI interface, and the MCU performs corresponding air pressure value display or other control according to the obtained data. The ASIC chip is also responsible for impedance conversion (Impedance transfer) to convert a Weak (Weak) voltage signal into a voltage signal output with a Driving force (Driving) (if the sensor Weak voltage signal is subjected to no impedance conversion processing, the signal is attenuated (attenuated) by parasitic capacitance, loading (Loading) and the like, and the output is abnormal).
The foregoing description is only of the optional embodiments of the present invention, and is not intended to limit the scope of the invention, and all the equivalent structural changes made by the description of the present invention and the accompanying drawings or direct/indirect application in other related technical fields are included in the scope of the invention under the inventive concept of the present invention.
Claims (7)
1. A power reset circuit, the power reset circuit comprising:
the power supply input end is used for accessing power supply voltage;
the detection end of the front-stage power supply detection circuit is connected with the power supply input end; the pre-stage power supply detection circuit is used for outputting a reset trigger signal when the power supply voltage which is connected is detected to be larger than a preset voltage threshold value and the maintenance time of the power supply voltage larger than the preset voltage threshold value is larger than or equal to preset time; the power supply voltage detection circuit is also used for detecting that the accessed power supply voltage is smaller than a preset voltage threshold value or the maintenance time of the power supply voltage larger than the preset voltage threshold value is smaller than a preset time, and not outputting a reset trigger signal;
the controlled end of the rear-stage power supply reset circuit is connected with the output end of the front-stage power supply detection circuit, and the input end of the rear-stage power supply reset circuit is connected with the power supply input end; the post-stage power supply reset circuit is used for converting the accessed power supply voltage into a delay input voltage when receiving the reset trigger signal, and outputting a power supply reset signal when the delay input voltage is greater than or equal to a preset critical voltage;
the front-stage power supply detection circuit comprises a delay trigger circuit and a switch circuit, wherein the detection end of the delay trigger circuit is the detection end of the front-stage power supply detection circuit, the output end of the delay trigger circuit is connected with the controlled end of the switch circuit, and the output end of the switch circuit is the output end of the front-stage power supply detection circuit;
the delay trigger circuit comprises a first switch tube, a first capacitor and a first trigger, wherein the input end of the first switch tube is the input end of the delay trigger circuit, the output end of the first switch tube is connected with the first end of the first capacitor and the input end of the first trigger, the second end of the first capacitor is grounded, and the output end of the first trigger is the output end of the delay trigger circuit.
2. The power reset circuit of claim 1 wherein said switching circuit comprises a second switching tube, a controlled end of said second switching tube being a controlled end of said switching circuit, an input end of said second switching tube being grounded, and an output end of said second switching tube being an output end of said switching circuit.
3. The power reset circuit of any one of claims 1 to 2, wherein the post-stage power reset circuit comprises a third switching tube, a second capacitor and a second trigger, wherein an input end of the third switching tube is an input end of the post-stage power reset circuit, an output end of the third switching tube is interconnected with a first end of the second capacitor and an input end of the first trigger, a second end of the second capacitor is grounded, and an output end of the second trigger is used for outputting the power reset signal.
4. The power reset circuit of claim 3 wherein said post power reset circuit further comprises an inverter, an input of said inverter being connected to an output of said second flip-flop, an output of said inverter being configured to output said power reset signal after inversion.
5. An ASIC chip comprising the power reset circuit of any of claims 1 to 4.
6. The ASIC chip of claim 5, further comprising:
the input end of the bias voltage generating circuit is used for being connected with a power supply voltage, and the output end of the bias voltage generating circuit is connected with the power supply end of the MEMS sensor; the bias voltage generating circuit is used for generating bias voltage according to the accessed power supply voltage and outputting the bias voltage to the MEMS sensor;
the signal processing circuit is connected with the output end of the MEMS sensor; and the signal processing circuit is used for carrying out signal processing on the detection signal output by the MEMS sensor and outputting the detection signal.
7. A microphone comprising a MEMS sensor and a power reset circuit as claimed in any one of claims 1 to 4;
or comprises an ASIC chip as claimed in any of claims 5 or 6.
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| CN202111635924.5A CN114302305B (en) | 2021-12-28 | 2021-12-28 | Power supply reset circuit, ASIC chip and microphone |
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| CN202111635924.5A CN114302305B (en) | 2021-12-28 | 2021-12-28 | Power supply reset circuit, ASIC chip and microphone |
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| CN114302305A (en) | 2022-04-08 |
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