CN108462489B - Phase-locked loop starting circuit - Google Patents
Phase-locked loop starting circuit Download PDFInfo
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- CN108462489B CN108462489B CN201810541110.7A CN201810541110A CN108462489B CN 108462489 B CN108462489 B CN 108462489B CN 201810541110 A CN201810541110 A CN 201810541110A CN 108462489 B CN108462489 B CN 108462489B
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- transistor
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- locked loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/181—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a numerical count result being used for locking the loop, the counter counting during fixed time intervals
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention provides a phase-locked loop starting circuit, which comprises a NOR gate, a first NAND gate, a second NAND gate, a self-adding counter, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a transmission gate, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor. The invention can enable the phase-locked loop to quickly preset the internal important node to a specific level in controllable time, shorten the starting and locking time of the PLL, and control the starting sequence of the whole loop so as to prevent the whole loop from being changed due to the influence of process, voltage and temperature.
Description
Technical Field
The invention relates to the field of integrated circuit design, in particular to a phase-locked loop starting circuit.
Background
With the rapid development of integrated circuit designs and CMOS processes, integrated circuits have entered a System on Chip (SoC) design stage. With the continuous improvement of the complexity, the integration level and the working frequency of chips of an electronic system, the requirements on the distribution quality and the stability of an on-chip clock are also higher and higher. The phase-locked loop (Phase Locked Loop, PLL) is an important functional module in modern integrated circuit design as a clock source of a system on chip, and is widely applied to various SoC chips.
The phase-locked loop is a negative feedback system comparing an output phase with an input phase, and controls the frequency and phase of an oscillation signal inside the loop by using an externally input reference signal. As shown in fig. 1, the conventional pll START circuit has switches S1 and S2 open, S3 closed, and VCTL is pulled to VDD voltage before the input signal START comes; after the START signal comes, S2 is turned off, S1 and S3 are turned on, the VCTL signal is slowly pulled down by the VREF1 signal until the comparator toggles, generating control signals for the various blocks in the PLL, and turning S1 off, and the START-up process ends. The conventional pll starting circuit compares two analog voltages VREF1 and VREF2 with a comparator, and the generated signal is used as an enable signal of the entire loop, and since offset voltage (offset) of the comparator and the time for VCTRL to pull down are affected by the process, voltage and temperature, the comparison result is inaccurate, and the time for the comparator to flip is not fixed, which may cause an abnormal pll starting state.
Disclosure of Invention
The invention aims to provide a phase-locked loop starting control circuit which can accelerate the starting of the phase-locked loop, shorten the locking time and enhance the stability and the reliability of the phase-locked loop.
The technical solution for realizing the purpose of the invention is as follows: a phase-locked loop start-up circuit comprising a nor gate, a first nand gate, a second nand gate, a self-up counter, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a transmission gate, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, wherein: one input end of the NOR gate is connected with the Q output end of the up-counter, the other input end of the NOR gate is connected with the input end CLKN of the phase-locked loop starting circuit, and the output end of the NOR gate is connected with the CK input end of the up-counter; one input end of the first NAND gate is connected with the QN output end of the self-up counter, the other input end of the first NAND gate is connected with the input end CLKP of the phase-locked loop starting circuit, and the output end of the first NAND gate is connected with the CN input end of the self-up counter; the Q output end of the self-adding counter is also connected with the input ends of the first inverter and the third inverter, the output end LOOP_ST of the phase-locked LOOP starting circuit, and the RESET input end is connected with the input end RESET of the phase-locked LOOP starting circuit; the output end of the first inverter is connected with the input end of the second inverter and the gate end of the second transistor; the output end of the second inverter is connected with the gate ends of the fifth transistor and the seventh transistor; the output end of the third inverter is connected with one input end of the second NAND gate; the other input end of the second NAND gate is connected with the input end RESET of the phase-locked loop starting circuit, and the output end of the second NAND gate is connected with the input end of the fourth inverter; the output end of the fourth inverter is connected with the gate end of the eighth transistor; the input end of the fifth inverter is connected with the input end RESET of the phase-locked loop starting circuit, the gate end of the first transistor and one control end of the transmission gate, and the output end of the fifth inverter is connected with the other control end of the transmission gate, the gate ends of the sixth transistor and the fourth transistor; the drain terminals of the second transistor and the seventh transistor are connected, the drain terminals of the eighth transistor and the fifth transistor are connected with the source terminals of the sixth transistor and the first transistor, and the output terminal V1 of the phase-locked loop starting circuit is connected with the drain terminals of the second transistor and the seventh transistor; the source terminal of the fifth transistor is grounded; the source end of the eighth transistor is connected with a power supply Vdd; the drain ends of the sixth transistor and the first transistor are connected, and the drain end of the third transistor is connected with the input end of the transmission gate; the drain terminal is connected with the output terminal of the transmission gate and the source terminal of the third transistor; the source terminals of the fourth transistor and the third transistor are grounded.
As a preferred embodiment, the self-up counter comprises at least three D flip-flops, wherein the input CK, CN of the first D flip-flop is the input CK, CN of the self-up counter, respectively, and the output Q, QN of the last D flip-flop is the output Q, QN of the self-up counter, respectively, and the input CK, CN of the intermediate D flip-flop is connected to the output Q, QN of the previous D flip-flop.
As a preferred embodiment, the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are all N-type transistors.
As a preferred embodiment, the sixth transistor, the seventh transistor and the eighth transistor are P-type transistors.
As a preferred embodiment, the first inverter, the second inverter, the third inverter, the fourth inverter, and the fifth inverter are TTL not gates.
Compared with the prior art, the invention has the remarkable advantages that:
1) The invention can enable the phase-locked loop to quickly preset the internal important node to a specific level in controllable time, and shortens the starting and locking time of the PLL;
2) The invention can control the starting sequence of the whole loop by counting the output clock of the VCO by the self-adding counter, so that the starting sequence is not changed due to the influence of the process, the voltage and the temperature.
Drawings
Fig. 1 is a diagram of a conventional phase-locked loop start-up circuit.
Fig. 2 is a diagram of a phase locked loop start-up circuit of the present invention.
Fig. 3 is a block diagram of the phase-locked loop portion of the present invention.
Fig. 4 is a circuit diagram of a self-up counter.
Detailed Description
The present invention will be further described with reference to the drawings and the specific embodiments.
As shown in fig. 2, the pll starting circuit 201 includes a nor gate 101, a first nand gate 102, a second nand gate 107, a self-up counter 103, a first inverter 104, a second inverter 105, a third inverter 106, a fourth inverter 108, a fifth inverter 109, a transmission gate 110, a first transistor MN1, a second transistor MN2, a third transistor MN3, a fourth transistor MN4, a fifth transistor MN5, a sixth transistor MP1, a seventh transistor MP2, and an eighth transistor MP3, and the connection relationships between the components are as follows:
the input RESET of the pll start circuit 201 is connected to the input of the inverter 109, and the inverter 109 provides a signal opposite to the input signal RESET to the circuit.
MN3, MN4 source-to-ground, MN4 drain-to-drain, MN3 gate and transmission gate 110 output, MN3 drain-to-drain, transmission gate 110 input, MN4 gate and transmission gate 110 one control terminal, inverter 109 output, transmission gate 110 another control terminal, phase-locked loop start circuit 201 input RESET.
A transmission gate is formed by a P pipe MP1 and an N pipe MN1, and the source end of a N, P pipe is connected with the drain end of MP 3; the drain is connected to the drain of MN3 and the input of transmission gate 110. The gate of MP1 is connected with the output end of inverter 109 and the gate of MN 4; the gate of MN1 is connected to the RESET input of pll 201. MP3 provides a high voltage for VC, the source is connected with the power supply Vdd, and the grid is connected with the output end of the inverter 108.
One input end of the nor gate 101 is connected with the Q output end of the up counter 103, the other input end is connected with the input end CLKN of the phase-locked loop starting circuit 201, and the output end is connected with the CK input end of the up counter 103; one input end of the NAND gate 102 is connected with the QN output end of the up counter 103, the other input end is connected with the input end CLKP of the phase-locked loop starting circuit 201, and the output end is connected with the CN input end of the up counter 103. The outputs of nor gate 101 and nand gate 102 are a pair of inverted signals. As a specific embodiment, the self-up counter 103 is composed of n (n is greater than or equal to 3) D flip-flops, as shown in fig. 4, the input terminals CK and CN of the D flip-flop 301 are respectively connected to the output terminal of the nor gate 101 and the output terminal of the nand gate 102, and the output terminal Q, QN is respectively connected to the input terminals CN and CK of the D flip-flop 302. The D flip-flops 302 and 303 can be connected with n D flip-flops according to the requirement, and the connection method is the same as that described above. If the number of D flip-flops included in the self-up counter 103 is an even number, the output terminal Q, QN of the D flip-flop 301 is connected to the input terminals CK, CN of the D flip-flop 302, respectively, and the output terminal Q, QN of the n/2D flip-flop is connected to the output terminals CN, CK of the (n+1)/2D flip-flop, respectively. The output terminal Q, QN of the D flip-flop 303 is fed back to the input terminal to perform the function of dividing by two, so the self-up counter 103 is required to count up to 2 （n-1） The output signal loop_st of the phase-locked LOOP start-up circuit 201 is output after a period.
The output Q of the self-up counter 103 is connected to the inputs of inverters 104, 106. The output of inverter 106 is coupled to one input of NAND gate 107, and the other input of NAND gate 107 is coupled to the input RESET of PLL enable circuit 201, and the output signal of NAND gate 107 is either set to 1 or varies with the output LOOP_ST signal of PLL enable circuit 201. The output end of the NAND gate 107 is connected with the input end of the inverter 108, the output end of the inverter 108 is connected with the grid electrode of MP3, and the switch of MP3 is controlled, so that the charging of the VC point by the high level is controlled.
The output end of the inverter 104 is connected with the input end of the inverter 105 and the grid electrode of the MN2, the output end of the inverter 105 is connected with the grid electrodes of the MP2 and the MN5, the MN2 and the MP2 form a transmission gate to control the charging and discharging of the VC to the V1, the source ends are connected with the drain ends of the MP3 and the MN5 and the source ends of the MP1 and the MN 1; the drain terminal is connected to the output terminal V1 of the pll start circuit 201. The source of MN5 is grounded to provide a discharge path for the VC point in the circuit.
The connection relationship between the pll start-up circuit 201 and the Voltage Controlled Oscillator (VCO), frequency DIVIDER (DIVIDER) 203, and Phase Frequency Detector (PFD) 204 is shown in fig. 3. When reset=0, the entire phase-locked loop is in a RESET state. The RESET signal is turned off by inverter 109, net01 signal is 1, mn1, MP 1. The RESET signal goes through nand gate 107, setting the net02 signal to 1, and through inverter 108, setting the MP3 input signal to 0 causes the pipe to open and the VC point begins to charge to high Vdd. At this time, since reset=0, the self-up counter 103 is not enabled, the loop_st signal is 0, the net03 signal is 1 through the inverter 104, the MN2 input signal is turned on from low to high, the net04 signal is 0, the mp2 input signal is 0 through the inverter 105, the tube is turned on, the MN5 is turned off, and the high level is transmitted from the VC point to the V1 point. RESET is 0, the net01 signal is 1, the MN4 input signal is turned on from low to high through the inverter 109, the high level of the MN3 gate is pulled down to 0, and the unknown Z is avoided.
When reset=1, the whole phase-locked LOOP starts, the RESET signal passes through the nand gate 107, so that the net02 signal changes with the loop_st, at this time, the loop_st signal is 0, the mp3 input signal is 1, and the pipe is cut off; MP2 and MN2 are kept on, MN5 is kept off, and VC and V1 are kept at high level; meanwhile, the RESET signal passes through the inverter 109, so that the net01 signal is 0, the MN1 and the MP1 are turned on, the MN4 is turned off, the V1 begins to discharge along with the VC point, and the drain end of the MN3 is charged; the transmission gate 110 is turned on, the high level is transferred from the MN3 drain to the MN3 gate via net05, causing the pipe to turn on from low to high, and the MN3 drain signal is pulled low.
The RESET signal remains at 1, the Voltage Controlled Oscillator (VCO) 202, the self-up counter 103 is enabled, when V1 discharges to a certain level (related to VCO design parameters) along with VC, the Voltage Controlled Oscillator (VCO) 202 begins to oscillate, outputting CLKN, CLKP signals, at which time V1 continues to fall; after the CLK signal counts N periods through the self-up counter (which can be set by the counter), the output indication signal loop_st signal is 1, the net03 signal is 0 through the inverter 104, the net04 signal is 1 through the inverter 105, the mn2 and MP2 are turned off, the V1 point is suspended, and the specific level is kept not to drop any more. MN5 turns on, pulling the VC point voltage down to 0. The frequency DIVIDER (DIVIDER) 203 and the Phase Frequency Detector (PFD) 204 are enabled to start working under the control of the loop_st signal, the whole LOOP is opened, and the phase-locked LOOP starting process is finished.
Claims (5)
1. A phase-locked loop start-up circuit comprising a nor gate (101), a first nand gate (102), a second nand gate 107, a self-up counter (103), a first inverter (104), a second inverter (105), a third inverter (106), a fourth inverter (108), a fifth inverter (109), a transmission gate (110), a first transistor (MN 1), a second transistor (MN 2), a third transistor MN3, a fourth transistor (MN 4), a fifth transistor (MN 5), a sixth transistor (MP 1), a seventh transistor (MP 2) and an eighth transistor (MP 3), characterized in that: one input end of the NOR gate (101) is connected with the Q output end of the up counter (103), the other input end of the NOR gate is connected with the input end CLKN of the phase-locked loop starting circuit (201), and the output end of the NOR gate is connected with the CK input end of the up counter (103); one input end of the first NAND gate (102) is connected with the QN output end of the self-up counter (103), the other input end of the first NAND gate is connected with the input end CLKP of the phase-locked loop starting circuit (201), and the output end of the first NAND gate is connected with the CN input end of the self-up counter (103); the Q output end of the self-adding counter (103) is also connected with the input ends of the first inverter (104) and the third inverter (106) and the output end LOOP-ST of the phase-locked LOOP starting circuit (201), and the RESET input end is connected with the input end RESET of the phase-locked LOOP starting circuit (201); the output end of the first inverter (104) is connected with the input end of the second inverter (105) and the gate end of the second transistor (MN 2); the output end of the second inverter (105) is connected with the gate ends of the fifth transistor (MN 5) and the seventh transistor (MP 2); the output end of the third inverter (106) is connected with one input end of the second NAND gate (107); the other input end of the second NAND gate (107) is connected with the input end RESET of the phase-locked loop starting circuit (201), and the output end of the second NAND gate is connected with the input end of the fourth inverter (108); the output end of the fourth inverter (108) is connected with the gate end of the eighth transistor (MP 3); the input end of the fifth inverter (109) is connected with the input end RESET of the phase-locked loop starting circuit (201), the gate end of the first transistor (MN 1) and one control end of the transmission gate (110), and the output end is connected with the other control end of the transmission gate (110), the gate ends of the sixth transistor (MP 1) and the fourth transistor (MN 4); the source ends of the second transistor (MN 2) and the seventh transistor (MP 2) are connected, the drain ends of the eighth transistor (MP 3) and the fifth transistor (MN 5) and the source ends of the sixth transistor (MP 1) and the first transistor (MN 1), the drain ends of the second transistor (MN 2) and the seventh transistor (MP 2) are connected, and the output end V1 of the phase-locked loop starting circuit (201) is connected; a source terminal of the fifth transistor (MN 5) is grounded; the source end of the eighth transistor (MP 3) is connected with a power supply Vdd; the drain terminal of the sixth transistor (MP 1) and the drain terminal of the first transistor (MN 1) are connected, and the drain terminal of the third transistor (MN 3) and the input terminal of the transmission gate (110); the drain end of the fourth transistor (MN 4) is connected with the output end of the transmission gate (110) and the source end of the third transistor (MN 3); the source terminals of the fourth transistor (MN 4) and the third transistor (MN 3) are grounded.
2. The phase-locked loop start-up circuit of claim 1, wherein: the self-up counter (103) comprises at least three D flip-flops, wherein the input ends CK and CN of the first D flip-flop are respectively used as the input ends CK and CN of the self-up counter (103), the output end Q, QN of the last D flip-flop is respectively used as the output end Q, QN of the self-up counter (103), and the input ends CK and CN of the D flip-flop positioned in the middle are connected with the output end Q, QN of the previous D flip-flop.
3. The phase-locked loop start-up circuit of claim 1, wherein: the first transistor (MN 1), the second transistor (MN 2), the third transistor (MN 3), the fourth transistor (MN 4), and the fifth transistor (MN 5) are N-type transistors.
4. The phase-locked loop start-up circuit of claim 1, wherein: the sixth transistor (MP 1), the seventh transistor (MP 2) and the eighth transistor (MP 3) are P-type transistors.
5. The phase-locked loop start-up circuit of claim 1, wherein: the first inverter (104), the second inverter (105), the third inverter (106), the fourth inverter (108) and the fifth inverter (109) are TTL NOT gates.
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| CN201810541110.7A CN108462489B (en) | 2018-05-30 | 2018-05-30 | Phase-locked loop starting circuit |
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| CN201810541110.7A CN108462489B (en) | 2018-05-30 | 2018-05-30 | Phase-locked loop starting circuit |
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| CN108462489B true CN108462489B (en) | 2023-09-29 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107181487A (en) * | 2017-05-15 | 2017-09-19 | 西安电子科技大学 | A kind of charge pump phase lock loop of quick lock in |
| CN107222187A (en) * | 2017-04-18 | 2017-09-29 | 宁波大学 | A kind of short pulse type d type flip flop based on FinFET |
| CN207869089U (en) * | 2018-05-30 | 2018-09-14 | 南京胜跃新材料科技有限公司 | Phaselocked loop start-up circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TW201421907A (en) * | 2012-11-30 | 2014-06-01 | Univ Nat Chiao Tung | Pulse-based flip flop |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107222187A (en) * | 2017-04-18 | 2017-09-29 | 宁波大学 | A kind of short pulse type d type flip flop based on FinFET |
| CN107181487A (en) * | 2017-05-15 | 2017-09-19 | 西安电子科技大学 | A kind of charge pump phase lock loop of quick lock in |
| CN207869089U (en) * | 2018-05-30 | 2018-09-14 | 南京胜跃新材料科技有限公司 | Phaselocked loop start-up circuit |
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