JP2005323269A - Reset control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that a control system for an actuator such as a motor which includes a plurality of blocks having a reset function enters an unstable system state after resetting is released and when the actuator is driven while the system is in the unstable state, there is a possibility of causing an operation different from an expected operation to possibly cause deterioration or breaking of an element of the system. <P>SOLUTION: A reset control circuit is equipped with a circuit 12 which outputs a power-ON reset signal S1 and 1st and 2nd delay circuits 14 and 15 which divide the signal S1 into a CPU reset signal S2a and a communication circuit reset signal S3a and delay the signals S2a and S3a by fixed times, is characterized in that a sensor 1b, a CPU 1c, and a communication circuit 1d which are a plurality of functional blocks are reset for certain times with the signals S1a, S2a, and S3a respectively and then released from being reset in successively different timing according to the delay times of the signals S2a and S3a of the circuits 14 and 15. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a reset control circuit that performs control so that reset states of a plurality of functional blocks are sequentially released at different timings in a control system having a plurality of blocks having a reset function.

Conventionally, in a control system for an actuator such as a motor that has multiple blocks with a reset function, the start-up process for all blocks that release the power-on reset signal, such as when the power is turned on, is constant after the power is turned on. After a lapse of time, it is performed simultaneously with a single signal.
Further, as shown in Patent Document 1, in a control system having a plurality of blocks (CPUs), a defective CPU is separated from a control target among a plurality of CPUs, and a normal CPU is assigned in a certain order. In addition, the start-up is also performed sequentially.

JP-A-8-16534

In the control system as described above, the system state after reset release becomes unstable. Driving the actuator in an unstable state of the system may cause an operation different from an expected operation, and may cause deterioration or destruction of system elements.
Also, the time required for the system to stabilize when the power is turned on is largely dependent on the operating environment, and is difficult to quantify. Therefore, for example, when a reset signal is given to all blocks using only a single signal, it is necessary to set the time from reset release to the start of system operation with a sufficient margin. It takes a long time to start.
Accordingly, the present invention provides a reset control circuit capable of shortening the rise time of the system while ensuring the reliability of the operation of the system at the time of reset.

A reset control circuit that solves the above problems has the following characteristics.
That is, the reset signal output means for outputting the main reset signal, the reset signal dividing means for dividing the main reset signal into a plurality of sub reset signals, and at least one sub reset signal among the plurality of sub reset signals. Delay means for delaying the reset signal for a fixed time, and the plurality of functional blocks are respectively set to a reset state by the sub-reset signal, and are sequentially reset at different timings according to the delay time of the sub-reset signal by the delay means. The state is released.
Thereby, by setting the optimum delay time in each functional block at the time of start-up, it is possible to shorten the time from the power-on to the completion of the start-up of the control system.

According to a second aspect of the present invention, the order in which the reset states of the plurality of functional blocks are released matches the order of the signal processing process flow of each functional block.
Thereby, the signal at the time of normal operation of each functional block can be reflected to the next functional block, and an unstable signal is not processed.
Further, it is possible to prevent deterioration and destruction of the element due to a malfunction when the power is turned on, and it is possible to improve the reliability of the motor control system.

According to a third aspect of the present invention, the delay means cancels the reset state of the next functional block after the time necessary for the functional block to operate normally has elapsed after canceling the reset state of a certain functional block. To release.
Thereby, each functional block does not operate or malfunction in a state where it is not unstable, element deterioration and destruction can be prevented, and the reliability of the motor control system can be improved.

According to a fourth aspect of the present invention, the delay means is constituted by a digital timer that operates by inputting a clock signal.
Thereby, when the specification of the motor control system is changed, the setting of the delay time of the delay means can be easily changed.

According to a fifth aspect of the present invention, the delay unit includes a reference voltage, an RC line composed of passive elements such as a resistor and a capacitor, and a comparison unit that compares the reference voltage with an output voltage from the RC line. Yes.
This eliminates the need to wait for the timer oscillation circuit to stabilize compared to the case where a digital timer is used as a delay means, shortening the time until the control system stabilizes and completing startup quickly. It becomes possible to make it.

According to the present invention, it is possible to shorten the time from when the power is turned on to when the control system starts up by setting the optimum delay time for each functional block at the time of startup of the control system.
In addition, a signal at the time of normal operation of each functional block can be reflected to the next functional block, and an unstable signal is not processed. Further, it is possible to prevent deterioration and destruction of the element due to a malfunction when the power is turned on, and it is possible to improve the reliability of the motor control system.

Next, modes for carrying out the present invention will be described with reference to the accompanying drawings.
A motor control system as a control system including the reset control circuit of the present invention will be described.
As shown in FIG. 1, the motor control system mainly includes a control system unit 1 and a drive system unit 2.

The control system unit 1 includes a power supply IC 1a, a sensor 1b that detects the rotation angle of the motor 2a, a CPU 1c that generates and outputs a motor control signal, and a communication circuit 1d. Each of the sensor 1b, the CPU 1c, and the communication circuit 1d is a functional block.
The communication circuit 1d connects an external control circuit 3 provided outside the control system unit 1 and the CPU 1c.
Further, a battery 4 is connected to the power supply IC 1a of the control system unit 1, and the motor control system is turned on and off by an ignition switch 5.
On the other hand, the drive system unit 2 includes a motor 2a, a motor drive circuit 2b, and a driven body 2c driven by the motor 2a.

In the motor control system configured as described above, the CPU 1c generates a motor control signal based on the rotation angle of the motor 2a detected by the sensor 1b of the control system unit 1. This motor control signal is output to the motor drive circuit 2b, the motor 2a is driven by the motor drive circuit 2b to which the motor control signal is input, and the driven body 2c is driven by the motor 2a.
The driven body 2c in the drive system unit 2 of the present control system is driven by a motor 2a with a predetermined stroke amount, and the stroke amount is determined by the external control circuit 3.

A reset control circuit 11 is configured in the power supply IC 1a, and the reset control circuit 11 controls a reset signal when the motor control system is powered on to start up the motor control system.
The flow of the signal processing process of each functional block when this motor control system is started is in the order of the sensor 1b, the CPU 1c, and the communication circuit 1d.

Here, since the output signals of the sensor 1b and the communication circuit 1d after the release of the power-on reset signal such as when the power is turned on are initial values, the CPU 1C receives the initial values of the sensor 1b and the communication circuit 1d as input signals. If it is received, the CPU 1c may generate a control signal that tries to drive the motor 2a in an operation different from the operation that should be expected.
Therefore, in the present control system, the motor 2a is improperly driven to prevent the element from being deteriorated or destroyed, thereby improving the reliability.

As shown in FIGS. 2 and 3, the reset control circuit 11 is composed of, for example, a CMOS digital circuit, and a power-on reset circuit 12 serving as a reset signal output means for outputting a main reset signal, A first delay circuit 14 and a second delay circuit 15 are provided as reset signal dividing means for dividing the reset signal.
Specifically, the first delay circuit 14 and the second delay circuit 15 shown in FIG. 3 are configured by a digital timer that operates in response to a clock signal input from the oscillation circuit 13.

The power-on reset signal S1, which is the main reset signal output from the power-on reset circuit 12, is input to the sensor 1b as it is as the sensor reset signal S1a, and is divided and delayed by the first delay circuit 14, and the first sub signal It becomes the reset signal S2.
The first sub-reset signal S2 is directly input to the CPU 1c as the CPU reset signal S2a and is divided and delayed by the second delay circuit 15 to become the second sub-reset signal S3. The second sub-reset signal S3 is input to the communication circuit 1d as the communication circuit reset signal S3a.

A timing chart of control in the reset control circuit 11 is as shown in FIG. The power-on reset signal S1, the sensor reset signal S1a, the CPU reset signal S2a, and the communication circuit reset signal S3a are, for example, low active.
When the power is turned on by the ignition switch 5, the power-on reset signal S1 is output by the power-on reset circuit 12, and the sensor reset signal S1a, the CPU reset signal S2a, and the communication are sent to the sensor 1b, the CPU 1c, and the communication circuit 1d, respectively. A circuit reset signal S3a is applied.

Thereafter, the sensor reset signal S1a is released at the same timing as the power-on reset signal S1 is released.
The first delay circuit 14 holds the CPU reset signal S2a until the sensor 1b operates normally, and a sufficient time t1 for the sensor 1b to operate normally after the sensor reset signal S1a is released. After the elapse of time, the CPU reset signal S2a is canceled.

Similarly, the second delay circuit 14 holds the communication circuit reset signal S3a until the CPU 1c operates normally, and a sufficient time t2 for the CPU 1c to operate normally after the CPU reset signal S2a is released. After elapses, the communication circuit reset signal S3a is canceled.
A sufficient time t1 for the sensor 1b to operate normally and a sufficient time t2 for the CPU 1c to operate normally are set in the power supply IC 1a in advance.

As described above, the reset signals of the respective functional blocks such as the sensor reset signal S1a, the CPU reset signal S2a, and the communication circuit reset signal S3a are collectively managed in the power supply IC 1a, and the delay means such as the first and second delay circuits 14 and 15 are used. The CPU reset signal S2a and the communication circuit reset signal S3a are delayed.
In this case, it is possible to shorten the time from the power-on to the completion of the startup of the control system by setting the optimum delay time in each functional block at the time of startup.
The first delay circuit 14 and the second delay circuit 15 cancel the reset state of a certain functional block (for example, the sensor 1b), and then wait for the time necessary for the functional block to operate normally. Since the functional block (for example, the CPU 1c) is released from the reset state, each functional block does not operate or malfunction in a stable state. Here, “the time required for the functional block to operate normally” can be, for example, the time until the power supply voltage of the functional block reaches a range of ± 10% of the specified voltage after reset is released. .

In particular, the order in which the reset state of the functional block is released is the same as the order of the signal processing process of each functional block as the order of the sensor 1b, the CPU 1c, and the communication circuit 1d. The signal at the time of operation can be reflected in the next functional block, and an unstable signal is not processed.
Thereby, it is possible to prevent deterioration and destruction of the element due to a malfunction at power-on, and to improve the reliability of the motor control system.

  In addition, since the first and second delay circuits 14 and 15 are constituted by digital timers that operate by inputting a clock signal, the first and second delay circuits are changed when the specifications of the motor control system are changed. The setting of the delay time of the circuits 14 and 15 can be easily changed.

Next, a second embodiment of the reset control circuit 11 will be described.
In the reset control circuit 11 shown in FIG. 5, the delay means includes a reference voltage, an RC line composed of passive elements such as resistors and capacitors, and a comparison means that compares the reference voltage and the output voltage from the RC line. ing.
That is, the reset control circuit 11 of FIG. 5 includes a power-on reset circuit 12, a delay circuit 21 composed of a resistor and a capacitor, a first comparator 22, and a second comparator 23. Has a reference voltage V1, and the second comparator 23 has a reference voltage V2. The reference voltage V1 and the reference voltage V2 are “V2> V1”.

The power-on reset signal S1 from the power-on reset circuit 12 is directly input to the sensor 1b as the sensor reset signal S1a, and is divided by the delay circuit 21 to become the first sub-reset signal S2.
The first sub-reset signal S2 is input to the first comparator 22, and is input from the first comparator 22 to the CPU 1c as the CPU reset signal S2a. The first comparator 22 compares the voltage of the first sub-reset signal S2 with the reference voltage V1, and cancels the input of the CPU reset signal S2a to the CPU 1c when the voltage of the first sub-reset signal S2 becomes higher. Is done.

The first sub-reset signal S2 is divided in the middle to become the second sub-reset signal S3, which is input to the second comparator 23, and is input from the second comparator 23 to the communication circuit 1d as the communication circuit reset signal S3a.
In the second comparator 23, the voltage of the second sub-reset signal S3 is compared with the reference voltage V2, and when the voltage of the second sub-reset signal S3 becomes higher, the input of the communication circuit reset signal S3a to the communication circuit 1d is performed. Canceled.

In this case, the sensor reset signal S1a is released at the same timing as the power-on reset signal S1 is released.
The CPU reset signal S2a is maintained in the output state until the voltage of the first sub-reset signal S2 becomes higher than the reference voltage V1 after the power-on reset signal S1 is canceled, and the communication circuit reset signal S3a is the second signal. The output state is maintained until the voltage of the sub-reset signal S3 becomes higher than the reference voltage V2.

The time that the output state of the CPU reset signal S2a is held after the power-on reset signal S1 is canceled varies depending on the resistance and capacitor specifications of the delay circuit 21 and the reference voltage V1, but the sensor reset signal S1a is canceled. After that, a sufficient time for the sensor 1b to operate normally is set.
Further, the time for which the output state of the communication circuit reset signal S3a is held varies depending on the resistance and capacitor specifications of the delay circuit 21 and the reference voltage V2, but the CPU 1c operates normally after the CPU reset signal S2a is released. It is set so that sufficient time has passed.

  Thus, by delaying the CPU reset signal S2a and the communication circuit reset signal S3a by the delay circuit 21 and the first and second comparators 22 and 23 formed of passive elements, the first and second described above are performed. Compared to the case where a digital timer is used as the second delay circuits 14 and 15, it is not necessary to wait for the time until the oscillation circuit 13 of the timer is stabilized, and the time until the control system is stabilized is shortened to stand up earlier. It is possible to complete the raising.

Next, a third embodiment of the reset control circuit 11 will be described.
In the reset control circuit 11 shown in FIG. 6, a plurality of delay circuits 25 and 26, which are RC lines composed of passive elements of resistors and capacitors, are provided as delay means.
The power-on reset signal S1 from the power-on reset circuit 12 is input to the sensor 1b as it is as the sensor reset signal S1a and is divided by the first delay circuit 25 to become the first sub-reset signal S2. S2 is input to the CPU 1c as the CPU reset signal S2a.
The first sub-reset signal S2 is divided in the middle by the second delay circuit 26 to become the second sub-reset signal S3. The second sub-reset signal S3 is input to the communication circuit 1d as the communication circuit reset signal S3a. .

In this case, the sensor reset signal S1a is released at the same timing as the power-on reset signal S1 is released.
Further, the CPU reset signal S2a is maintained in an output state until a sufficient time for the sensor 1b to operate normally passes by the first delay circuit 25 even after the power-on reset signal S1 is canceled. The circuit reset signal S3a is held in an output state by the second delay circuit 26 until a sufficient time has elapsed for the CPU 1c to operate normally.

In the above description of the control system, the motor control system for driving the motor has been described. However, for example, the control system for other actuators such as a cylinder can also be applied.
The control system unit 1 includes the sensor 1b, the CPU 1c, and the communication circuit 1d as functional blocks, but is not limited thereto.

It is a circuit diagram which shows the motor control system provided with the reset control circuit of this invention. It is a figure which shows the flow of a reset signal. It is a circuit diagram which shows the 1st example of a reset control circuit. It is a figure which shows the timing chart of the reset signal in this reset control circuit. It is a circuit diagram which shows the 2nd example of a reset control circuit. It is a circuit diagram which shows the 3rd example of a reset control circuit.

Explanation of symbols

1 Control system section 1a Power supply IC
1b Sensor 1c CPU
1d communication circuit 2 drive system section 2a motor 11 reset control circuit 12 power-on reset circuit 14 first delay circuit 15 second delay circuit

Claims (5)

A reset control circuit in a control system comprising a plurality of functional blocks,
Reset signal output means for outputting a main reset signal;
Reset signal dividing means for dividing the main reset signal into a plurality of sub-reset signals;
Delay means for delaying at least one sub-reset signal among the plurality of sub-reset signals for a fixed time,
A plurality of functional blocks are reset for a certain time by the sub-reset signal, and the reset state is sequentially released at different timings according to the delay time of the sub-reset signal by the delay means. .   The reset control circuit according to claim 1, wherein an order in which the reset states of the plurality of functional blocks are released coincides with an order of a signal processing process flow of each functional block.   The delay means cancels the reset state of the next functional block after the time necessary for the functional block to operate normally has elapsed after canceling the reset state of a certain functional block. The reset control circuit according to claim 1 or 2.   4. The reset control circuit according to claim 1, wherein the delay means is constituted by a digital timer that operates in response to an input of a clock signal. 2. The delay means comprises a reference voltage, an RC line composed of a passive element of a resistor and a capacitor, and a comparison means for comparing the reference voltage with an output voltage from the RC line. The reset control circuit according to claim 3.

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