CN208386968U - For generating the control circuit and lighting system of multichannel means of chaotic signals - Google Patents

Abstract

The utility model belongs to technical field of integrated circuits, provides a kind of for generating the control circuit and lighting system of multichannel means of chaotic signals；The control circuit includes: the first oscillator unit, the second oscillator unit, the first frequency unit, the second frequency unit and the first output unit；First oscillator unit generates the first oscillator signal；Second oscillator unit generates the second oscillator signal；First frequency unit carries out repeatedly frequency dividing to the first oscillator signal according to power-on reset signal and obtains multi-channel frequency division signal；Second frequency unit carries out repeatedly frequency dividing to the second oscillator signal according to power-on reset signal and obtains trigger signal；First output unit carries out first time logical operation to trigger signal and multi-channel frequency division signal according to power-on reset signal and obtains the very poor driving signal of multichannel regularity；By the utility model can effectively solve integrated circuit in traditional technology can not Conduce Disciplinarian difference driving signal, and its realized circuit function is single, can not blanket problem.

Description

For generating the control circuit and lighting system of multichannel means of chaotic signals

Technical field

The utility model belongs to technical field of integrated circuits more particularly to a kind of for generating the control of multichannel means of chaotic signals Circuit processed and lighting system.

Background technique

Large scale integrated circuit is generallyd use in traditional technology and generates driving signal, and then realizes corresponding circuit function； The functional requirement realized however as people for electronic circuit is more and more, passes through the generated driving signal of integrated circuit Performance parameter also becomes to become increasingly complex；Traditional integrated circuit generallys use some signals and generates chip to generate certain law Property very strong signal, although these very strong signals of regularity can drive electronic component to realize more complicated function simultaneously, It is contemplated that some special functional requirements in electronic circuit, if very strong by traditional integrated circuit regularity generated Signal cannot achieve preferable circuit function；It is with the illumination of LED (Light Emitting Diode, light emitting diode) lamp Example, people then need to generate irregular driving signal by electronic circuit to obtain better light appreciation effect Realize that multiple LED light carry out random sudden strain of a muscle, to bring good visual effect；However the integrated circuit of traditional technology can only give birth to At the very strong driving signal of regularity, multiple LED light can not be driven to realize preferable disorderly sudden strain of a muscle effect.

Therefore, integrated circuit generallys use signal generation chip and can be only generated the stronger drive of multichannel regularity in traditional technology Dynamic signal, the circuit structure of itself are fixed, it is difficult to which the very poor driving signal of Conduce Disciplinarian leads to traditional integrated circuit institute The circuit function of realization is single, and poor compatibility can not be generally applicable in, and the usage experience sense of user is lower.

Utility model content

The utility model provides a kind of for generating the control circuit and lighting system of multichannel means of chaotic signals, it is intended to solve In traditional technology integrated circuit can not Conduce Disciplinarian difference driving signal so that lead to the circuit function that integrated circuit is realized It is single, it can not blanket problem.

The utility model first aspect provides a kind of for generating the control circuit of multichannel means of chaotic signals, comprising:

It is configured to generate the first oscillator unit of the first oscillator signal；

It is configured to generate the second oscillator unit of the second oscillator signal；

It is connect with first oscillator unit, is configured to carry out first oscillator signal according to power-on reset signal N times divide to obtain the first frequency unit of the road L fractional frequency signal；

It connect, is configured to according to the power-on reset signal to second oscillator signal with second oscillator unit It carries out M frequency dividing and obtains the second frequency unit of trigger signal；And

It connect, is configured to according to the power-on reset signal pair with first frequency unit and second frequency unit The trigger signal and the road L fractional frequency signal carry out first time logical operation and obtain the first output unit of the road L driving signal；

Wherein, the N, the L and the M are greater than or equal to 2 positive integer, and L is less than or equal to N。

In one of them embodiment, first oscillator unit includes: the first NAND gate, the second NAND gate, One resistance, first capacitor, the first reverser, the second reverser, third reverser, the 4th reverser, the 5th reverser, the 6th are instead To device and the 7th reverser；

Wherein, the first end of the first resistor, the first end of the first capacitor and first reverser is defeated Enter the input terminal that end is connected to second reverser altogether, the output of second reverser terminates the first of second NAND gate Input terminal, the second input of second NAND gate terminate the output end of first NAND gate, and the of first NAND gate One input terminal and the output end of second NAND gate are connected to the input terminal of the 4th reverser altogether, first reverser Output terminates the input terminal of the third reverser, and the second of output termination first NAND gate of the third reverser is defeated Enter end, the output of the 4th reverser terminates the input terminal of the 5th reverser, the output end of the 5th reverser and The second end of the first capacitor is connected to the input terminal of the 6th reverser altogether, the output end of the 6th reverser and described The second end of first resistor is connected to the input terminal of the 7th reverser, the output termination described first of the 7th reverser altogether Frequency unit.

In one of them embodiment, second oscillator unit includes: third NAND gate, the 4th NAND gate, Two resistance, the second capacitor, the 8th reverser, the 9th reverser, the tenth reverser, the 11st reverser, the 12nd reverser, 13 reversers, the 14th reverser and the 15th reverser；

Wherein, the first end of the second resistance, the first end of second capacitor and the 8th reverser is defeated Enter the input terminal that end is connected to the 9th reverser altogether, the output of the 9th reverser terminates the first of the 4th NAND gate Input terminal, the second input of the 4th NAND gate terminate the output end of the third NAND gate, and the of the third NAND gate One input terminal and the output end of the 4th NAND gate are connected to the input terminal of the 11st reverser, the 8th reverser altogether Output terminate the input terminal of the tenth reverser, the output of the tenth reverser terminates the second of the third NAND gate Input terminal, the output of the 11st reverser terminate the input terminal of the 12nd reverser, the 12nd reverser The second end of output end and second capacitor is connected to the input terminal of the 13rd reverser altogether, the 13rd reverser The second end of output end and the second resistance is connected to the input terminal of the 14th reverser altogether, the 14th reverser Output terminates the input terminal of the 15th reverser, and the output of the 15th reverser terminates second frequency unit.

In one of them embodiment, first frequency unit includes: the 16th reverser and the first T trigger battle array Column；Wherein, the first T flip-flop array includes N number of cascade T trigger, each in the first T flip-flop array For accessing the power-on reset signal, the Q output of every level-one T trigger is used for the reset signal input terminal of grade T trigger The fractional frequency signal is exported, the Q output of i-stage T trigger connects the CKB input terminal of i+1 grade T trigger, i-stage T triggering The CK input terminal of the QB output termination i+1 grade T trigger of device；

The CKB input of first order T trigger in the first T flip-flop array terminates the defeated of the 16th reverser Outlet, the CK input terminal of the first order T trigger in the first T flip-flop array and the input terminal of the 16th reverser It is connected to first oscillator unit altogether；Wherein the i is 1 to any positive integer between N-1.

In one of them embodiment, second frequency unit include: the 17th reverser, eighteen incompatibilities to device and 2nd T flip-flop array；Wherein, the 2nd T flip-flop array includes M cascade T triggers, is triggered in the 2nd T In device array, the reset signal input terminal of every level-one T trigger is used to access the power-on reset signal, j-th stage T trigger Q output meets the CKB input terminal of+1 grade of T trigger of jth, the CK of QB output termination+1 grade of T trigger of jth of j-th stage T trigger Input terminal；

The CK input of first order T trigger in the input terminal of 17th reverser and the 2nd T flip-flop array End is connected to second oscillator unit altogether, in the 2nd T flip-flop array described in the QB output termination of M grades of T triggers For eighteen incompatibilities to the input terminal of device, the eighteen incompatibilities terminate first output unit to the output of device；Wherein, the j is 1 To any positive integer between M-1.

In one of them embodiment, first output unit includes: the 19th reverser and d type flip flop array； Wherein, the d type flip flop array includes L cascade d type flip flops, in the d type flip flop array, every level-one d type flip flop Reset signal input terminal is for accessing the power-on reset signal, and frequency dividing is believed all the way for the D input terminal access of every level-one d type flip flop Number, for exporting, driving signal, the CKB input terminal of every level-one d type flip flop are connected to the Q output of every level-one d type flip flop altogether all the way The input terminal of the output end of 19th reverser, the CK input terminal of every level-one d type flip flop and the 19th reverser is total It is connected to second frequency unit.

In one of them embodiment, further includes: with first frequency unit, second frequency unit and institute The connection of the first output unit is stated, access DC power supply is configured to and generates the power on reset unit of the power-on reset signal.

In one of them embodiment, the power on reset unit includes: the first PMOS tube, third capacitor, the 20th Reverser, the 21st reverser and the 22nd reverser；

The source electrode of first PMOS tube connects the DC power supply, the grounded-grid of first PMOS tube, and described first The drain electrode of PMOS tube and the first end of the third capacitor are connected to the input terminal of the 20th reverser, the third capacitor altogether Second end ground connection, the output of the 20th reverser terminates the input terminal of the 21st reverser, the described 20th The output of one reverser terminates the input terminal of the 22nd reverser, and the output end of the 22nd reverser is for defeated The power-on reset signal out.

In one of them embodiment, further includes: connect with first output unit, be configured to drive the road L Dynamic signal carries out second of logical operation and obtains the second output unit of multichannel Drive Optimization signal；

Wherein, second output unit includes multiple signal optimization modules, and each signal optimization module includes one Logic gate and a reverser；The logic gate includes at least two input terminals, and the input terminal access of the logic gate is driven all the way Dynamic signal, the output of the logic gate terminate the input terminal of the reverser, and the output end of the reverser is for exporting all the way Drive Optimization signal.

The utility model second aspect provides a kind of lighting system, including control circuit as described above, and with the control Circuit connection processed, the multiple LED light disorderly dodged under the driving of the road L driving signal.

In the above-mentioned control circuit for generating multichannel means of chaotic signals, the first oscillation is generated by the first oscillator unit Signal generates the second oscillator signal by the second oscillator unit, is carried out by the first frequency unit to the first oscillator signal multiple Multi-channel frequency division signal is obtained after frequency dividing, and the second oscillator signal is carried out by the second frequency unit to obtain triggering letter after repeatedly dividing Number, and then the first output unit carries out first time logical operation to trigger signal and multi-channel frequency division signal according to power-on reset signal After the irregular driving signal of multichannel can be obtained, due between per driving signal all the way frequency and the parameters such as phase have not Systematicness and randomness, and then a variety of circuit functions can be realized by the driving signal, each industry neck can be universally applied to In domain；The driving signal for any number that the control circuit can generate simultaneously, compatibility is strong, and scalability is high, the scope of application Extensively；Efficiently solving integrated circuit in traditional technology can not the driving signal of Conduce Disciplinarian difference, the circuit function realized It is single, it can not blanket problem.

Detailed description of the invention

Fig. 1 is provided by the embodiment of the utility model a kind of for generating the module of the control circuit of multichannel means of chaotic signals Structure chart；

Fig. 2 is a kind of circuit structure diagram of first oscillator unit provided by the embodiment of the utility model；

Fig. 3 is a kind of circuit structure diagram of second oscillator unit provided by the embodiment of the utility model；

Fig. 4 is a kind of circuit structure diagram of first frequency unit provided by the embodiment of the utility model；

Fig. 5 is a kind of circuit structure diagram of second frequency unit provided by the embodiment of the utility model；

Fig. 6 is a kind of circuit structure diagram of first output unit provided by the embodiment of the utility model；

Fig. 7 is provided by the embodiment of the utility model another for generating the mould of the control circuit of multichannel means of chaotic signals Block structural diagram；

Fig. 8 is a kind of circuit structure diagram of power on reset unit provided by the embodiment of the utility model；

Fig. 9 is a kind of circuit structure diagram of second output unit provided by the embodiment of the utility model；

Figure 10 is a kind of function structure chart of lighting system provided by the embodiment of the utility model.

Specific embodiment

Fig. 1 shows provided by the embodiment of the utility model for generating the mould of the control circuit 10 of multichannel means of chaotic signals Block structure illustrates only part relevant to the utility model embodiment, details are as follows for ease of description:

As shown in Figure 1, control circuit 10 includes: the first oscillator unit 101, the second oscillator unit 102, first frequency dividing Unit 103, the second frequency unit 104 and the first output unit 105, wherein the first oscillator unit 101 generates the first oscillation Signal H0, the second oscillator unit 102 generate the second oscillator signal L0；Pass through the first oscillator unit 101 generated first Oscillator signal H0 has specific frequency and phase, passes through the second oscillator signal L0 generated of the second oscillator unit 102 With specific frequency and phase, optionally, the parameter of the parameter of the first oscillator signal H0 and the second oscillator signal L0 can phases With can not also be identical, herein without limitation to this, wherein the parameter of the oscillator signal includes but is not limited to: the week of signal Phase, frequency, phase, amplitude；In the present embodiment, the parameter of the parameter of the first oscillator signal H0 and the second oscillator signal L0 not phase Together, wherein the first oscillator signal H0 is high-frequency signal, the period of the high-frequency signal is 10 microseconds between 900 microseconds；Second vibration Swinging signal L0 is low frequency signal, and the period of the low frequency signal is between 10 milliseconds to 900 milliseconds；Preferably, the first oscillator signal The period of H0 and the period of the second oscillator signal L0, it is necessary to meet following condition: the period of the first oscillator signal H0 and the second oscillation The period of signal L0 is all prime number, and the period of the second oscillator signal L0 is not belonging to 64 divided by the period of the first oscillator signal H0 Within integer；When meeting the condition in the period in the period of the first oscillator signal H0 and the second oscillator signal L0, control electricity It road 10 will the worse multi-channel drive signal D of Conduce Disciplinarian；All due to the first oscillator signal H0 and the second oscillator signal L0 With specific frequency of oscillation, control circuit 10 is repeatedly divided and is patrolled to the first oscillator signal H0 and the second oscillator signal L0 After volume operation, control circuit 10 can output multi-channel there is the driving signal of different frequency, to realize increasingly complex circuit function Energy.

First frequency unit 103 is connect with the first oscillator unit 101, and the first oscillator unit 101 believes the first oscillation Number H0 is transmitted to the first frequency unit 103, and the first frequency unit 103 is according to power-on reset signal POR to the first oscillator signal H0 N times are carried out to divide to obtain the road L fractional frequency signal Q；Wherein power-on reset signal POR has power on reset unit generation, by above replying by cable Position signal POR can be driven each electric power component in the first frequency unit 103 and carry out reset operation；Specifically, whenever first Frequency unit 103 carries out after once dividing the first oscillator signal H0, and the frequency of the first oscillator signal H0 will change, that After carrying out n times frequency dividing to the first oscillator signal H0 by the first frequency unit 103, obtained every fractional frequency signal Q all the way is There can be specific frequency, then the road L fractional frequency signal Q there will be multi-frequency.

Second frequency unit 104 is connect with the second oscillator unit 102, and the second frequency unit 104 is believed according to electrification reset Number POR carries out M frequency dividing to the second oscillator signal L0 and obtains trigger signal L1；Wherein power-on reset signal POR is in the second frequency dividing It can play the role of reset in unit 104；After carrying out M frequency dividing to the second oscillator signal L0 by the second frequency unit 104 The frequency of i.e. changeable second oscillator signal L0, and then the trigger signal L1 generated has specific frequency and phase；First is defeated Unit 105 is connect with the first frequency unit 103 and the second frequency unit 104 out, and the first output unit 105 is believed according to electrification reset Number POR carries out first time logical operation to the road trigger signal L1 and L fractional frequency signal Q and obtains the road L driving signal D；Due to first In output unit 105, the frequency of fractional frequency signal Q can be changed at random by carrying out logical operation to fractional frequency signal Q, therefore when the After one output unit 105 carries out first time logical operation to the road trigger signal L1 and L fractional frequency signal Q, per driving signal D's all the way What frequency and phase were randomly generated, there is arbitrariness；Then pass through the frequency of the generated road the L driving signal D of the first output unit 105 Rate and phase have the characteristics that irregular；Further, the output of the first output unit 105 terminates external electronic device, when When the road L driving signal D is transmitted to external electronic device by the first output unit 105, due to the frequency and phase of the road L driving signal D Position has the characteristics that arbitrariness and randomness, therefore it is various by multi-channel drive signal D external electronic device realization to can be driven Complicated circuit function, to meet actual demand of the people in each industrial circle.

It should be noted that the N, the L and the M are greater than or equal to 2 positive integer, and L is less than Or it is equal to N.

By the utility model embodiment, the first frequency unit 103 is according to power-on reset signal POR to the first oscillator signal H0 carries out repeatedly frequency dividing and obtains multi-channel frequency division signal Q, and the second frequency unit 104 is vibrated according to power-on reset signal POR to second Signal L0 carries out repeatedly frequency dividing and obtains trigger signal L1, since the first frequency unit 103 divides the first oscillator signal H0 Number can be adjusted according to actual needs, and then can obtain having the fractional frequency signal Q of different frequency, the second frequency dividing is single The number that 104 couple of second oscillator signal L0 of member is divided can also be adjusted according to actual needs, therefore control circuit 10 With high scalability；Simultaneously because carrying out the first logical operation to multi-channel frequency division signal Q by the first output unit 105 Irregular multi-channel drive signal D can be obtained, since the phase and frequency of multi-channel drive signal D has randomness and any Property, and then electronic circuit can be driven by multi-channel drive signal D and realize various circuit functions, to meet the various of technical staff Demand；And it can be adjusted according to the concrete function of electronic circuit by the number of the driving signal D generated of control circuit 10 Whole, compatibility is extremely strong, can be widely used in each industrial technical field；Efficiently solve integrated circuit in traditional technology Can not Conduce Disciplinarian difference driving signal, the circuit function for causing integrated circuit to be realized is single, can not generally be useful in each The problems in a industrial circle.

As an alternative embodiment, Fig. 2 shows the first oscillator units provided by the embodiment of the utility model 101 circuit structure, as shown in Fig. 2, the first oscillator unit 101 includes: the first NAND gate NAND1, the second NAND gate NAND2, first resistor R1, first capacitor C1, the first reverser INV1, the second reverser INV2, third reverser INV3, the 4th Reverser INV4, the 5th reverser INV5, the 6th reverser INV6 and the 7th reverser INV7；Wherein the of first resistor R1 The input terminal of one end, the first end of first capacitor C1 and the first reverser INV1 is connected to the input of the second reverser INV2 altogether End, the first input end of the second NAND gate NAND2 of output termination of the second reverser INV2, the second of the second NAND gate NAND2 The output end of the first NAND gate NAND1 of input termination, the first input end of the first NAND gate NAND1 and the second NAND gate NAND2 Output end be connected to the input terminal of the 4th reverser INV4 altogether, the output termination third reverser INV3's of the first reverser INV1 Input terminal, the second input terminal of the first NAND gate NAND1 of output termination of third reverser INV3, the 4th reverser INV4's is defeated The input terminal of the 5th reverser INV5 is terminated out, and the output end of the 5th reverser INV5 and the second end of first capacitor C2 are connected to altogether It is anti-that the input terminal of 6th reverser INV6, the output end of the 6th reverser INV6 and the second end of first resistor R1 are connected to the 7th altogether To the input terminal of device INV7, the output of the 7th reverser INV7 terminates the first frequency unit 103；Wherein the 7th reverser INV7 Output end is the output end of the first frequency unit 103, for the first oscillator signal H0 to be transmitted to the first frequency unit 103.

As an alternative embodiment, Fig. 3 shows the second oscillator unit provided by the embodiment of the utility model 102 circuit structure, as shown in figure 3, the second oscillator unit 102 includes: third NAND gate NAND3, the 4th NAND gate NAND4, second resistance R2, the second capacitor C2, the 8th reverser INV8, the 9th reverser INV9, the tenth reverser INV10, 11 reverser INV11, the 12nd reverser INV12, the 13rd reverser INV13, the 14th reverser INV14 and the tenth Five reverser INV15；Wherein, the first end of second resistance R2, the first end of the second capacitor C2 and the 8th reverser INV8 Input terminal is connected to the input terminal of the 9th reverser INV9 altogether, the 4th NAND gate NAND4's of output termination of the 9th reverser INV9 First input end, the output end of the second input termination third NAND gate NAND3 of the 4th NAND gate NAND4, third NAND gate The output end of the first input end of NAND3 and the 4th NAND gate NAND4 are connected to the input terminal of the 11st reverser INV11 altogether, the Eight reverser INV8 output termination the tenth reverser INV10 input terminal, the tenth reverser INV10 output termination third with The second input terminal of NOT gate NAND3, the input terminal of the 12nd reverser INV12 of output termination of the 11st reverser INV11, the The second end of the output end of 12 reverser INV12 and the second capacitor C2 are connected to the input terminal of the 13rd reverser INV13 altogether, the The output end of 13 reverser INV13 and the second end of second resistance R2 are connected to the input terminal of the 14th reverser INV14 altogether, the The input terminal of the 15th reverser INV15 of output termination of 14 reverser INV14, the output end of the 15th reverser INV15 Connect the second frequency unit 104；Wherein the output end of the 15th reverser INV15 is the output end of the second oscillator unit 102, is used In the second oscillator signal L0 is transmitted to the second frequency unit 104.

As an alternative embodiment, Fig. 4 shows the first frequency unit 103 provided by the embodiment of the utility model Circuit structure, as shown in figure 4, the first frequency unit 103 includes: the 16th reverser INV16 and the first T flip-flop array 1031；Wherein, the first T flip-flop array 1031 includes N number of cascade T trigger, in the first T flip-flop array 1031, often The reset signal input terminal R of level-one T trigger accesses power-on reset signal POR, can be realized by power-on reset signal POR Reset operation is carried out for each T trigger in the first frequency unit 1031；The Q output of every level-one T trigger is for defeated Fractional frequency signal Q out, the Q output of i-stage T trigger ZTRi meet the CKB input terminal of i+1 grade T trigger ZTRi+1, i-stage T The CK input terminal of the QB output termination i+1 grade T trigger ZTRi+1 of trigger ZTRi；In first T flip-flop array 1031 The output end of the 16th reverser INV16 of CKB input termination of first order T trigger ZTR1, in the first T flip-flop array 1031 The CK input terminal of first order T trigger ZTR1 and the input terminal of the 16th reverser INV16 be connected to the first oscillator unit altogether 101, for accessing the first oscillator signal H0.

It should be noted that the i is 1 to any positive integer between N-1.

In the circuit structure of the first frequency unit 103 out shown in Fig. 4, since the first T flip-flop array 1031 includes Multiple T triggers, and T trigger is used as electronic component common in the art, when the first T flip-flop array 1031 connects When entering the first oscillator signal H0, is overturn using the signal of multiple T triggers and keep function, the first T flip-flop array 1031 is right First oscillator signal H0 carries out that the road L fractional frequency signal Q1, Q2 ... QL-1, QL can be obtained after repeatedly dividing；Specifically, in conjunction in Fig. 4 The circuit structure of first frequency unit 103 is equivalent to each when the first oscillator signal H0 passes sequentially through every level-one T trigger Grade T trigger carries out a divide operation for the first oscillator signal H0；It is each and then in the first T flip-flop array 1031 The fractional frequency signal Q that the Q output of grade T trigger is exported has different frequency and phase；Therefore, optionally from the first T The signal composition road L point chosen L T trigger in flip-flop array 1031, and the Q output of this L T trigger is exported Frequency signal Q, then this road L fractional frequency signal Q has a variety of frequency and phase；It is preferably carried out mode as one kind, in order to The frequency and phase for enough making the road L fractional frequency signal Q have randomness and random ordering, preferential to select in the first T flip-flop array 1031 Take the Q output of N-L+1 grades to N grades of T trigger to be exported signal composition the road L fractional frequency signal Q1, Q2 ... QL-1, QL, due to have passed through multiple frequency dividing, the regularity of the frequency and phase of fractional frequency signal Q is worse at this time, and then 10 energy of control circuit Enough circuit functions of driving electronic circuit realization Various Complex.

It should be noted that in the circuit structure of the first frequency unit 103, due to passing through the first T flip-flop array 1031 couple of first oscillator signal H0 carries out having obtained the road L fractional frequency signal Q1, Q2 ... QL-1, QL after repeatedly dividing, then per all the way The fractional frequency signal period all can be the integral multiple in the first oscillator signal H0 period, and also can not phase per the period of fractional frequency signal all the way Together.

As an alternative embodiment, Fig. 5 shows the second frequency unit 104 provided by the embodiment of the utility model Circuit structure, as shown in figure 5, the second frequency unit 104 includes: the 17th reverser INV17, eighteen incompatibilities to device INV18 And the 2nd T flip-flop array 1041；Wherein the 2nd T flip-flop array 1041 includes M cascade T trigger ZTR1, ZTR2 ... ZTRM-1, ZTRM are replied by cable in the reset signal input terminal R access of every level-one T trigger in the 2nd T flip-flop array 1041 Position signal POR, carries out reset operation to the T trigger in the 2nd T flip-flop array 1041 by power-on reset signal POR；Jth The Q output of grade T trigger ZTRj meets the CKB input terminal of+1 grade of T trigger ZTRj+1 of jth, the QB of j-th stage T trigger ZTRj The CK input terminal of output termination+1 grade of T trigger ZTRj+1 of jth；The input terminal and the 2nd T trigger of 17th reverser INV17 The CK input terminal of first order T trigger ZTR1 is connected to the second oscillator unit 102 altogether in array 1041, for accessing the second oscillation Signal L0；The QB output of M grades of T trigger ZTRM terminates eighteen incompatibilities to the defeated of device INV18 in 2nd T flip-flop array 1041 Enter end, eighteen incompatibilities terminate the first output unit 105 to the output of device INV18, eighteen incompatibilities to the output end of device INV18 be the The output end of two divided-frequency unit 104, for trigger signal L1 to be transmitted to the first output unit 105.

It should be noted that the j is 1 to any positive integer between M-1.

According to the circuit structure of above-mentioned second frequency unit 104, the 2nd T flip-flop array 1041 includes M cascade T touchings Device is sent out, since T trigger has the function of keeping and overturn to signal, when the second oscillation of the 2nd T flip-flop array 1041 access When signal L0, then multiple T triggers have carried out multiple frequency dividing to the second oscillator signal L0, i.e., changeable second oscillator signal L0's Frequency and phase, and then the 2nd T flip-flop array 1041 produces the trigger signal L1 with different frequency and phase；Specifically , in practical applications, those skilled in the art can select the T trigger of different number, example in the second frequency unit 104 Property, M can be 10,11 or 12 etc., if the quantity of T trigger included in the 2nd T flip-flop array 1041 is more, then 2nd T flip-flop array 1041 also will be more to the second oscillator signal L0 number divided, so as to by changing the The quantity of T trigger in two T flip-flop arrays 1041, and then the trigger signal L1 of different frequency can be obtained, it can with high Scalability.

As an alternative embodiment, Fig. 6 shows the first output unit 105 provided by the embodiment of the utility model Circuit structure, as shown in fig. 6, the first output unit 105 includes: the 19th reverser INV19 and d type flip flop array 1051； Wherein, d type flip flop array 1051 includes L cascade d type flip flop ZDR1, ZDR2 ... ZDRL-1, ZDRL, in d type flip flop array In 1051, the reset signal input terminal R of every level-one d type flip flop accesses power-on reset signal POR, passes through power-on reset signal POR Reset operation is carried out to every level-one d type flip flop in d type flip flop array 1051, the D input terminal access of every level-one d type flip flop is all the way Fractional frequency signal, in conjunction with above-mentioned first frequency unit 103 circuit structure it is found that every level-one d type flip flop herein D input terminal point It is not connect with the Q output of T trigger in the first T flip-flop array 1031；The Q output of every level-one d type flip flop is for exporting Driving signal all the way can drive electronic circuit to realize corresponding function by the driving signal；The CKB of every level-one d type flip flop is defeated Enter the output end that end is connected to the 19th reverser INV19 altogether, the CK input terminal and the 19th reverser of every level-one d type flip flop The input terminal of INV19 is connected to the second frequency unit 104 altogether, for accessing trigger signal L1.

Specifically, d type flip flop has the processing function of digital signal as electronic component common in traditional technology； In d type flip flop array 1051, fractional frequency signal progress logical operation is defeated in turn to trigger signal L1 and all the way for every level-one d type flip flop Driving signal all the way out, as noted previously, as the phase and frequency of the road the L fractional frequency signal Q generated of the first frequency unit 103 is all With randomness and arbitrariness, therefore, d type flip flop array 1051 carries out the first logic to the road trigger signal L1 and L fractional frequency signal Q After operation, the frequency and phase of the obtained road L driving signal D also has erratic behavior, and is believed by T trigger triggering The logical operation that number L1 and fractional frequency signal Q are carried out will enhance the randomness and arbitrariness of multi-channel drive signal D；Due to multichannel The frequency and phase of driving signal D be it is extremely irregular, when multi-channel drive signal D is transmitted to the external world by the first output unit 105 Electronic circuit in, electronic circuit can be made to realize more complicated circuit function by multi-channel drive signal D.

In order to which the working principle of control circuit 10 in the utility model embodiment is better described, in conjunction with Fig. 1-6, pass through one A specific application scenarios illustrate the work step of control circuit 10, and this application scene is to apply above-mentioned control circuit 10 Multiple LED light are realized in the technical effect disorderly dodged, specific as follows:

In the conventional technology, the light source with different brightness and frequency is issued by multiple LED light, as disorderly dodges effect Fruit can bring good visual sense of beauty due to disorderly dodge by LED light, disorderly dodge by LED light wide Generally applied in the every field such as the Curtain Wall Design of skyscraper, billboard publicity；In this application scene, if technical staff 4 LED light are needed to realize the effect disorderly dodged, in this application scene, the parameter setting of control circuit 10 is as follows:

N=7；L=4；M=14；

It is at this time high-frequency signal, the first oscillator signal by the first oscillator signal H0 that the first oscillator unit 101 generates The period of H0 is 200 microseconds；It is low frequency signal, the second vibration by the second oscillator signal L0 that the second oscillator unit 102 generates The period for swinging signal L0 is 200 milliseconds；First frequency unit 103 obtains 4 tunnels to 7 frequency dividings of the first oscillator signal H0 progress and does not advise Fractional frequency signal Q1, Q2, Q3 and Q4 then, the second frequency unit 104 carry out 14 frequency dividings to the second oscillator signal L0 and are touched Signalling L1, as being random, and trigger signal L1 by the phase of trigger signal L1 obtained by the second frequency unit 104 Phase there are rising edges and failing edge；According to the control between the input signal and output signal of d type flip flop in traditional technology Logic, only when the signal that the CK input terminal of d type flip flop is accessed is rising edge, the signal phase of the Q output of d type flip flop It can be just consistent with the signal phase of the D input terminal of d type flip flop, then the letter accessed whenever the CK input terminal of d type flip flop When number there is rising edge, the signal phase of the Q output of d type flip flop will be kept with the signal phase of the D input terminal of d type flip flop Unanimously, thus, the signal period that the Q output of d type flip flop exports can be the CK input terminal institute input signal week of d type flip flop The integral multiple of phase.

The specific circuit structure in conjunction with the first output unit 105 in the utility model embodiment, due in d type flip flop array In 1051, fractional frequency signal, the CK input terminal of every level-one d type flip flop access triggering all the way for the D input terminal access of every level-one d type flip flop Signal L1, the reverse signal of the CKB input terminal access trigger signal L1 of every level-one d type flip flop, then the Q of every level-one d type flip flop The phase bit timing of output end institute output drive signal be by trigger signal L1 phase bit timing and fractional frequency signal phase bit timing Lai It determines；If the frequency of 4 road fractional frequency signal Q1, Q2, Q3 and Q4 and the frequency of trigger signal L1 have the characteristics that regularity is very poor, The frequency and phase for 4 tunnel driving signal D1, D2, D3 and D4 that so the first output unit 105 is exported also have regularity Very poor feature；Specifically, if trigger signal L1 be rising edge when, 103 4 road generated fractional frequency signal of the first frequency unit Q1, Q2, Q3 and Q4 are high level, then in d type flip flop array 1051, what the D input terminal of every level-one d type flip flop was accessed Signal is high level, and the signal that the CK input terminal of every level-one d type flip flop is accessed is rising edge, and the CKB of every level-one d type flip flop is defeated Entering the accessed signal in end is failing edge, according to the control logic between the input signal and output signal of d type flip flop, often at this time The driving signal that the Q output of level-one d type flip flop is exported is high level, and passes through the first output unit 105 is exported 4 Driving signal D1, D2, D3 and D4 can maintain always high level on road, when next rising edge occurs in trigger signal L1, drive The phase of dynamic signal can just change according to the phase of fractional frequency signal；Therefore when rising edge occurs in trigger signal L1, D touching The phase of driving signal and the phase of fractional frequency signal of the Q output output of hair device are consistent, and the phase of driving signal When can be maintained to the trigger signal L1 next rising edge of appearance, repeatedly, and then 105 pairs of triggerings letters of the first output unit Number L1 and 4 road fractional frequency signal Q1, Q2, Q3 and Q4 obtains 4 tunnel driving signal D1, D2, D3 and D4 after carrying out logical operation.

Therefore according to the working principle of above-mentioned first output unit 105, driving signal is generated by the first output unit 105 The phase cycling of D is determined according to the phase cycling of trigger signal L1 and the phase cycling of fractional frequency signal Q, if trigger signal L1 Phase and the phase of fractional frequency signal Q be all irregular distribution or the phase and the second oscillator signal of the first oscillator signal H0 The phase of L0 is all irregular distribution, then the phase of driving signal D also has erratic behavior；Specifically, working as trigger signal L1 Phase when there is rising edge, the level state of fractional frequency signal Q is uncertain, then the Q output institute by d type flip flop is defeated The level state of driving signal D is also uncertain out, i.e., per driving signal D all the way be likely to be at high level state can also Can be in low level state, thus the phase and frequency of driving signal D be all it is extremely irregular, have randomness and arbitrariness； Further, if the period of the first oscillator signal H0 and the period of the second oscillator signal L0 are all prime numbers, trigger signal L1's Phase and the phase of fractional frequency signal Q have higher randomness, and the matching degree of the two can be lower, so that control circuit 10 can give birth to At the worse multi-channel drive signal D of regularity, and then drives multiple LED light to realize and more preferably disorderly dodge effect.

As a preferred embodiment, circuit structure in, in the first frequency unit 103 and the first output unit Increase multiple logic gates, such as XOR gate, same or door and door, that is, NOT gate between 105, the road L is divided by multiple logic gates and is believed Number Q carries out logical operation, then the D that the signal after logical operation is transmitted to d type flip flop in the first output unit 105 is inputted End, so that the multi-channel drive signal D that d type flip flop array 1051 is exported has higher random ordering, regularity is worse.

In conjunction with the application scenarios of above-mentioned the utility model, first oscillator signal H0 is carried out by the first frequency unit 103 Multi-channel frequency division signal Q repeatedly is obtained after frequency dividing, second oscillator signal L0 is carried out after repeatedly dividing by the second frequency unit 104 Obtain trigger signal L1, due to the phase of fractional frequency signal Q, the phase of frequency and trigger signal L1, period be all it is uncertain, with Machine, thus when the first output unit 105 to trigger signal L1 and multi-channel frequency division signal Q carry out first time logical operation obtain it is more Road driving signal D, the phase of driving signal D be also it is uncertain, have randomness and arbitrariness, and then pass through control circuit 10 The very poor multi-channel drive signal D of regularity is generated, it is irregular that multiple LED light progress can be driven by multi-channel drive signal D It is random dodge, bring good user experience to audience；And according to the circuit composed structure of control circuit 10, control circuit 10 The number of generated driving signal can be adjusted according to the quantity of LED light, for example, control circuit 10 produce 4 tunnels, 5 tunnels or The driving signals such as 6 tunnel of person, to realize that the LED light of different number carries out random sudden strain of a muscle, therefore the compatibility of the control circuit 10 it is extremely strong, can Scalability is high, has the extensive scope of application；To solve the generated multi-way LED lamp driving letter of integrated circuit in traditional technology Number the unrest realized of too strong, the multiple LED light of regularity dodge ineffective, and then cause the visual experience sense of user is bad to ask Topic.

As a preferred embodiment, Fig. 7 show it is provided by the embodiment of the utility model for generating multichannel not Another circuit structure of the control circuit 10 of regular signal, compared to the modular structure of control circuit 10 shown in figure 1, figure Control circuit 10 shown in 7 further comprises power on reset unit 701 and the second output unit 702, specific:

Power on reset unit 701 and the first frequency unit 103, the second frequency unit 102 and the first output unit 105 connect It connects, power on reset unit 701 accesses DC power supply VDD and generates power-on reset signal POR, and power on reset unit 701 will Power-on reset signal POR is transmitted to other circuit units in control circuit 10, and power-on reset signal POR is in control circuit 10 The effect resetted can be achieved；Second output unit 702 is connect with the first output unit 105, and the first output unit 105 drives the road L Dynamic signal D is transmitted to the second output unit 702, and the second output unit 702 carries out second of logical operation to the road L driving signal D Obtain multichannel Drive Optimization signal DL；As noted previously, as having by the road the L driving signal that the first output unit 105 generates Very poor regularity, after the second output unit 702 carries out second of logical operation to the road L driving signal, obtained multichannel The phase and frequency of Drive Optimization signal DL has higher randomness and arbitrariness, is equivalent to control circuit 10 to trigger signal The road L1 and L fractional frequency signal Q has carried out logical operation twice, the multichannel Drive Optimization signal DL tool that control circuit 10 is exported at this time There is higher erratic behavior；Therefore, in the modular structure of control circuit 10 out shown in Fig. 7, the first output unit 105 passes through When second output unit 702 connects external electronic device, multichannel Drive Optimization signal DL was transmitted to by the second output unit 702 at that time When external electronic device, external electronic device can realize that the random of better effect dodges effect, mentions according to multichannel Drive Optimization signal DL The high practicability of the control circuit 10.

As an alternative embodiment, Fig. 8 shows power on reset unit 701 provided by the embodiment of the utility model Circuit structure, as shown in figure 8, power on reset unit 701 include: the first PMOS tube PMOS1, it is third capacitor C3, the 20th anti- To device INV20, the 21st reverser INV21 and the 22nd reverser INV22；Wherein, the source electrode of the first PMOS tube PMOS1 Meet DC power supply VDD, the drain electrode of the grounded-grid GND, the first PMOS tube PMOS1 of the first PMOS tube PMOS1 and third capacitor C3 First end be connected to the input terminal of the 20th reverser C20 altogether, the second end of third capacitor C3 is grounded GND, the 20th reverser The input terminal of the 21st reverser INV21 of output termination of INV20, the output termination second of the 21st reverser INV21 The input terminal of 12 reverser INV22, the output end of the 22nd reverser INV22 are the output end of power on reset unit 701, For exporting power-on reset signal POR.

According to the circuit structure of power on reset unit 701, when power on reset unit 701 is rigid obtains electric, the first PMOS tube PMOS1 conducting, DC power supply VDD charge to third capacitor C3 by the first PMOS tube PMOS1, since third capacitor C3 charging exists The effect of delay can be generated in charging process；In third capacitor C3 charging process, exported by power on reset unit 701 Power-on reset signal POR can maintain 1 microsecond to the high level state of 10 microseconds；After third capacitor C3 charging complete, power on Reset signal POR becomes low level state；And then power-on reset signal POR is transmitted to control circuit by power on reset unit 701 Other units (including the first frequency unit 103, the second frequency unit 102 and first output unit 105) in 10, to realize Other units in control circuit 10 carry out reset operation.

It is understood that power-on reset signal POR can rise in control circuit 10 in the utility model embodiment To the effect of reset, T trigger and d type flip flop carry out reset operation according to power-on reset signal in control circuit 10, in reality Other function signals can also be used to realize the effect of reset in application field, control circuit 10, it is only necessary to used other Power-on reset signal POR realizes identical reset function in function signal and the present embodiment, so that control circuit 10 also can Realize corresponding signal processing function.

As an alternative embodiment, the second output unit 702 includes multiple signal optimization modules, each signal is excellent Changing module includes a logic gate and a reverser；Logic gate includes at least two input terminals, the input terminal access one of logic gate Road driving signal, the output end of logic gate connect the input terminal of reverser, and the output end of reverser is for exporting Drive Optimization all the way Signal；Therefore in the second output unit 702, after carrying out logical operation to multi-channel drive signal D by multiple logic gates, into one Step enhances the frequency of driving signal D and the randomness of phase and arbitrariness, the second output unit 702 can output rule more The multichannel Drive Optimization signal of difference, and then electronic circuit is driven to realize more preferably circuit function.

Optionally, in the optimization module of the second output unit 702, logic gate are as follows: with or door, XOR gate, NAND gate or NOT gate or door or with door.

Illustratively, in order to better illustrate 702 working principle of the second output unit, Fig. 9 shows the utility model reality The circuit structure of second output unit 702 of example offer, the circuit structure of the first output unit 105 gone out as shown in connection with fig. 6 are provided； As shown in figure 9, the second output unit 702 contains 6 signal optimization modules 7021, and in each signal optimization module Logic gate in 7021 can be with door AND or door OR and XOR gate XOR etc., an input terminal random access of each logic gate Wherein driving signal D all the way, and then there is pole by the Drive Optimization signal DL that 7021 logical operation of signal optimization module generates Big randomness and contingency, and then the multichannel Drive Optimization by being exported after 702 second of the logical operation of the second output unit The phase and frequency of signal DL is extremely irregular, correspondingly, electronic circuit is realized according to multichannel Drive Optimization signal DL at this time Increasingly complex circuit effect.

By the utility model embodiment, control circuit 10 includes the first output unit 105 and the second output unit 702, on the one hand, first time logical operation is carried out to trigger signal L1 and multi-channel frequency division signal Q by the first output unit 105 and is obtained To multi-channel drive signal D, since the phase and frequency of multichannel driving has randomness and arbitrariness；On the other hand, pass through second Output unit 702 obtains the worse multichannel Drive Optimization letter of regularity after carrying out second of logical operation to multi-channel drive signal D Number DL, is equivalent to control circuit 10 at this time and has successively carried out logical operation twice to trigger signal L1 and multi-channel frequency division signal Q, keep away The multi-channel drive signal for having exempted from the output of the first output unit 105 still may have the problem of stronger regularity；By to multichannel Driving signal D, which carries out second of logical operation, will be significantly enhanced the randomness of multichannel Drive Optimization signal DL and irregular Property, so can the irregular Drive Optimization signal DL of general warranty multichannel can drive electronic circuit realize more preferably circuit imitate Fruit；And since the signal optimization module in the second output unit 702 can be adjusted according to actual needs, then the second output The Drive Optimization signal DL of the exportable any number of unit 702, compatibility with higher can be widely used in different industry In field；To efficiently solve the regular stronger and its institute of the driving signal generated of integrated circuit in traditional technology The circuit function of realization is single, can not blanket problem.

As an alternative embodiment, Figure 10 shows lighting system 100 provided by the embodiment of the utility model Modular structure, wherein lighting system 100 includes control circuit 10 as described above and multiple LED light 1001；Multiple LED light 1001 connect with control circuit 10 respectively, and multi-channel drive signal D is transmitted in multiple LED light by control circuit 10, and then multiple LED light carries out random sudden strain of a muscle under the driving of multi-channel drive signal D；According to discussed above, due to generated by control circuit 10 Driving signal D have the characteristics that it is extremely irregular, multiple LED light according to multi-channel drive signal D can be realized it is splendid it is random dodge effect, To enhance user experience；Therefore lighting system 100 can be applied the curtain wall in commercial advertising board, skyscraper by technical staff And the fields such as urban landscape lamp, there is extremely strong practical application value.

It is realized in the technical field disorderly dodged it should be noted that herein only applying control circuit 10 in LED light, Since this is only a kind of embodiment, do not constitute for electric for generating the control of multichannel means of chaotic signals in the utility model The technology limiting on road 10；It is understood that in practical applications, related technical personnel can apply the control circuit 10 in machine Other technical fields such as the mobile design of device people, the flight path control of unmanned plane, as long as inventive concept and the circuit of its essence Control circuit 10 is consistent in structure and the utility model, this still falls within the protection scope of the utility model.Meanwhile herein In, the quantity referred both to greater than 1 of such as multiple and multichannel etc；Such as first and second etc relational terms be used merely to by One entity is distinguished with another entity, and without necessarily requiring or implying between these entities, there are any this reality Relationship or sequence.And the terms "include", "comprise" or any other variant are intended to non-exclusive inclusion, from And make include a series of elements product or the intrinsic element of structure.In addition, herein, " being greater than ", " being less than ", " being more than " etc. is interpreted as not including this number；" more than ", " following ", " within " etc. be interpreted as including this number.

Claims (10)

1. a kind of for generating the control circuit of multichannel means of chaotic signals characterized by comprising

It is configured to generate the first oscillator unit of the first oscillator signal；

It is configured to generate the second oscillator unit of the second oscillator signal；

It is connect with first oscillator unit, is configured to carry out n times to first oscillator signal according to power-on reset signal Frequency dividing obtains the first frequency unit of the road L fractional frequency signal；

It is connect with second oscillator unit, is configured to carry out second oscillator signal according to the power-on reset signal M times frequency dividing obtains the second frequency unit of trigger signal；And

It connect, is configured to according to the power-on reset signal to described with first frequency unit and second frequency unit Trigger signal and the road L fractional frequency signal carry out first time logical operation and obtain the first output unit of the road L driving signal；

Wherein, the N, the L and the M are greater than or equal to 2 positive integer, and L is less than or equal to N.

2. circuit according to claim 1, which is characterized in that first oscillator unit includes: the first NAND gate, Two NAND gates, first resistor, first capacitor, the first reverser, the second reverser, third reverser, the 4th reverser, the 5th are instead To device, the 6th reverser and the 7th reverser；

Wherein, the input terminal of the first end of the first resistor, the first end of the first capacitor and first reverser It is connected to the input terminal of second reverser altogether, the output of second reverser terminates the first input of second NAND gate End, the second input of second NAND gate terminate the output end of first NAND gate, and the first of first NAND gate is defeated Enter the input terminal held and be connected to the 4th reverser altogether with the output end of second NAND gate, the output of first reverser The input terminal of the third reverser is terminated, the output of the third reverser terminates the second input of first NAND gate End, the output of the 4th reverser terminate the input terminal of the 5th reverser, the output end of the 5th reverser and institute The second end for stating first capacitor is connected to the input terminal of the 6th reverser, the output end of the 6th reverser and described altogether The second end of one resistance is connected to the input terminal of the 7th reverser, described first point of the output termination of the 7th reverser altogether Frequency unit.

3. control circuit according to claim 1, which is characterized in that second oscillator unit include: third with it is non- Door, the 4th NAND gate, second resistance, the second capacitor, the 8th reverser, the 9th reverser, the tenth reverser, the 11st are reversely Device, the 12nd reverser, the 13rd reverser, the 14th reverser and the 15th reverser；

Wherein, the input terminal of the first end of the second resistance, the first end of second capacitor and the 8th reverser It is connected to the input terminal of the 9th reverser altogether, the output of the 9th reverser terminates the first input of the 4th NAND gate End, the second input of the 4th NAND gate terminate the output end of the third NAND gate, and the first of the third NAND gate is defeated The output end for entering end and the 4th NAND gate is connected to the input terminal of the 11st reverser altogether, the 8th reverser it is defeated The input terminal of the tenth reverser is terminated out, and the output of the tenth reverser terminates the second input of the third NAND gate End, the output of the 11st reverser terminate the input terminal of the 12nd reverser, the output of the 12nd reverser The second end of end and second capacitor is connected to the input terminal of the 13rd reverser, the output of the 13rd reverser altogether The second end of end and the second resistance is connected to the input terminal of the 14th reverser, the output of the 14th reverser altogether The input terminal of the 15th reverser is terminated, the output of the 15th reverser terminates second frequency unit.

4. control circuit according to claim 1, which is characterized in that first frequency unit includes: the 16th reversed Device and the first T flip-flop array；Wherein, the first T flip-flop array includes N number of cascade T trigger, in the first T In flip-flop array, the reset signal input terminal of every level-one T trigger is for accessing the power-on reset signal, every level-one T touching For the Q output of hair device for exporting the fractional frequency signal, the Q output of i-stage T trigger meets the CKB of i+1 grade T trigger Input terminal, the CK input terminal of the QB output termination i+1 grade T trigger of i-stage T trigger；

The CKB input of first order T trigger in the first T flip-flop array terminates the output of the 16th reverser It holds, the CK input terminal of the first order T trigger in the first T flip-flop array and the input terminal of the 16th reverser are total It is connected to first oscillator unit；Wherein the i is 1 to any positive integer between N-1.

5. control circuit according to claim 1, which is characterized in that second frequency unit includes: the 17th reversed Device, eighteen incompatibilities are to device and the 2nd T flip-flop array；Wherein, the 2nd T flip-flop array includes M cascade T triggerings Device, in the 2nd T flip-flop array, the reset signal input terminal of every level-one T trigger is for accessing the electrification reset Signal, the Q output of j-th stage T trigger connect the CKB input terminal of+1 grade of T trigger of jth, the QB output end of j-th stage T trigger Connect the CK input terminal of+1 grade of T trigger of jth；

The CK input terminal of first order T trigger is total in the input terminal of 17th reverser and the 2nd T flip-flop array It is connected to second oscillator unit, the QB output termination the described tenth of M grades of T triggers in the 2nd T flip-flop array The input terminal of eight reversers, the eighteen incompatibilities terminate first output unit to the output of device；Wherein, the j is 1 to M- Any positive integer between 1.

6. control circuit according to claim 1, which is characterized in that first output unit includes: the 19th reversed Device and d type flip flop array；Wherein, the d type flip flop array includes L cascade d type flip flops, in the d type flip flop array, The reset signal input terminal of every level-one d type flip flop is for accessing the power-on reset signal, the D input terminal of every level-one d type flip flop Fractional frequency signal, the Q output of every level-one d type flip flop are used to export driving signal all the way all the way for access, every level-one d type flip flop CKB input terminal is connected to the output end of the 19th reverser altogether, and the CK input terminal of every level-one d type flip flop and the described 19th is instead It is connected to second frequency unit altogether to the input terminal of device.

7. control circuit according to claim 1, which is characterized in that further include: with first frequency unit, described Two divided-frequency unit and first output unit connection, are configured to access DC power supply and generate the power-on reset signal Power on reset unit.

8. control circuit according to claim 7, which is characterized in that the power on reset unit include: the first PMOS tube, Third capacitor, the 20th reverser, the 21st reverser and the 22nd reverser；

The source electrode of first PMOS tube meets the DC power supply, the grounded-grid of first PMOS tube, the first PMOS The drain electrode of pipe and the first end of the third capacitor are connected to the input terminal of the 20th reverser altogether, and the of the third capacitor Two ends ground connection, the output of the 20th reverser terminate the input terminal of the 21st reverser, and the described 21st is anti- The input terminal of the 22nd reverser is terminated to the output of device, the output end of the 22nd reverser is for exporting institute State power-on reset signal.

9. control circuit according to claim 1-8, which is characterized in that further include: it is single with first output Member connection, be configured to obtain second of the logical operation of progress of the road L driving signal multichannel Drive Optimization signal second are defeated Unit out；

Wherein, second output unit includes multiple signal optimization modules, and each signal optimization module includes a logic Door and a reverser；The logic gate includes at least two input terminals, and driving is believed all the way for the input terminal access of the logic gate Number, the output of the logic gate terminates the input terminal of the reverser, and the output end of the reverser drives all the way for exporting Optimize signal.

10. a kind of lighting system, is characterized in that, including such as the described in any item control circuits of claim 1-9, and with the control Circuit connection processed, the multiple LED light disorderly dodged under the driving of the road L driving signal.