CN113328732B - Dead time generation method and circuit with controllable delay time - Google Patents
Dead time generation method and circuit with controllable delay time Download PDFInfo
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- CN113328732B CN113328732B CN202110663156.8A CN202110663156A CN113328732B CN 113328732 B CN113328732 B CN 113328732B CN 202110663156 A CN202110663156 A CN 202110663156A CN 113328732 B CN113328732 B CN 113328732B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
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- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
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- H03K2005/00019—Variable delay
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Abstract
The invention discloses a dead time generation method and a dead time generation circuit with controllable delay time, wherein the dead time generation method comprises the following steps of: generating an oscillation clock based on a resistor and capacitor network connected in series, and preprocessing the oscillation clock; the oscillation clock is used as clock input and carries out buffer processing on the data input signal to generate a positive phase and an inverse phase output signal; the oscillation clock and the preprocessed oscillation clock are used as clock inputs, rising edges and falling edges of data input signals are identified, and pulse indication signals are generated; the oscillation clock is used as a clock input, and clock divide-by-eight signals related to rising edges and falling edges of the data input signals are generated under the control of the pulse indication signals; and carrying out operation processing based on the oscillation clock, the positive and negative phase two-way output signal and the clock eight-frequency division signal, wherein dead time of eight times of clock cycles is arranged between the output positive and negative signals. The invention realizes the adjustable and controllable dead zone delay time.
Description
Technical Field
The invention belongs to the technical field of semiconductor integrated circuits, and particularly relates to a dead time generation method and circuit with controllable delay time.
Background
The motor driver power driving tube generally adopts an NMOS-NMOS structure, and the grid electrodes of the NMOS are respectively driven by two signals with opposite phases. The power tube has larger grid capacitance due to the requirements of voltage resistance and the like, the larger parasitic capacitance can lead the power tube to have a longer charge-discharge process when being turned on or turned off, the process can lead the rising edge and the falling edge of two paths of signals with opposite phases to generate overlapped parts, one power tube is not completely turned off at the overlapped parts, but the other power tube is already turned on, the two power tubes are turned on simultaneously to form a low-resistance passage from a power supply to the ground, and the low-resistance passage can lead high current to flow through the power tube to burn.
To avoid this, a time difference needs to be introduced between the signal on states with opposite phases, and when one signal changes from high to low for a period of time, the other signal changes from low to high, and the introduced time is dead time.
Fig. 1 shows a conventional delay generating circuit, which is composed of two delay sub-modules and two and gates, and the two output signals have dead time. The delay unit adopts an RC structure formed by an inverter chain and a resistor and a capacitor, the delay time is determined by the delay of the inverter chain and an RC time constant, the dependence on the process is large, and meanwhile, the RC design cannot be changed after being determined, so that the delay time is fixed. Fig. 2 shows another conventional delay generating circuit, which is composed of two delay sub-modules, an and gate and an or gate, and the two output signals have dead time. The delay unit adopts an inverter chain structure, the delay time is determined by the delay of the inverter chain, the dependence on the process is large, and the delay time is fixed.
It is therefore desirable to provide a circuit that meets the functional requirements of delay time adjustability and controllability with little dependence on process manufacturing.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a dead time generation method and a dead time generation circuit with controllable delay time, and solves the problems that the delay time of the conventional delay generation circuit is fixed and the dependence on process manufacturing is large.
In order to achieve the above purpose, the present invention provides the following technical solutions: a dead time generation method with controllable delay time comprises the following steps:
generating an oscillation clock based on a resistor and capacitor network connected in series, and preprocessing the oscillation clock;
the oscillation clock is used as clock input and carries out buffer processing on the data input signal to generate a positive phase and an inverse phase output signal;
the oscillation clock and the preprocessed oscillation clock are used as clock inputs, rising edges and falling edges of data input signals are identified, and pulse indication signals are generated;
the oscillation clock is used as a clock input, and clock divide-by-eight signals related to rising edges and falling edges of the data input signals are generated under the control of the pulse indication signals;
and carrying out operation processing based on the oscillation clock, the positive and negative phase two-way output signal and the clock eight-frequency division signal, wherein dead time of eight times of clock cycles is arranged between the output positive and negative signals.
Further, the oscillating clock is used as a clock input, and the specific steps of generating clock divide-by-eight signals associated with rising edges and falling edges of the data input signal under the control of the pulse indication signal are as follows:
the oscillation clock is used as clock input, the pulse indication signal is used as reset input signal, frequency division control is carried out through the pulse indication signal, frequency division is carried out from the first rising edge and the falling edge of the data input signal, frequency division is carried out again on each subsequent rising edge and falling edge, and clock eight-division signals related to the rising edge and the falling edge of the data input signal are obtained.
Further, the oscillation clock is preprocessed by an inverter.
The invention also provides a circuit of the dead time generation method with controllable delay time, which comprises a clock generation module, an input preprocessing module, a delay mark generation module, an eight-frequency division clock generation module and a dead time delay generation module;
the clock generation module is used for generating an oscillation clock and a preprocessed oscillation clock by using a resistor and a capacitor which are connected in series;
the input preprocessing module is used for taking an oscillation clock as clock input and carrying out buffer processing on a data input signal to generate a positive phase and an inverse phase output signal;
the delay mark generation module is used for identifying rising edges and falling edges of data input signals and generating pulse indication signals by taking the oscillation clock and the preprocessed oscillation clock as clock inputs;
the clock-eighth frequency division clock generation module is used for taking an oscillation clock as clock input and generating clock-eighth frequency division signals related to rising edges and falling edges of the data input signals under the control of the pulse indication signals;
the dead time delay generation module is used for carrying out operation processing on the oscillation clock, the positive and negative phase two-way output signals and the clock eight-frequency division signal, and dead time of eight times of clock cycles is arranged between the positive and negative signals.
Further, the clock generation module includes a first resistor R1, a first capacitor C1, a first inverter INV1, a second inverter INV2, and a third inverter INV3;
one end of the first resistor R1 is connected with the input end of the first inverter INV1, the other end of the first resistor R1 is connected with the output end of the first inverter INV1, one end of the first capacitor C1 is connected with the input end of the first inverter INV1, and the other end of the first capacitor C1 is grounded; the input of the second inverter INV2 is connected with the output of the first inverter INV1, and the second inverter INV2 outputs a CLK signal; the input of the third inverter INV3 is connected to the output of the second inverter INV2, and the third inverter INV3 outputs the/CLK signal.
Further, the CLK signal can also be set through an RC network.
Further, the input preprocessing module comprises a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6 and a first trigger D1;
the data input end of the first trigger D1 is a global input DATAIN signal, the clock input end of the first trigger D1 is a CLK signal, the RESET input end of the first trigger D1 is a global RESET signal, the output end of the first trigger D1 is sequentially connected with a fifth inverter INV5 and a sixth inverter INV6, and the sixth inverter INV6 outputs a DATAIN_H signal; the output end of the first flip-flop D1 is also driven by the buffer of the fourth inverter INV4, and outputs datain_l signals, where datain_h and datain_l are mutually inverse signals.
Further, the delay identification generating module includes a seventh inverter INV7, an eighth inverter INV8, a second flip-flop D2, a third flip-flop D3, a first NAND gate NAND1, and a first OR gate OR1;
the data input end of the second trigger D2 is a DATAIN signal, the clock input end of the second trigger D2 is a CLK signal, the RESET input end of the second trigger D2 is a global RESET signal, the output end of the second trigger D2 is connected with the input end of the seventh inverter INV7, the input end of the eighth inverter INV8 and the data input end of the third trigger D3, the clock input end of the third trigger D3 is a/CLK signal, and the RESET input end of the third trigger D3 is a global RESET signal; the input of the first NAND gate NAND1 is connected with the output of the third trigger D3, the input of the first NAND gate NAND1 is also connected with the output of the eighth inverter INV8, the input of the first OR gate OR1 is respectively connected with the output of the seventh inverter INV7, the output of the first NAND gate NAND1 and the output of the third trigger D3, and the output of the first OR gate OR1 is a FLAG signal.
Further, the divide-by-eight clock generating module includes a ninth inverter INV9, a tenth inverter INV10, an eleventh inverter INV11, a fourth flip-flop D4, a fifth flip-flop D5, a sixth flip-flop D6, AND a first AND gate AND1;
the ninth inverter INV9 is connected in parallel to the fourth flip-flop D4, the tenth inverter INV10 is connected in parallel to the fifth flip-flop D5, the eleventh inverter INV11 is connected in parallel to the sixth flip-flop D6, the clock input terminals of the fourth flip-flop D4, the fifth flip-flop D5 AND the sixth flip-flop D6 are CLK signals, the reset input terminals of the fourth flip-flop D4, the fifth flip-flop D5 AND the sixth flip-flop D6 are FLAG signals, the inverted output of the fourth flip-flop D4, the inverted output of the fifth flip-flop D5 AND the inverted output of the sixth flip-flop D6 are used as the inputs of the first AND gate AND1, AND the first AND gate AND1 outputs 8CLK signals.
Further, the dead zone delay generating module includes a twelfth inverter INV12, a thirteenth inverter INV13, a fourteenth inverter INV14, a fifteenth inverter INV15, a seventh flip-flop D7, an eighth flip-flop D8, a second OR gate OR2, and a third OR gate OR3;
the data input end of the seventh trigger D7 is an output signal of the second OR gate OR2, the clock input end of the seventh trigger D7 is a CLK signal, and the reset input end of the seventh trigger D7 is a DATAIN_H signal; the data input end of the eighth trigger D8 is an output signal of the third OR gate OR3, the clock input end of the eighth trigger D8 is a CLK signal, and the reset input end of the eighth trigger D8 is a DATAIN_L signal; the inputs of the second OR gate OR2 are the output of the 8CLK signal and the seventh flip-flop D7, respectively; the input of the third OR gate OR3 is the output end of the 8CLK signal and the eighth flip-flop D8 respectively; the output of the seventh flip-flop D7 is buffer-driven by the twelfth and thirteenth inverters INV12 and INV13 to output the dataout_h signal, and the output of the eighth flip-flop D8 is buffer-driven by the fourteenth and fifteenth inverters INV14 and INV15 to output the dataout_l signal.
Compared with the prior art, the invention has at least the following beneficial effects:
the invention provides a dead time generation method with controllable delay time, which comprises the steps of manufacturing an oscillation clock, preprocessing the oscillation clock, taking the oscillation clock as clock input, and taking the oscillation clock and the preprocessed oscillation clock as clock input when generating pulse indication signals; in addition, buffer processing and rising edge and falling edge identification are respectively carried out on the data input signals so as to respectively generate positive and negative phase two paths of output signals and pulse indication signals, clock divide-by-eight signals related to the rising edge and the falling edge of the data input signals are generated through control of the pulse indication signals, operation processing is carried out according to an initial oscillation clock, the positive and negative phase two paths of output signals and the clock divide-by-eight signals, dead time of eight times of clock cycles is formed between the output positive and negative signals, the positive and negative signals are output to drive an up-down switch of the PWM converter, large current and power consumption caused by simultaneous opening of the up-down switch can be effectively avoided due to the existence of the dead time, meanwhile, the delay time of the dead time is eight times of the clock cycles and is only related to the oscillation clock cycles, and the clock cycles are determined by capacitance and resistance values which are externally connected in series and are irrelevant to a manufacturing process. Different resistor and capacitor values can generate oscillation clocks with different periods, namely different delay time can be generated, and the adjustable and controllable dead zone delay time is realized.
Further, frequency division control is performed through the pulse indication signal, frequency division is started from the first rising edge/falling edge of the data input signal, frequency division is performed again on each subsequent rising edge/falling edge, and clock eight-division signals associated with the rising edge and the falling edge of the data input signal are obtained, and the eight-division signals simultaneously comprise rising edge/falling edge information and eight-time clock information of the data input signal, so that dead zone delay time of eight-time clock cycles can be generated at the rising edge/falling edge of the subsequent data output signal.
The invention also provides a dead time generating circuit with controllable delay time, which is used for generating an oscillation clock through a clock generating module, generating positive and negative phase two paths of output signals through an input preprocessing module, identifying the rising edge and the falling edge of a data input signal through a delay identification generating module and generating pulse indication signals, wherein the eight-frequency-division clock generating module is used for generating clock eight-frequency-division signals related to the rising edge and the falling edge of the data input signal under the control of the pulse indication signals, and the dead time delay generating module is used for carrying out operation processing on the oscillation clock, the positive and negative phase two paths of output signals and the clock eight-frequency-division signals, and the dead time of eight times of clock cycles is between the positive and negative signals. The whole circuit structure takes a clock as a reference, the rising edge and the falling edge of the data input signal are identified through the special circuit structure, the eight-times frequency division signal related to the rising edge and the falling edge of the data input signal is generated, the rising edge and the falling edge of the data input signal can be precisely delayed, and finally the delay time is uniquely determined by the clock cycle. Because all signal processing in the whole circuit structure takes a clock as a reference, all signal changes take a clock rising edge as a reference, and finally the dead time generated is eight times of clock cycles, the delay time is only related to the clock cycles, and the whole circuit realizes the accurate and controllable dead time delay time.
Furthermore, the clock generation module adopts a general RC oscillation principle, and generates sawtooth waves at the output end of the Schmitt inverter INV1 by utilizing the high and low threshold values of the Schmitt inverter INV1 and the charging and discharging principle of RC, so that an oscillation clock CLK is generated at the output end of the INV 2. The module is characterized in that the clock frequency is determined by the charge and discharge time of RC, and different oscillation periods can be generated by setting different RC sizes.
Furthermore, the input preprocessing module performs buffer preprocessing on the input signal DATAIN to generate positive and negative phase two paths of output DATAIN_H and DATAIN_L, and the rising edges and the falling edges of the DATAIN_H and the DATAIN_L are aligned with the rising edge of the CLK under the action of the CLK signal, so that the operation processing of all signals is ensured to take a clock as a reference, and the accurate and controllable delay time is further ensured.
Further, the delay FLAG generation module can make the FLAG signal appear on rising and falling edges of the input data signal as a frequency division signal start FLAG. The method ensures that the subsequent frequency division starts from the rising edge/falling edge of the input signal, the second rising edge/falling edge restarts frequency division, and the frequency division signal starts from the high level, so that the basis for generating accurate frequency division by the subsequent eight-frequency division clock generation module is provided.
Further, the eight-frequency division clock generation module can enable the FLAG signal to carry out frequency division control, so that frequency division is started from the first rising edge/falling edge of the input signal, the second rising edge/falling edge and each subsequent rising edge/falling edge start to carry out frequency division again, a clock eight-frequency division signal associated with the rising edge and the falling edge of the data input signal is obtained, the eight-frequency division signal simultaneously comprises rising edge/falling edge information and eight-time clock information of the data input signal, and the dead zone delay generation module can carry out delay time of eight-time clock cycles on each rising edge of the data input signal.
Furthermore, the dead time delay generating module performs operation processing by using the original clock signal CLK, the clock eight-frequency division signal 8CLK, and the original input positive and negative phase two-way outputs datain_h and datain_l, so that the time when the output positive and negative signals dataout_h and dataout_l are simultaneously at the low level is eight times of the clock period (i.e., dead time). Since DATAIN_H is used as the reset signal of the D7 trigger, DATAOUT_H delays the high pulse rising edge of the DATAIN_H signal under the action of the CLK and 8CLK signals, while the falling edge remains unchanged; similarly, since datain_l is used as the reset signal for the D8 flip-flop, dataout_l delays the high pulse rising edge of datain_l signal under the action of CLK and 8CLK signals while the falling edge remains unchanged, thus creating dead time between dataout_h and dataout_l, which is the time of simultaneously low level.
Drawings
Fig. 1 is an equivalent circuit diagram of a conventional dead zone generating circuit;
FIG. 2 is an equivalent circuit diagram of a conventional dead zone generating circuit in another embodiment;
fig. 3 is an equivalent circuit diagram of the dead zone circuit of the present invention;
fig. 4 is a functional schematic diagram of the dead zone generating circuit of the present invention.
Detailed Description
The invention is further described below with reference to the drawings and the detailed description.
As shown in fig. 3, the present invention provides a dead time generation circuit with controllable delay time, comprising: the device comprises a clock generation module, an input preprocessing module, a delay identification generation module, an eight-frequency division clock generation module and a dead zone delay generation module. Wherein the method comprises the steps of
The clock generation module generates an oscillating clock through a configured resistor-capacitor network,
the input preprocessing module is used for carrying out buffer processing on an input signal to generate a positive output and a negative output;
the delay mark generation module mainly recognizes the rising edge/falling edge of an input signal and generates a pulse indication signal;
the clock divide-by-eight clock generation module generates a clock divide-by-eight signal related to the rising/falling edge of the input signal under the control of the pulse indication signal;
the dead time delay generating module utilizes the original clock signal, the clock eight-frequency dividing signal and the original input positive and negative phase output to carry out operation processing, so that the time for outputting the positive and negative signals to be at the low level simultaneously is eight times of clock period (namely dead time).
The positive and negative signal output is used for driving the upper switch and the lower switch of the PWM converter, and the existence of dead zones can effectively avoid large current and power consumption caused by the simultaneous opening of the upper switch and the lower switch.
In the present embodiment, the clock generation module includes a first resistor R1, a first capacitor C1, a first inverter INV1, a second inverter INV2, and a third inverter INV3;
one end of the first resistor R1 is connected with the input end of the first inverter INV1, the other end of the first resistor R1 is connected with the output end of the first inverter INV1, one end of the first capacitor C1 is connected with the input end of the first inverter INV1, and the other end of the first capacitor C1 is grounded; the input of the second inverter INV2 is connected with the output of the first inverter INV1, and the second inverter INV2 outputs a CLK signal; the input of the third inverter INV3 is connected to the output of the second inverter INV2, and the third inverter INV3 outputs the/CLK signal.
The input preprocessing module comprises a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6 and a first trigger D1;
the data input end of the first trigger D1 is a global input DATAIN signal, the clock input end of the first trigger D1 is a CLK signal, the RESET input end of the first trigger D1 is a global RESET signal, the output end of the first trigger D1 is sequentially connected with a fifth inverter INV5 and a sixth inverter INV6, and the sixth inverter INV6 outputs a DATAIN_H signal; the output end of the first flip-flop D1 is also driven by the buffer of the fourth inverter INV4, and outputs datain_l signals, where datain_h and datain_l are mutually inverse signals.
Specifically, the clock generation module in the invention adopts a general RC oscillation principle, and utilizes the high and low threshold values of the Schmidt inverter INV1 and the charge and discharge principle of RC to generate sawtooth waves at the output end of the Schmidt inverter INV1 so as to generate an oscillation clock CLK at the output end of INV 2. The frequency of the oscillation clock CLK is determined by the size of the resistor and capacitor. The input preprocessing module performs buffer preprocessing on an input signal DATAIN to generate positive and negative phase two-way outputs DATAIN_H and DATAIN_L, and rising edges and falling edges of the DATAIN_H and DATAIN_L are aligned with rising edges of CLK (clock signal) through the action of the CLK signal.
In the present embodiment, the delay flag generating module includes a seventh inverter INV7, an eighth inverter INV8, a second flip-flop D2, a third flip-flop D3, a first NAND gate NAND1, a first OR gate OR1. The data input end of the second trigger D2 is a DATAIN signal, the clock input end of the second trigger D2 is a CLK signal, the RESET input end of the second trigger D2 is a global RESET signal, the output end of the second trigger D2 is the input of the seventh inverter INV7, the input of the eighth inverter INV8 and the data input end of the third trigger D3, the clock input of the third trigger D3 is a/CLK signal, and the RESET input end of the third trigger D3 is a global RESET signal; one input of the first NAND gate NAND1 is the output of the third flip-flop D3, the other input is the output of the eighth inverter INV8, the three inputs of the first OR gate OR1 are the output of the seventh inverter INV7, the output of the first NAND gate NAND1 and the output of the third flip-flop D3, respectively, and the output of the first OR gate OR1 is the FLAG signal.
Specifically, the delay mark generation module mainly recognizes rising/falling edges of an input signal DATAIN and generates a pulse indication signal FLAG; the period of the FLAG signal is half of the period of the input signal DATAIN; the pulse width is half the CLK period. The FLAG signal appears on the rising and falling edges of the input data signal as a divide signal start FLAG. It is ensured that the subsequent frequency division starts from the rising edge of the input signal, the second rising edge resumes frequency division, and the divided signal starts from a high level.
In the present embodiment, the divide-by-eight clock generation block includes a ninth inverter INV9, a tenth inverter INV10, an eleventh inverter INV11, a fourth flip-flop D4, a fifth flip-flop D5, a sixth flip-flop D6, AND a first AND gate AND1. The fourth trigger D4 and the ninth inverter INV9 form a frequency division circuit, the fifth trigger D5 and the tenth inverter INV10 form a frequency division circuit, and the sixth trigger D6 and the eleventh inverter INV11 form a frequency division circuit; the clock input terminals of the fourth flip-flop D4, the fifth flip-flop D5 AND the sixth flip-flop D6 are CLK signals, the reset input terminals of the fourth flip-flop D4, the fifth flip-flop D5 AND the sixth flip-flop D6 are FLAG signals, the inverted output of the fourth flip-flop D4, the inverted output of the fifth flip-flop D5 AND the inverted output of the sixth flip-flop D6 are used as the inputs of the first AND gate AND1, AND the first AND gate AND1 outputs an 8CLK signal.
Specifically, the divide-by-eight clock generation module generates the divide-by-eight signal 8CLK related to the rising/falling edges of the input signal under the control of the pulse indication signal FLAG. The basic working principle is as follows: the CLK signal is divided by the D flip-flop into 2CLK, 4CLK and 8CLK, after which the 2CLK, 4CLK and 8CLK signals are and-operated to output a periodic signal with a pulse width of CLK and a pulse period of 8CLK. The FLAG signal performs frequency division control to ensure that frequency division starts from the first rising/falling edge of the input signal, and that frequency division starts again from the second and subsequent rising/falling edges.
In the present embodiment, the dead zone delay generation module includes a twelfth inverter INV12, a thirteenth inverter INV13, a fourteenth inverter INV14, a fifteenth inverter INV15, a seventh flip-flop D7, an eighth flip-flop D8, a second OR gate OR2, a third OR gate OR3. The data input end of the seventh trigger D7 is an output signal of the second OR gate OR2, the clock input end of the seventh trigger D7 is a CLK signal, and the reset input end of the seventh trigger D7 is a DATAIN_H signal; the data input end of the eighth trigger D8 is an output signal of the third OR gate OR3, the clock input end of the eighth trigger D8 is a CLK signal, and the reset input end of the eighth trigger D8 is a DATAIN_L signal; the inputs of the second OR gate OR2 are the output of the 8CLK signal and the seventh flip-flop D7, respectively; the input of the third OR gate OR3 is the output end of the 8CLK signal and the eighth flip-flop D8 respectively; the output of the seventh flip-flop D7 is buffer-driven by the twelfth and thirteenth inverters INV12 and INV13 to output the dataout_h signal, and the output of the eighth flip-flop D8 is buffer-driven by the fourteenth and fifteenth inverters INV14 and INV15 to output the dataout_l signal.
Specifically, the dead time delay generating module performs operation processing by using the original clock signal CLK, the clock divide by eight signal 8CLK, and the original input positive and negative phase two-way outputs datain_h and datain_l: after the first rising/falling edge of datain_h arrives, the 8CLK signal high pulse arrives after eight times of clock cycles, as input to the flip-flop D7, the output of the flip-flop D7 goes high following the 8CLK signal high pulse, since the 8CLK signal pulse width is CLK cycle, after which the 8CLK signal remains low, and due to the latch effect of OR gate OR2, the output of the flip-flop D7 remains high until datain_h resets the flip-flop D7, so that the rising edges of dataout_h and datain_h produce eight times of clock cycles of delay. Similarly, the rising edges of DATAOUT_L and DATAIN_L produce a delay of eight clock cycles; finally, the output positive and negative signals dataout_h and dataout_l are simultaneously low for eight clock cycles (i.e., dead time).
As shown in FIG. 4, DATAIN_H and DATAIN_L are the signals after DATAIN buffering, DATAIN_H and DATAIN_L are the opposite phase signals, that is, the rising edge of DATAIN_H is aligned with the falling edge of DATAIN_L, DATAIN_H and DATAIN_L are also the opposite phase signals after passing through the dead zone generating circuit of the present invention, but the rising edge of DATAOUT_L occurs after the falling edge of DATAOUT_H is delayed by eight times clock cycles, and the rising edge of DATAOUT_H occurs after the falling edge of DATAOUT_L is delayed by eight times clock cycles, and the time that DATAOUT_H and DATAOUT_L are at low level is eight times clock cycles (that is, dead zone time).
The whole circuit is input with DATAIN, the output DATAOUT_H and DATAOUT_L are positive and negative phase signals of the DATAIN after dead zone delay treatment, and the time (dead zone time) of the DATAOUT_H and DATAOUT_L at the same time being at a low level is eight times of clock cycles. The clock period in the invention can be set by an externally-matched RC network, so that the dead time delay time can be dynamically adjusted, and the application flexibility is greatly improved.
In another embodiment of the present invention, the present invention further provides a dead time generation method with controllable delay time, including the following steps: generating an oscillation clock based on a resistor and capacitor network connected in series, and preprocessing the oscillation clock;
the oscillation clock is used as clock input and carries out buffer processing on the data input signal to generate a positive phase and an inverse phase output signal;
the oscillation clock and the preprocessed oscillation clock are used as clock inputs, rising edges and falling edges of data input signals are identified, and pulse indication signals are generated;
the oscillation clock is used as a clock input, and clock divide-by-eight signals related to rising edges and falling edges of the data input signals are generated under the control of the pulse indication signals;
and carrying out operation processing based on the oscillation clock, the positive and negative phase two-way output signal and the clock eight-frequency division signal, wherein dead time of eight times of clock cycles is arranged between the output positive and negative signals.
Finally, it should be noted that: the above examples are only specific embodiments of the present invention, and are not intended to limit the scope of the present invention, but it should be understood by those skilled in the art that the present invention is not limited thereto, and that the present invention is described in detail with reference to the foregoing examples: any person skilled in the art may modify or easily conceive of the technical solution described in the foregoing embodiments, or perform equivalent substitution of some of the technical features, while remaining within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A dead time generation method with controllable delay time, comprising the steps of:
generating an oscillation clock based on a resistor and capacitor network connected in series, and preprocessing the oscillation clock;
the oscillation clock is used as clock input and carries out buffer processing on the data input signal to generate a positive phase and an inverse phase output signal;
the oscillation clock and the preprocessed oscillation clock are used as clock inputs, rising edges and falling edges of data input signals are identified, and pulse indication signals are generated;
the oscillation clock is used as a clock input, and clock divide-by-eight signals related to rising edges and falling edges of the data input signals are generated under the control of the pulse indication signals;
and carrying out operation processing based on the oscillation clock, the positive and negative phase two-way output signal and the clock eight-frequency division signal, wherein dead time of eight times of clock cycles is arranged between the output positive and negative signals.
2. The dead time generation method of claim 1 wherein the oscillating clock is used as a clock input and the clock divide by eight signal associated with the rising and falling edges of the data input signal is generated under the control of the pulse indication signal as follows:
the oscillation clock is used as clock input, the pulse indication signal is used as reset input signal, frequency division control is carried out through the pulse indication signal, frequency division is carried out from the first rising edge and the falling edge of the data input signal, frequency division is carried out again on each subsequent rising edge and falling edge, and clock eight-division signals related to the rising edge and the falling edge of the data input signal are obtained.
3. The dead time generation method of claim 1 wherein the oscillating clock is preprocessed by an inverter.
4. A circuit for implementing a dead time generation method with controllable delay time according to any one of claims 1 to 3, comprising a clock generation module, an input preprocessing module, a delay identification generation module, an divide-by-eight clock generation module and a dead time generation module;
the clock generation module is used for generating an oscillation clock and a preprocessed oscillation clock by using a resistor and a capacitor which are connected in series;
the input preprocessing module is used for taking an oscillation clock as clock input and carrying out buffer processing on a data input signal to generate a positive phase and an inverse phase output signal;
the delay mark generation module is used for identifying rising edges and falling edges of data input signals and generating pulse indication signals by taking the oscillation clock and the preprocessed oscillation clock as clock inputs;
the clock-eighth frequency division clock generation module is used for taking an oscillation clock as clock input and generating clock-eighth frequency division signals related to rising edges and falling edges of the data input signals under the control of the pulse indication signals;
the dead time delay generation module is used for carrying out operation processing on the oscillation clock, the positive and negative phase two-way output signals and the clock eight-frequency division signal, and dead time of eight times of clock cycles is arranged between the positive and negative signals.
5. The dead time generation circuit with controllable delay time of claim 4 wherein the clock generation module comprises a first resistor R1, a first capacitor C1, a first inverter INV1, a second inverter INV2 and a third inverter INV3;
one end of the first resistor R1 is connected with the input end of the first inverter INV1, the other end of the first resistor R1 is connected with the output end of the first inverter INV1, one end of the first capacitor C1 is connected with the input end of the first inverter INV1, and the other end of the first capacitor C1 is grounded; the input of the second inverter INV2 is connected with the output of the first inverter INV1, and the second inverter INV2 outputs a CLK signal; the input of the third inverter INV3 is connected to the output of the second inverter INV2, and the third inverter INV3 outputs the/CLK signal.
6. The delay time controllable dead time generating circuit of claim 5 wherein the CLK signal is further configurable via an RC network.
7. The dead time generation circuit with controllable delay time of claim 4 wherein the input preprocessing module comprises a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6 and a first flip-flop D1;
the data input end of the first trigger D1 is a global input DATAIN signal, the clock input end of the first trigger D1 is a CLK signal, the RESET input end of the first trigger D1 is a global RESET signal, the output end of the first trigger D1 is sequentially connected with a fifth inverter INV5 and a sixth inverter INV6, and the sixth inverter INV6 outputs a DATAIN_H signal; the output end of the first flip-flop D1 is also driven by the buffer of the fourth inverter INV4, and outputs datain_l signals, where datain_h and datain_l are mutually inverse signals.
8. The dead time generation circuit with controllable delay time according to claim 4, wherein the delay identification generation module comprises a seventh inverter INV7, an eighth inverter INV8, a second flip-flop D2, a third flip-flop D3, a first NAND gate NAND1 and a first OR gate OR1;
the data input end of the second trigger D2 is a DATAIN signal, the clock input end of the second trigger D2 is a CLK signal, the RESET input end of the second trigger D2 is a global RESET signal, the output end of the second trigger D2 is connected with the input end of the seventh inverter INV7, the input end of the eighth inverter INV8 and the data input end of the third trigger D3, the clock input end of the third trigger D3 is a/CLK signal, and the RESET input end of the third trigger D3 is a global RESET signal; the input of the first NAND gate NAND1 is connected with the output of the third trigger D3, the input of the first NAND gate NAND1 is also connected with the output of the eighth inverter INV8, the input of the first OR gate OR1 is respectively connected with the output of the seventh inverter INV7, the output of the first NAND gate NAND1 and the output of the third trigger D3, and the output of the first OR gate OR1 is a FLAG signal.
9. The dead time generation circuit with controllable delay time according to claim 4, wherein the divide-by-eight clock generation module comprises a ninth inverter INV9, a tenth inverter INV10, an eleventh inverter INV11, a fourth flip-flop D4, a fifth flip-flop D5, a sixth flip-flop D6, AND a first AND gate AND1;
the ninth inverter INV9 is connected in parallel to the fourth flip-flop D4, the tenth inverter INV10 is connected in parallel to the fifth flip-flop D5, the eleventh inverter INV11 is connected in parallel to the sixth flip-flop D6, the clock input terminals of the fourth flip-flop D4, the fifth flip-flop D5 AND the sixth flip-flop D6 are CLK signals, the reset input terminals of the fourth flip-flop D4, the fifth flip-flop D5 AND the sixth flip-flop D6 are FLAG signals, the inverted output of the fourth flip-flop D4, the inverted output of the fifth flip-flop D5 AND the inverted output of the sixth flip-flop D6 are used as the inputs of the first AND gate AND1, AND the first AND gate AND1 outputs 8CLK signals.
10. The dead time generation circuit with controllable delay time according to claim 4, wherein the dead time generation module comprises a twelfth inverter INV12, a thirteenth inverter INV13, a fourteenth inverter INV14, a fifteenth inverter INV15, a seventh flip-flop D7, an eighth flip-flop D8, a second OR gate OR2, and a third OR gate OR3;
the data input end of the seventh trigger D7 is an output signal of the second OR gate OR2, the clock input end of the seventh trigger D7 is a CLK signal, and the reset input end of the seventh trigger D7 is a DATAIN_H signal; the data input end of the eighth trigger D8 is an output signal of the third OR gate OR3, the clock input end of the eighth trigger D8 is a CLK signal, and the reset input end of the eighth trigger D8 is a DATAIN_L signal; the inputs of the second OR gate OR2 are the output of the 8CLK signal and the seventh flip-flop D7, respectively; the input of the third OR gate OR3 is the output end of the 8CLK signal and the eighth flip-flop D8 respectively; the output of the seventh flip-flop D7 is buffer-driven by the twelfth and thirteenth inverters INV12 and INV13 to output the dataout_h signal, and the output of the eighth flip-flop D8 is buffer-driven by the fourteenth and fifteenth inverters INV14 and INV15 to output the dataout_l signal.
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| CN114978127B (en) * | 2022-06-13 | 2023-04-07 | 湖南毂梁微电子有限公司 | High-precision PWM dead zone control circuit and PWM control system |
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