CN113328732A - Dead time generation method and circuit with controllable delay time - Google Patents

Abstract

The invention discloses a dead time generation method with controllable delay time and a circuit thereof, comprising the following steps: generating an oscillation clock based on the serially connected resistor and capacitor network, and preprocessing the oscillation clock; an oscillation clock is used as clock input and carries out buffer processing on a data input signal to generate two paths of positive and negative output signals; the oscillation clock and the preprocessed oscillation clock are used as clock input, the rising edge and the falling edge of the data input signal are identified, and a pulse indication signal is generated; an oscillating clock is used as a clock input, and a clock octant division signal related to the rising edge and the falling edge of the data input signal is generated under the control of a pulse indication signal; the operation processing is carried out based on the oscillation clock, the positive and negative output signals and the clock octant frequency division signal, and the dead time of eight times of clock period is formed between the output positive and negative signals. The invention realizes the adjustability and controllability of dead zone delay time.

Description

Dead time generation method and circuit with controllable delay time

Technical Field

The invention belongs to the technical field of semiconductor integrated circuits, and particularly belongs to a dead time generation method and circuit with controllable delay time.

Background

The power driving tube of the motor driver generally adopts an NMOS-NMOS structure, and the grid electrodes of the NMOS are respectively driven by two signals with opposite phases. The power tube can have a larger gate capacitance due to requirements such as voltage resistance, the larger parasitic capacitance can enable the power tube to have a longer charging and discharging process when the power tube is started or turned off, the process can lead the rising and falling edges of two paths of signals with opposite phases to form an overlapping part, one power tube is not completely turned off in the overlapping part, but the other power tube is already started, the two power tubes are simultaneously started to form a low-resistance path from a power supply to the ground, and the low-resistance path can cause large current to flow through the power tube, so that the power tube is burnt.

In order to avoid this situation, a time difference needs to be introduced between the on states of the signals with opposite phases, when one path of signal changes from high to low for a period of time, the other path of signal changes from low to high, and the introduced time is the dead time.

Fig. 1 shows a conventional delay generating circuit, which is composed of two delay submodules and two and gates, and outputs two signals with dead time. The delay unit adopts an RC structure consisting of an inverter chain and a resistor capacitor, the delay time is determined by the delay of the inverter chain and an RC time constant, the dependence on the process is large, and the RC design cannot be changed after being determined, so the delay time is fixed. Fig. 2 shows another conventional delay generating circuit, which is composed of two delay submodules, an and gate and an or gate, and two output signals have dead time. The delay unit adopts an inverter chain structure, the delay time is determined by the delay of the inverter chain, the dependence on the process is large, and the delay time is fixed.

It is therefore desirable to provide a circuit that meets the functional requirements of adjustable and controllable delay times and minimal process manufacturing dependence.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides a dead time generation method and a dead time generation circuit with controllable delay time, and solves the problems that the delay time of the existing delay generation circuit is fixed and the dependence on process manufacturing is large.

In order to achieve the purpose, the invention provides the following technical scheme: a dead time generation method with controllable delay time comprises the following steps:

generating an oscillation clock based on the serially connected resistor and capacitor network, and preprocessing the oscillation clock;

an oscillation clock is used as clock input and carries out buffer processing on a data input signal to generate two paths of positive and negative output signals;

the oscillation clock and the preprocessed oscillation clock are used as clock input, the rising edge and the falling edge of the data input signal are identified, and a pulse indication signal is generated;

an oscillating clock is used as a clock input, and a clock octant division signal related to the rising edge and the falling edge of the data input signal is generated under the control of a pulse indication signal;

the operation processing is carried out based on the oscillation clock, the positive and negative output signals and the clock octant frequency division signal, and the dead time of eight times of clock period is formed between the output positive and negative signals.

Further, the oscillating clock is used as a clock input, and the specific steps of generating the clock octant division signal associated with the rising edge and the falling edge of the data input signal under the control of the pulse indication signal are as follows:

the oscillation clock is used as clock input, the pulse indication signal is used as a reset input signal, and frequency division control is carried out through the pulse indication signal, so that frequency division is carried out from the first rising edge and the first falling edge of the data input signal and is carried out again at each subsequent rising edge and each subsequent falling edge, and the clock eight-frequency division signal related to the rising edge and the falling edge of the data input signal is obtained.

Further, the oscillation clock is preprocessed through an inverter.

The invention also provides a circuit of the dead time generation method with controllable delay time, which comprises a clock generation module, an input preprocessing module, a delay identification generation module, an eight-frequency division clock generation module and a dead time delay generation module;

the clock generation module is used for generating an oscillation clock and a preprocessed oscillation clock by using a resistor and a capacitor which are connected in series;

the input preprocessing module is used for taking an oscillating clock as clock input and carrying out buffering processing on a data input signal to generate two paths of positive and negative output signals;

the delay identification generation module is used for taking an oscillation clock and the preprocessed oscillation clock as clock inputs, identifying the rising edge and the falling edge of a data input signal and generating a pulse indication signal;

the eight-frequency division clock generation module is used for taking an oscillating clock as a clock input and generating a clock eight-frequency division signal related to a rising edge and a falling edge of a data input signal under the control of a pulse indication signal;

the dead time delay generation module is used for carrying out operation processing by using an oscillation clock, positive and negative phase two-path output signals and a clock octant frequency division signal, and the dead time of eight times of clock period is between the output positive and negative signals.

Further, the clock generation module comprises a first resistor R1, a first capacitor C1, a first inverter INV1, a second inverter INV2 and a third inverter INV 3;

one end of the first resistor R1 is connected to an input end of the first inverter INV1, the other end of the first resistor R1 is connected to an output end of the first inverter INV1, one end of the first capacitor C1 is connected to an input of the first inverter INV1, and the other end of the first capacitor C1 is grounded; the input of the second inverter INV2 is connected to the output of the first inverter INV1, and the second inverter INV2 outputs the CLK signal; the input of the third inverter INV3 is connected to the output of the second inverter INV2, and the third inverter INV3 outputs/CLK signal.

Further, the CLK signal can also be set through an RC network.

Further, the input preprocessing module includes a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, and a first flip-flop D1;

the data input end of the first flip-flop D1 is a global input DATAIN signal, the clock input end of the first flip-flop D1 is a CLK signal, the RESET input end of the first flip-flop D1 is a global RESET signal, the output end of the first flip-flop D1 is sequentially connected with a fifth inverter INV5 and a sixth inverter INV6, and the sixth inverter INV6 outputs a DATAIN _ H signal; the output terminal of the first flip-flop D1 is also buffer-driven by the fourth inverter INV4, and outputs DATAIN _ L signal, where DATAIN _ H and DATAIN _ L are inverse signals to each other.

Further, the delay flag generating module includes a seventh inverter INV7, an eighth inverter INV8, a second flip-flop D2, a third flip-flop D3, a first NAND gate NAND1, and a first OR 1;

the data input end of the second flip-flop D2 is a DATAIN signal, the clock input end of the second flip-flop D2 is a CLK signal, the RESET input end of the second flip-flop D2 is a global RESET signal, the output end of the second flip-flop D2 is connected with the input of the seventh inverter INV7, the input of the eighth inverter INV8 and the data input end of the third flip-flop D3, the clock input of the third flip-flop D3 is a/CLK signal, and the RESET input end of the third flip-flop D3 is the global RESET signal; the input of the first NAND gate NAND1 is connected to the output of the third flip-flop D3, the input of the first NAND gate NAND1 is further connected to the output of the eighth inverter INV8, the input of the first OR gate OR1 is connected to the output of the seventh inverter INV7, the output of the first NAND gate NAND1 and the output of the third flip-flop D3, respectively, and the output of the first OR gate OR1 is a FLAG signal.

Further, the eight-divided clock generation module includes a ninth inverter INV9, a tenth inverter INV10, an eleventh inverter INV11, a fourth flip-flop D4, a fifth flip-flop D5, a sixth flip-flop D6, AND a first AND gate AND 1;

the ninth inverter INV9 is connected in parallel to the fourth flip-flop D4, the tenth inverter INV10 is connected in parallel to the fifth flip-flop D5, the eleventh inverter INV11 is connected in parallel to the sixth flip-flop D6, the clock input terminals of the fourth flip-flop D4, the fifth flip-flop D5 AND the sixth flip-flop D6 are CLK signals, the reset input terminals of the fourth flip-flop D4, the fifth flip-flop D5 AND the sixth flip-flop D6 are FLAG signals, the inverted output of the fourth flip-flop D4, the inverted output of the fifth flip-flop D5 AND the inverted output of the sixth flip-flop D6 are input to the first AND gate 1, AND the first AND gate 1 outputs 8CLK signals.

Further, the dead time delay generation module includes a twelfth inverter INV12, a thirteenth inverter INV13, a fourteenth inverter INV14, a fifteenth inverter INV15, a seventh flip-flop D7, an eighth flip-flop D8, a second OR gate OR2, and a third OR gate OR 3;

the data input end of the seventh flip-flop D7 is the output signal of the second OR gate OR2, the clock input end of the seventh flip-flop D7 is the CLK signal, and the reset input end of the seventh flip-flop D7 is the DATAIN _ H signal; the data input terminal of the eighth flip-flop D8 is the output signal of the third OR gate OR3, the clock input terminal of the eighth flip-flop D8 is the CLK signal, and the reset input terminal of the eighth flip-flop D8 is the DATAIN _ L signal; the inputs of the second OR gate OR2 are the 8CLK signal and the output of the seventh flip-flop D7, respectively; the inputs of the third OR gate OR3 are the 8CLK signal and the output of the eighth flip-flop D8, respectively; the output of the seventh flip-flop D7 is buffer-driven by the twelfth inverter INV12 and the thirteenth inverter INV13 to output a DATAOUT _ H signal, and the output of the eighth flip-flop D8 is buffer-driven by the fourteenth inverter INV14 and the fifteenth inverter INV15 to output a DATAOUT _ L signal.

Compared with the prior art, the invention has at least the following beneficial effects:

the invention provides a dead time generation method with controllable delay time, which is characterized in that an oscillation clock is manufactured, is preprocessed and is used as a clock input, and the oscillation clock and the preprocessed oscillation clock are used as clock inputs when a pulse indication signal is generated; in addition, the data input signal is respectively buffered and identified by the rising edge and the falling edge so as to respectively generate two paths of positive and negative output signals and pulse indication signals, a clock divide-by-eight signal associated with the rising and falling edges of the data input signal is generated by control of the pulse indication signal, then, operation processing is carried out according to the initial oscillation clock, the positive and negative output signals and the clock octant frequency division signal, so that the dead time of eight times clock period is formed between the output positive and negative signals, the positive and negative signals are output to drive an upper switch and a lower switch of the PWM converter, the dead time can effectively avoid large current and power consumption caused by the simultaneous opening of the upper switch and the lower switch, meanwhile, the delay time of the dead zone is eight times of the clock period, which is only related to the oscillation clock period, and the clock period is determined by the external series-connected capacitor and resistance value and is unrelated to the manufacturing process. Different resistance and capacitance values can generate oscillation clocks with different periods, so that different delay times can be generated, and the dead zone delay time can be adjusted and controlled.

Furthermore, frequency division control is carried out through the pulse indication signal, so that frequency division is started from the first rising edge/falling edge of the data input signal, and frequency division is carried out again on each subsequent rising edge/falling edge, and a clock eight-frequency division signal related to the rising edge and the falling edge of the data input signal is obtained, wherein the eight-frequency division signal simultaneously contains the rising edge/falling edge information and the eight-time clock information of the data input signal, and the dead zone delay time of eight-time clock periods can be generated at the rising edge/falling edge of the subsequent data output signal.

The invention also provides a dead time generating circuit with controllable delay time, which generates an oscillating clock through a clock generating module, an input preprocessing module generates positive and negative phase output signals, a delay identification generating module identifies the rising edge and the falling edge of a data input signal and generates a pulse indicating signal, an octant frequency division clock generating module generates a clock octant frequency division signal related to the rising edge and the falling edge of the data input signal under the control of the pulse indicating signal, the dead time delay generating module is used for carrying out operation processing on the oscillating clock, the positive and negative phase output signals and the clock octant frequency division signal, and the dead time of eight times of the clock period is formed between the output positive and negative signals. The whole circuit structure takes a clock as reference, the rising edge and the falling edge of the data input signal are identified through a special circuit structure, and the octave frequency division signal related to the rising edge and the falling edge of the data input signal is generated, so that the rising edge and the falling edge of the data input signal can be accurately delayed, and finally the delay time is uniquely determined by the clock period. Because all signal processing in the whole circuit structure takes the clock as reference, all signal changes take the clock rising edge as reference, the finally generated dead time is eight times of clock period, the delay time is only related to the clock period, and the whole circuit realizes the accurate control of the dead time.

Furthermore, the clock generation module generates a sawtooth wave at the output end of the schmitt inverter INV1 by using a general RC oscillation principle, a high-low threshold of the schmitt inverter INV1 and a charging and discharging principle of the RC, so as to generate the oscillation clock CLK at the output end of the INV 2. The module is characterized in that the clock frequency is determined by the charging and discharging time of the RC, and different oscillation periods can be generated by setting different RC sizes.

Furthermore, the input preprocessing module performs buffering preprocessing on the input signal DATAIN to generate positive and negative output DATAIN _ H and DATAIN _ L, and through the action of the CLK signal, the rising edge and the falling edge of the DATAIN _ H and the DATAIN _ L are aligned with the rising edge of the CLK, so that the operation processing of all signals is ensured to be carried out by taking the clock as reference, and the accuracy and the controllability of the delay time are further ensured.

Furthermore, the delay mark generation module can enable the FLAG signal to appear on the rising edge and the falling edge of the input data signal to be used as a frequency division signal start mark. Ensuring that the subsequent frequency division starts from the rising edge/falling edge of the input signal, the second rising edge/falling edge restarts the frequency division, and the frequency division signal starts from the high level is the basis for the subsequent eight-division clock generation module to generate the accurate frequency division.

Furthermore, the frequency division control of the FLAG signal can be performed by the frequency division eight clock generation module, so that the frequency division is performed from the first rising edge/falling edge of the input signal, and the frequency division is performed again from the second and subsequent rising edges/falling edges, so as to obtain the clock frequency division eight signal associated with the rising edge and the falling edge of the data input signal, wherein the frequency division eight signal simultaneously contains the rising edge/falling edge information and the eight-time clock information of the data input signal, and the dead zone delay generation module can perform the delay time of eight clock periods on each rising edge of the data input signal.

Further, the dead time delay generating module performs operation processing by using the original clock signal CLK, the clock octant signal 8CLK, and the originally input positive and negative output DATAIN _ H and DATAIN _ L, so that the time that the output positive and negative signals DATAOUT _ H and DATAOUT _ L are simultaneously at the low level is eight times the clock period (i.e., dead time). Because DATAIN _ H is used as the reset signal of the D7 flip-flop, DATAOUT _ H delays the high pulse rising edge of the DATAIN _ H signal under the action of the CLK and 8CLK signals, while the falling edge remains unchanged; similarly, because DATAIN _ L is used as the reset signal of the D8 flip-flop, DATAOUT _ L delays the rising edge of the high pulse of DATAIN _ L signal under the CLK and 8CLK signals while the falling edge remains unchanged, thus generating a dead time between DATAOUT _ H and DATAOUT _ L, which is a time period that is low at the same time.

Drawings

Fig. 1 is an equivalent circuit diagram of a conventional dead zone generating circuit;

fig. 2 is an equivalent circuit diagram of a conventional dead zone generating circuit in another embodiment;

FIG. 3 is an equivalent circuit diagram of the dead band circuit of the present invention;

fig. 4 is a functional schematic diagram of a dead band generation circuit of the present invention.

Detailed Description

The invention is further described with reference to the following figures and detailed description.

As shown in fig. 3, the present invention provides a dead time generation circuit with controllable delay time, including: the clock generating module, the input preprocessing module, the delay identification generating module, the frequency division eight clock generating module and the dead zone delay generating module. Wherein

The clock generation module generates an oscillating clock through a configured resistor-capacitor network,

the input preprocessing module carries out buffering processing on an input signal to generate positive and negative phase outputs;

the delay identification generation module is mainly used for identifying the rising edge/the falling edge of an input signal and generating a pulse indication signal;

the eight-frequency division clock generation module generates a clock eight-frequency division signal related to the rising edge/falling edge of the input signal under the control of the pulse indication signal;

the dead time delay generation module utilizes the original clock signal, the clock octave division signal and the original input positive and negative phase two-path output to carry out operation processing, so that the time for outputting the positive and negative signals and simultaneously being at a low level is eight times of the clock period (namely dead time).

Positive and negative signal output is used for driving the upper and lower switches of the PWM converter, and the existence of the dead zone can effectively avoid the large current and the power consumption caused by the simultaneous opening of the upper and lower switches.

In this embodiment, the clock generating module includes a first resistor R1, a first capacitor C1, a first inverter INV1, a second inverter INV2, and a third inverter INV 3;

one end of the first resistor R1 is connected to an input end of the first inverter INV1, the other end of the first resistor R1 is connected to an output end of the first inverter INV1, one end of the first capacitor C1 is connected to an input of the first inverter INV1, and the other end of the first capacitor C1 is grounded; the input of the second inverter INV2 is connected to the output of the first inverter INV1, and the second inverter INV2 outputs the CLK signal; the input of the third inverter INV3 is connected to the output of the second inverter INV2, and the third inverter INV3 outputs/CLK signal.

The input preprocessing module includes a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, and a first flip-flop D1;

the data input end of the first flip-flop D1 is a global input DATAIN signal, the clock input end of the first flip-flop D1 is a CLK signal, the RESET input end of the first flip-flop D1 is a global RESET signal, the output end of the first flip-flop D1 is sequentially connected with a fifth inverter INV5 and a sixth inverter INV6, and the sixth inverter INV6 outputs a DATAIN _ H signal; the output terminal of the first flip-flop D1 is also buffer-driven by the fourth inverter INV4, and outputs DATAIN _ L signal, where DATAIN _ H and DATAIN _ L are inverse signals to each other.

Specifically, the clock generation module in the invention adopts a general RC oscillation principle, and utilizes the high-low threshold of the Schmitt inverter INV1 and the charging and discharging principle of RC to generate a sawtooth wave at the output end of the Schmitt inverter INV1, so as to generate the oscillation clock CLK at the output end of INV 2. The frequency of the oscillating clock CLK is determined by the size of the resistor-capacitor. The input preprocessing module carries out buffering preprocessing on an input signal DATAIN to generate positive and negative phase two paths of outputs DATAIN _ H and DATAIN _ L, and the rising edge and the falling edge of DATAIN _ H and DATAIN _ L are aligned with the rising edge of CLK under the action of the CLK signal.

In this embodiment, the delay flag generating module includes a seventh inverter INV7, an eighth inverter INV8, a second flip-flop D2, a third flip-flop D3, a first NAND gate NAND1, and a first OR 1. Wherein the data input terminal of the second flip-flop D2 is a DATAIN signal, the clock input terminal of the second flip-flop D2 is a CLK signal, the RESET input terminal of the second flip-flop D2 is a global RESET signal, the output terminal of the second flip-flop D2 is the input of the seventh inverter INV7, the input of the eighth inverter INV8 and the data input terminal of the third flip-flop D3, the clock input of the third flip-flop D3 is a/CLK signal, and the RESET input terminal of the third flip-flop D3 is the global RESET signal; one input of the first NAND gate NAND1 is an output of the third flip-flop D3, the other input is an output of the eighth inverter INV8, three inputs of the first OR gate OR1 are an output of the seventh inverter INV7, an output of the first NAND gate NAND1, and an output of the third flip-flop D3, respectively, and an output of the first OR gate OR1 is a FLAG signal.

Specifically, the delay identifier generation module mainly identifies rising/falling edges of the input signal DATAIN and generates a pulse indication signal FLAG; the period of the FLAG signal is half of the period of the input signal DATAIN; the pulse width is half the period of CLK. The FLAG signal appears on the rising and falling edges of the input data signal as a start FLAG of the frequency division signal. It is ensured that the subsequent division starts with a rising edge of the input signal, the second rising edge restarts the division, and the divided signal starts with a high level.

In this embodiment, the eight-divided clock generating module includes a ninth inverter INV9, a tenth inverter INV10, an eleventh inverter INV11, a fourth flip-flop D4, a fifth flip-flop D5, a sixth flip-flop D6, AND a first AND gate AND 1. The fourth flip-flop D4 and the ninth inverter INV9 form a frequency-halving circuit, the fifth flip-flop D5 and the tenth inverter INV10 form a frequency-halving circuit, and the sixth flip-flop D6 and the eleventh inverter INV11 form a frequency-halving circuit; the clock input ends of the fourth flip-flop D4, the fifth flip-flop D5 AND the sixth flip-flop D6 are CLK signals, the reset input ends of the fourth flip-flop D4, the fifth flip-flop D5 AND the sixth flip-flop D6 are FLAG signals, the inverted output of the fourth flip-flop D4, the inverted output of the fifth flip-flop D5 AND the inverted output of the sixth flip-flop D6 are used as the input of the first AND gate 1, AND the first AND gate AND1 outputs 8CLK signals.

Specifically, the divided-by-eight clock generation module generates a divided-by-eight signal 8CLK associated with the rising/falling edge of the input signal under the control of the pulse indication signal FLAG. The basic working principle is as follows: the CLK signal is divided into 2CLK, 4CLK and 8CLK by the D flip-flop, and then the 2CLK, 4CLK and 8CLK signals are AND-operated to output a periodic signal with the pulse width of CLK and the pulse period of 8 CLK. The FLAG signal performs frequency division control to ensure that the frequency division starts from the first rising edge/falling edge of the input signal and the second and each subsequent rising edge/falling edge starts to divide again.

In this embodiment, the dead time delay generation module includes a twelfth inverter INV12, a thirteenth inverter INV13, a fourteenth inverter INV14, a fifteenth inverter INV15, a seventh flip-flop D7, an eighth flip-flop D8, a second OR gate OR2, and a third OR gate OR 3. Wherein the data input terminal of the seventh flip-flop D7 is the output signal of the second OR gate OR2, the clock input terminal of the seventh flip-flop D7 is the CLK signal, and the reset input terminal of the seventh flip-flop D7 is the DATAIN _ H signal; wherein the data input terminal of the eighth flip-flop D8 is the output signal of the third OR gate OR3, the clock input terminal of the eighth flip-flop D8 is the CLK signal, and the reset input terminal of the eighth flip-flop D8 is the DATAIN _ L signal; the inputs of the second OR gate OR2 are the 8CLK signal and the output of the seventh flip-flop D7, respectively; the inputs of the third OR gate OR3 are the 8CLK signal and the output of the eighth flip-flop D8, respectively; the output of the seventh flip-flop D7 is buffer-driven by the twelfth inverter INV12 and the thirteenth inverter INV13 to output a DATAOUT _ H signal, and the output of the eighth flip-flop D8 is buffer-driven by the fourteenth inverter INV14 and the fifteenth inverter INV15 to output a DATAOUT _ L signal.

Specifically, the dead time delay generation module performs operation processing by using an original clock signal CLK, a clock octant signal 8CLK, and an original input positive and negative phase two-way output DATAIN _ H and DATAIN _ L: after the first rising/falling edge of DATAIN _ H arrives, eight clock cycles are passed, the 8CLK signal high pulse arrives as the input of the flip-flop D7, the output of the flip-flop D7 goes high following the 8CLK signal high pulse, after which the 8CLK signal keeps low because the 8CLK signal pulse width is CLK cycle, the output of the flip-flop D7 keeps high because of the latching action of the OR gate OR2, until the DATAIN _ H resets the flip-flop D7, therefore, the rising edges of DATAOUT _ H and DATAIN _ H generate eight clock cycles of delay. Similarly, rising edges of DATAOUT _ L and DATAIN _ L generate eight times of clock period delay; the time for the output positive and negative signals DATAOUT _ H and DATAOUT _ L to be simultaneously low is eight clock cycles (i.e., dead time).

As shown in fig. 4, DATAIN _ H and DATAIN _ L are signals after DATAIN buffering, DATAIN _ H and DATAIN _ L are inverse signals, that is, the rising edge of DATAIN _ H is aligned with the falling edge of DATAIN _ L, and the falling edge of DATAIN _ H is aligned with the rising edge of DATAIN _ L, after passing through the dead zone generating circuit of the present invention, DATAOUT _ H and DATAOUT _ L are also inverse signals, but the falling edge of DATAOUT _ H is delayed by eight clock cycles, the rising edge of DATAOUT _ L occurs, and the falling edge of DATAOUT _ L is delayed by eight clock cycles, the rising edge of DATAOUT _ H occurs, and the time that DATAOUT _ H and DATAOUT _ L are both low is eight clock cycles (i.e., dead zone time).

The input of the whole circuit is DATAIN, the outputs DATAOUT _ H and DATAOUT _ L are positive and negative phase signals of DATAIN after dead time delay processing, and the time (dead time) that DATAOUT _ H and DATAOUT _ L are simultaneously low level is eight times of clock period. The clock period in the invention can be set by an externally-arranged RC network, so that the dead zone delay time can be dynamically adjusted, and the application flexibility is greatly improved.

In another embodiment of the present invention, the present invention further provides a dead time generation method with controllable delay time, including the following steps: generating an oscillation clock based on the serially connected resistor and capacitor network, and preprocessing the oscillation clock;

an oscillation clock is used as clock input and carries out buffer processing on a data input signal to generate two paths of positive and negative output signals;

the oscillation clock and the preprocessed oscillation clock are used as clock input, the rising edge and the falling edge of the data input signal are identified, and a pulse indication signal is generated;

an oscillating clock is used as a clock input, and a clock octant division signal related to the rising edge and the falling edge of the data input signal is generated under the control of a pulse indication signal;

the operation processing is carried out based on the oscillation clock, the positive and negative output signals and the clock octant frequency division signal, and the dead time of eight times of clock period is formed between the output positive and negative signals.

Finally, it should be noted that: the above-mentioned embodiments are only specific embodiments of the present invention, which are used for illustrating the technical solutions of the present invention and not for limiting the same, and the protection scope of the present invention is not limited thereto, although the present invention is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: any person skilled in the art can modify or easily conceive the technical solutions described in the foregoing embodiments or equivalent substitutes for some technical features within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the embodiments of the present invention, and they should be construed as being included therein. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (10)

1. A dead time generation method with controllable delay time is characterized by comprising the following steps:

generating an oscillation clock based on the serially connected resistor and capacitor network, and preprocessing the oscillation clock;

an oscillation clock is used as clock input and carries out buffer processing on a data input signal to generate two paths of positive and negative output signals;

the oscillation clock and the preprocessed oscillation clock are used as clock input, the rising edge and the falling edge of the data input signal are identified, and a pulse indication signal is generated;

an oscillating clock is used as a clock input, and a clock octant division signal related to the rising edge and the falling edge of the data input signal is generated under the control of a pulse indication signal;

the operation processing is carried out based on the oscillation clock, the positive and negative output signals and the clock octant frequency division signal, and the dead time of eight times of clock period is formed between the output positive and negative signals.

2. The method of claim 1, wherein the oscillating clock is used as a clock input, and the step of generating the clock octant signal associated with the rising edge and the falling edge of the data input signal under the control of the pulse indication signal comprises the following steps:

the oscillation clock is used as clock input, the pulse indication signal is used as a reset input signal, and frequency division control is carried out through the pulse indication signal, so that frequency division is carried out from the first rising edge and the first falling edge of the data input signal and is carried out again at each subsequent rising edge and each subsequent falling edge, and the clock eight-frequency division signal related to the rising edge and the falling edge of the data input signal is obtained.

3. The method of claim 1, wherein the oscillating clock is pre-conditioned by an inverter.

4. The circuit for realizing the dead time generation method with controllable delay time of any one of claims 1 to 3, is characterized by comprising a clock generation module, an input preprocessing module, a delay identification generation module, an octant clock generation module and a dead time generation module;

the clock generation module is used for generating an oscillation clock and a preprocessed oscillation clock by using a resistor and a capacitor which are connected in series;

the input preprocessing module is used for taking an oscillating clock as clock input and carrying out buffering processing on a data input signal to generate two paths of positive and negative output signals;

the delay identification generation module is used for taking an oscillation clock and the preprocessed oscillation clock as clock inputs, identifying the rising edge and the falling edge of a data input signal and generating a pulse indication signal;

the eight-frequency division clock generation module is used for taking an oscillating clock as a clock input and generating a clock eight-frequency division signal related to a rising edge and a falling edge of a data input signal under the control of a pulse indication signal;

the dead time delay generation module is used for carrying out operation processing by using an oscillation clock, positive and negative phase two-path output signals and a clock octant frequency division signal, and the dead time of eight times of clock period is between the output positive and negative signals.

5. The dead time generation circuit with controllable delay time of claim 4, wherein the clock generation module comprises a first resistor R1, a first capacitor C1, a first inverter INV1, a second inverter INV2 and a third inverter INV 3;

one end of the first resistor R1 is connected to an input end of the first inverter INV1, the other end of the first resistor R1 is connected to an output end of the first inverter INV1, one end of the first capacitor C1 is connected to an input of the first inverter INV1, and the other end of the first capacitor C1 is grounded; the input of the second inverter INV2 is connected to the output of the first inverter INV1, and the second inverter INV2 outputs the CLK signal; the input of the third inverter INV3 is connected to the output of the second inverter INV2, and the third inverter INV3 outputs/CLK signal.

6. A delay time controllable dead time generating circuit as claimed in claim 5 wherein said CLK signal is further configurable via an RC network.

7. The controllable delay time dead time generating circuit of claim 4, wherein said input preprocessing module comprises a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6 and a first flip-flop D1;

the data input end of the first flip-flop D1 is a global input DATAIN signal, the clock input end of the first flip-flop D1 is a CLK signal, the RESET input end of the first flip-flop D1 is a global RESET signal, the output end of the first flip-flop D1 is sequentially connected with a fifth inverter INV5 and a sixth inverter INV6, and the sixth inverter INV6 outputs a DATAIN _ H signal; the output terminal of the first flip-flop D1 is also buffer-driven by the fourth inverter INV4, and outputs DATAIN _ L signal, where DATAIN _ H and DATAIN _ L are inverse signals to each other.

8. The controllable delay time dead time generating circuit of claim 4, wherein said delay flag generating module comprises a seventh inverter INV7, an eighth inverter INV8, a second flip-flop D2, a third flip-flop D3, a first NAND gate NAND1 and a first OR gate OR 1;

the data input end of the second flip-flop D2 is a DATAIN signal, the clock input end of the second flip-flop D2 is a CLK signal, the RESET input end of the second flip-flop D2 is a global RESET signal, the output end of the second flip-flop D2 is connected with the input of the seventh inverter INV7, the input of the eighth inverter INV8 and the data input end of the third flip-flop D3, the clock input of the third flip-flop D3 is a/CLK signal, and the RESET input end of the third flip-flop D3 is the global RESET signal; the input of the first NAND gate NAND1 is connected to the output of the third flip-flop D3, the input of the first NAND gate NAND1 is further connected to the output of the eighth inverter INV8, the input of the first OR gate OR1 is connected to the output of the seventh inverter INV7, the output of the first NAND gate NAND1 and the output of the third flip-flop D3, respectively, and the output of the first OR gate OR1 is a FLAG signal.

9. The controllable delay time dead time generating circuit of claim 4, wherein the eight-divided clock generating module comprises a ninth inverter INV9, a tenth inverter INV10, an eleventh inverter INV11, a fourth flip-flop D4, a fifth flip-flop D5, a sixth flip-flop D6 AND a first AND gate 1;

the ninth inverter INV9 is connected in parallel to the fourth flip-flop D4, the tenth inverter INV10 is connected in parallel to the fifth flip-flop D5, the eleventh inverter INV11 is connected in parallel to the sixth flip-flop D6, the clock input terminals of the fourth flip-flop D4, the fifth flip-flop D5 AND the sixth flip-flop D6 are CLK signals, the reset input terminals of the fourth flip-flop D4, the fifth flip-flop D5 AND the sixth flip-flop D6 are FLAG signals, the inverted output of the fourth flip-flop D4, the inverted output of the fifth flip-flop D5 AND the inverted output of the sixth flip-flop D6 are input to the first AND gate 1, AND the first AND gate 1 outputs 8CLK signals.

10. The controllable delay time dead time generating circuit of claim 4, wherein said dead time delay generating module comprises a twelfth inverter INV12, a thirteenth inverter INV13, a fourteenth inverter INV14, a fifteenth inverter INV15, a seventh flip-flop D7, an eighth flip-flop D8, a second OR gate OR2 and a third OR gate OR 3;

the data input end of the seventh flip-flop D7 is the output signal of the second OR gate OR2, the clock input end of the seventh flip-flop D7 is the CLK signal, and the reset input end of the seventh flip-flop D7 is the DATAIN _ H signal; the data input terminal of the eighth flip-flop D8 is the output signal of the third OR gate OR3, the clock input terminal of the eighth flip-flop D8 is the CLK signal, and the reset input terminal of the eighth flip-flop D8 is the DATAIN _ L signal; the inputs of the second OR gate OR2 are the 8CLK signal and the output of the seventh flip-flop D7, respectively; the inputs of the third OR gate OR3 are the 8CLK signal and the output of the eighth flip-flop D8, respectively; the output of the seventh flip-flop D7 is buffer-driven by the twelfth inverter INV12 and the thirteenth inverter INV13 to output a DATAOUT _ H signal, and the output of the eighth flip-flop D8 is buffer-driven by the fourteenth inverter INV14 and the fifteenth inverter INV15 to output a DATAOUT _ L signal.

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