CN107979359A - A kind of clock synchronization circuit for maintaining fixed pulse - Google Patents
A kind of clock synchronization circuit for maintaining fixed pulse Download PDFInfo
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- CN107979359A CN107979359A CN201810027277.1A CN201810027277A CN107979359A CN 107979359 A CN107979359 A CN 107979359A CN 201810027277 A CN201810027277 A CN 201810027277A CN 107979359 A CN107979359 A CN 107979359A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
Abstract
The present invention relates to a kind of clock synchronization circuit for maintaining fixed pulse, including external clock processing module and oscillator module, external clock processing module includes Schmidt trigger, rising edge detection unit, external clock detection unit and the first rest-set flip-flop, Schmidt trigger, rising edge detection unit, external clock detection unit, the input terminal and output terminal of first rest-set flip-flop are sequentially connected with, oscillator module includes rising edge id signal generation unit, trailing edge id signal generation unit and oscillator signal generation unit, rising edge id signal generation unit connects the input terminal of oscillator signal generation unit with the output terminal of trailing edge id signal generation unit, the input terminal of rising edge id signal generation unit connects the output terminal of oscillator signal generation unit with the input terminal of trailing edge id signal generation unit.This circuit ensures that clock-pulse width is constant, suitable for switching power circuit.
Description
Technical field
The present invention relates to a kind of clock synchronization circuit, specifically a kind of maintenance for Switching Power Supply PWM controls is consolidated
Determine the clock synchronization circuit of pulse, belong to technical field of integrated circuits.
Background technology
For conventional clock synchronous circuit, when the access of no external clock is V_sync=0, internal oscillator self-vibration produces
Clock signal OSC, specific input-output wave shape figure are as shown in Figure 1.When accessing external clock V_sync synchronizations, clock signal
The pulsewidth of OSC can be consistent with external clock, it is impossible to be kept constant, specific input-output wave shape figure is as shown in Figure 2.Switching
Often include conventional clock synchronous circuit in the pwm control circuit of power supply, be illustrated in figure 3 a kind of BUCK types Switching Power Supply
PWM control principle drawings, it can be seen that clock signal OSC and duty cycle signals V_duty are respectively as in schematic diagram shown in Fig. 3 first
The set of rest-set flip-flop and reset signal.By weber lawDraw, BUCK type Switching Power Supplies PWM controls
The duty cycle of signal V_pwm processed is, it is seen that D by output input ratio determine and with other internal signals without
Close.However, for clock synchronization circuit therein, if the external clock accessed make it that the pulsewidth of clock signal OSC is very big,
It will cause the control of the duty cycle D while subject clock signal OSC and duty cycle signals V_duty of V_pwm, referring specifically to the institute of attached drawing 4
Show.
The content of the invention
The present invention is exactly for the nonsynchronous problem of clock signal present in existing clock synchronization circuit, there is provided Yi Zhongwei
The clock synchronization circuit of fixed pulse is held, the circuit overall construction design is ingenious, can effectively ensure that the pulse of clock synchronization circuit
Fix and influenced from external clock.
To achieve these goals, the technical solution adopted by the present invention is a kind of synchronous electricity of clock for maintaining fixed pulse
Road, including external clock processing module and oscillator module, the external clock processing module include Schmidt trigger, rise
Along detection unit, external clock detection unit and the first rest-set flip-flop, the input terminal of the Schmidt trigger is drawn as outer
The signal input part of portion's clock processing module, the input terminal of the output terminal connection rising edge detection unit of Schmidt trigger, on
Rise the input terminal along the output terminal connection external clock detection unit of detection unit, the output terminal connection of external clock detection unit
The input terminal of first rest-set flip-flop, the output terminal of the first rest-set flip-flop draw the signal output as external clock processing module
End；
The oscillator module includes rising edge id signal generation unit, trailing edge id signal generation unit and oscillator signal
Generation unit, the external clock of the signal output part connection rising edge id signal generation unit of the external clock processing module
Control terminal, the output terminal of rising edge id signal generation unit connect vibration with the output terminal of trailing edge id signal generation unit
The input terminal of signal generation unit, the input terminal of rising edge id signal generation unit and trailing edge id signal generation unit
Input terminal connects the output terminal of oscillator signal generation unit, and the output terminal of oscillator signal generation unit, which is drawn, is used as oscillator module
Signal output part, the signal output part output clock signal OSC of oscillator module.
As a modification of the present invention, the rising edge detection unit includes the 3rd phase inverter, the 3rd capacitance, first
NAND gate, the 4th phase inverter, the input terminal of the 3rd phase inverter draw the input terminal as rising edge detection unit, the 3rd phase inverter
Output terminal connect an input terminal of the first NAND gate, another input terminal of the first NAND gate connects the defeated of the 3rd phase inverter
Enter end, one end of the 3rd capacitance is connected to the output terminal of the 3rd phase inverter, and the other end of the 3rd capacitance is grounded, the first NAND gate
Output terminal connects the input terminal of the 4th phase inverter, and the output terminal of the 4th phase inverter draws the output as rising edge detection unit
End.
As a modification of the present invention, it is brilliant that the external clock detection unit includes the 5th MOS transistor, the 6th MOS
Body pipe, the 7th MOS transistor, the 4th capacitance, the 3rd comparator, the 5th phase inverter, hex inverter, the 7th phase inverter, the 8th
Phase inverter, the 9th phase inverter, the second NAND gate, the grid of the 5th MOS transistor are drawn as the defeated of external clock detection unit
Enter end, the source electrode ground connection of the 5th MOS transistor, the drain electrode of the 5th MOS transistor and the 6th MOS transistor is connected to the after joining altogether
Incoming clock FREQUENCY CONTROL after the grid of the inverting input of three comparators, the 6th MOS transistor and the 7th MOS transistor joins altogether
The source electrode of signal V_rt, the 6th MOS transistor and the 7th MOS transistor accesses power supply VCC after joining altogether, the 7th MOS transistor
Drain electrode connection clock frequency control signal V_rt, the normal phase input end access reference signal V_ref of the 3rd comparator, the 3rd compares
The output terminal of device connects the input terminal of the 5th phase inverter, and the output terminal of the 5th phase inverter connects an input of the second NAND gate
End, another input terminal of the second NAND gate connect the output terminal of the 7th phase inverter, the input terminal connection the 5th of the 7th phase inverter
The grid of MOS transistor, the input terminal of the output terminal connection hex inverter of the second NAND gate, the input terminal of the 8th phase inverter connect
Connect the input terminal of the 7th phase inverter, the output terminal of the 8th phase inverter connects the input terminal of the 9th phase inverter, hex inverter it is defeated
The output terminal of outlet and the 9th phase inverter draws the output terminal as external clock detection unit jointly.
As a modification of the present invention, the rising edge id signal generation unit includes the first MOS transistor, first
It is capacitance, the second MOS transistor, the 3rd MOS transistor, first comparator, the first three-level phase inverter, the first nor gate, first anti-
Phase device, the grid of the first MOS transistor are drawn the external clock control terminal as rising edge id signal generation unit and are connected
The signal output part of external clock processing module, the source electrode ground connection of the first MOS transistor, the second MOS transistor and the 3rd MOS are brilliant
The drain electrode of body pipe is connected to the inverting input of first comparator, the drain electrode of the first MOS transistor and the first capacitance after joining altogether
One end be all connected with the inverting input of first comparator, the grid incoming clock frequency control signal V_ of the second MOS transistor
The source electrode of rt, the source electrode access power supply VCC of the second MOS transistor, the other end of the first capacitance and the 3rd MOS transistor connects
Ground, the grid of the 3rd MOS transistor draw the input terminal as rising edge id signal generation unit and connect oscillator signal production
The output terminal of raw unit, the normal phase input end access reference signal V_ref of first comparator, the output terminal connection of first comparator
The input terminal of first three-level phase inverter, an input terminal of output terminal the first nor gate of connection of the first three-level phase inverter, first
The output terminal of another input terminal connection rising edge detection unit of nor gate, the output terminal connection first of the first nor gate are anti-phase
The input terminal of device, the output terminal of the first phase inverter draw the output terminal as rising edge id signal generation unit and connect vibration
The input terminal of signal generation unit.
As a modification of the present invention, the trailing edge id signal generation unit includes constant current source, the 4th MOS
Transistor, the second phase inverter, the second capacitance, the second comparator, the second three-level phase inverter, it is brilliant that constant current source accesses the 4th MOS
The drain electrode of body pipe, the input terminal of the second phase inverter draw the input terminal as trailing edge id signal generation unit and connect vibration
The output terminal of signal generation unit, the output terminal of the second phase inverter connect the grid of the 4th MOS transistor, the 4th MOS transistor
Drain electrode the second comparator of connection inverting input, the source electrode ground connection of the 4th MOS transistor, one end access the of the second capacitance
The inverting input of two comparators, the other end ground connection of the second capacitance, the normal phase input end access reference signal of the second comparator
V_ref, the output terminal of the second comparator connect the input terminal of the second three-level phase inverter, and the output terminal of the second three-level phase inverter is drawn
As trailing edge id signal generation unit output terminal and connect the input terminal of oscillator signal generation unit.
As a modification of the present invention, the oscillator signal generation unit includes the second rest-set flip-flop, anti-phase Schmidt
Trigger, the reset terminal and set end of second rest-set flip-flop draw the input terminal as oscillator signal generation unit respectively,
The output terminal of the rising edge id signal generation unit connects the reset terminal of the second rest-set flip-flop, and trailing edge id signal produces
The output terminal of unit connects the set end of the second rest-set flip-flop, and the output terminal of the second rest-set flip-flop connects anti-phase Schmidt trigger
Input terminal, the output terminal of anti-phase Schmidt trigger draws the output terminal as oscillator signal generation unit.
As a modification of the present invention, first MOS transistor, the 3rd MOS transistor, the 4th MOS transistor,
Five MOS transistors use N-type MOS transistor, and second MOS transistor, the 6th MOS transistor and the 7th MOS transistor are adopted
Use N-type MOS transistor.
As a modification of the present invention, the first three-level phase inverter and the second three-level phase inverter are anti-using three
Phase device is in series, and first rest-set flip-flop and the second rest-set flip-flop are formed using two nor gate interconnections.
As a modification of the present invention, the external clock processing module output external clock id signal V_sync_
H, when there is external clock V_sync to access circuit, external clock id signal V_sync_h is drawn high until external clock V_sync
It is disconnected from the circuit；The pulse width of the oscillator module output clock signal OSC is to the second capacitance by constant current source
Charging interval determine, and the clock cycle of clock signal OSC by the sum of charging interval of the first capacitance and the second capacitance certainly
It is fixed.
As a modification of the present invention, the value magnitude of the 3rd capacitance is pico farad level.
Relative to the prior art, advantages of the present invention includes：This clock synchronization circuit has the advantages of simple structure and easy realization, property
Can be reliable and stable, due to having used constant current source, the arteries and veins for the clock signal OSC that whole circuit is exported in oscillator module
It is that the charging interval of the second capacitance is determined by constant current source to rush width, and the clock cycle of clock signal OSC is by first
The sum of charging interval of capacitance and the second capacitance determines, so regardless of whether accessed external clock in circuit, what it was exported
The pulse width of clock signal OSC immobilizes, so that frequency and pulse width no requirement (NR) to external clock, greatly expand
The working range of clock synchronization circuit, the switching power circuit especially suitable for PWM modulation；In addition, handle mould in external clock
Rising edge detection unit employed in block produces narrow pulse signal SYN_CLK at external clock V_sync rising edges, and will
Narrow pulse signal SYN_CLK is used to control the clock signal OSC of oscillator module to export, and effectively reduces circuit delay.
Brief description of the drawings
Fig. 1 is input-output wave shape figure of the conventional clock synchronous circuit in no external timing signal and self-vibration.
Fig. 2 is input-output wave shape figure of the conventional clock synchronous circuit when accessing external timing signal synchronization.
Fig. 3 is the BUCK type Switching Power Supply PWM control principle drawings comprising conventional clock synchronous circuit.
Fig. 4 is that the BUCK type Switching Power Supplies PWM comprising conventional clock synchronous circuit controls each signal waveforms.
Fig. 5 is the clock synchronization circuit structure chart of maintenance fixed pulse proposed by the present invention.
Fig. 6 is the input-output wave shape figure of the clock synchronization circuit of maintenance fixed pulse proposed by the present invention.
Embodiment
In order to deepen the understanding of the present invention and understanding, the invention will be further described below in conjunction with the accompanying drawings and introduces.
As shown in figure 5, a kind of clock synchronization circuit for maintaining fixed pulse, including external clock processing module and oscillator
Module, the external clock processing module include Schmidt trigger, rising edge detection unit, external clock detection unit and the
One rest-set flip-flop, the input terminal of the Schmidt trigger draw the signal input part as external clock processing module, Shi Mi
The input terminal of the output terminal connection rising edge detection unit of special trigger, the output terminal connection external clock of rising edge detection unit
The input terminal of detection unit, the output terminal of external clock detection unit connect the input terminal of the first rest-set flip-flop, the first RS triggerings
The output terminal of device draws the signal output part as external clock processing module.The oscillator module includes rising edge mark letter
Number generation unit, trailing edge id signal generation unit and oscillator signal generation unit, the letter of the external clock processing module
The external clock control terminal of number output terminal connection rising edge id signal generation unit, rising edge id signal generation unit it is defeated
Outlet connects the input terminal of oscillator signal generation unit, rising edge mark letter with the output terminal of trailing edge id signal generation unit
The input terminal of number generation unit connects the output of oscillator signal generation unit with the input terminal of trailing edge id signal generation unit
End, the output terminal of oscillator signal generation unit draw the signal output part as oscillator module, and the signal of oscillator module is defeated
Outlet output clock signal OSC.
Specifically, the rising edge id signal generation unit includes the first MOS transistor M4, the first capacitance C1, second
MOS transistor M2, the 3rd MOS transistor M3, first comparator OP1, the first three-level phase inverter X2, the first nor gate nor1,
The grid of one phase inverter inv4, the first MOS transistor M4 draws the external clock control as rising edge id signal generation unit
End processed and the signal output part for connecting external clock processing module, the source electrode ground connection of the first MOS transistor M4, the 2nd MOS crystal
The drain electrode of pipe M2 and the 3rd MOS transistor M3 is connected to the inverting input of first comparator OP1, the first MOS crystal after joining altogether
One end of the drain electrode of pipe M4 and the first capacitance C1 are all connected with the inverting input of first comparator OP1, the second MOS transistor M2
Grid incoming clock frequency control signal V_rt, the second MOS transistor M2 source electrode access power supply VCC, the first capacitance C1's
The source electrode of the other end and the 3rd MOS transistor M3 are grounded, and the grid of the 3rd MOS transistor M3 is drawn as rising edge mark letter
The input terminal of number generation unit simultaneously connects the output terminal of oscillator signal generation unit, and the normal phase input end of first comparator OP1 connects
Enter reference signal V_ref（Its value range is 0-5V）, the first three-level phase inverter X2's of output terminal connection of first comparator OP1
Input terminal, the output terminal of the first three-level phase inverter X2 connect an input terminal of the first nor gate nor1, the first nor gate nor1
Another input terminal connection rising edge detection unit output terminal, the output terminal of the first nor gate nor1 connects the first phase inverter
The input terminal of inv4, the output terminal of the first phase inverter inv4 draw output terminal and company as rising edge id signal generation unit
Connect the input terminal of oscillator signal generation unit.
The trailing edge id signal generation unit includes constant current source Iref, the 4th MOS transistor M5, second anti-phase
Device inv8, the second capacitance C2, the second comparator OP2, the second three-level phase inverter X1, it is brilliant that constant current source Iref accesses the 4th MOS
The drain electrode of body pipe M5, the input terminal of the second phase inverter inv8 draw input terminal and company as trailing edge id signal generation unit
The output terminal of oscillator signal generation unit is connect, the output terminal of the second phase inverter inv8 connects the grid of the 4th MOS transistor M5, the
The inverting input of the second comparator OP2 of drain electrode connection of four MOS transistor M5, the source electrode ground connection of the 4th MOS transistor M5, the
The inverting input of the second comparator OP2, the other end ground connection of the second capacitance C2, the second comparator are accessed in one end of two capacitance C2
The normal phase input end access reference signal V_ref of OP2（Its value range is 0-5V）, the output terminal connection of the second comparator OP2
The input terminal of second three-level phase inverter X1, the output terminal of the second three-level phase inverter X1 is drawn produces list as trailing edge id signal
The output terminal of member simultaneously connects the input terminal of oscillator signal generation unit.
The oscillator signal generation unit includes the second rest-set flip-flop, anti-phase Schmidt trigger, the 2nd RS triggerings
The reset terminal and set end of device draw the input terminal as oscillator signal generation unit respectively, and the rising edge id signal produces
The output terminal of unit connects the reset terminal of the second rest-set flip-flop, and the output terminal of trailing edge id signal generation unit connects the 2nd RS
The set end of trigger, the output terminal of the second rest-set flip-flop connect the input terminal of anti-phase Schmidt trigger, and anti-phase Schmidt touches
Send out output terminal of the output terminal extraction of device as oscillator signal generation unit.
The rising edge detection unit includes the 3rd phase inverter inv13, the 3rd capacitance C4, the first NAND gate nand2, the 4th
The input terminal of phase inverter inv14, the 3rd phase inverter inv13 draw the input terminal as rising edge detection unit, the 3rd phase inverter
The output terminal of inv13 connects an input terminal of the first NAND gate nand2, and another input terminal of the first NAND gate nand2 connects
Connecing the input terminal of the 3rd phase inverter inv13, one end of the 3rd capacitance C4 is connected to the output terminal of the 3rd phase inverter inv13, and the 3rd
The other end ground connection of capacitance C4, the output terminal of the first NAND gate nand2 connect the input terminal of the 4th phase inverter inv14, and the 4th is anti-
The output terminal of phase device inv14 draws the output terminal as rising edge detection unit.
The external clock detection unit includes the 5th MOS transistor M6, the 6th MOS transistor M7, the 7th MOS transistor
M8, the 4th capacitance C3, the 3rd comparator OP3, the 5th phase inverter inv9, hex inverter inv10, the 7th phase inverter inv11,
Eight phase inverter inv12, the 9th phase inverter inv13, the second NAND gate nand1, the grid of the 5th MOS transistor M6 are drawn as outer
The input terminal of portion's clock detecting unit, the source electrode ground connection of the 5th MOS transistor M6, the 5th MOS transistor M6 and the 6th MOS crystal
The drain electrode of pipe M7 is connected to the inverting input of the 3rd comparator OP3, the 6th MOS transistor M7 and the 7th MOS crystal after joining altogether
Incoming clock frequency control signal V_rt after the grid of pipe M8 joins altogether（Its value range is 0-5V）, the 6th MOS transistor M7 and
The source electrode of 7th MOS transistor M8 accesses power supply VCC, the drain electrode connection clock frequency control of the 7th MOS transistor M8 after joining altogether
Signal V_rt, the 6th MOS transistor M7 and the 7th MOS transistor M8 form current mirroring circuit, clock frequency control signal V_rt
For controlling the size of current of the current mirror.The normal phase input end access reference signal V_ref of 3rd comparator OP3（Its value
Scope is 0-5V）, the input terminal of the 5th phase inverter inv9 of output terminal connection of the 3rd comparator OP3, the 5th phase inverter inv9's
Output terminal connects an input terminal of the second NAND gate nand1, and another input terminal connection the 7th of the second NAND gate nand1 is anti-
The output terminal of phase device inv11, the input terminal of the 7th phase inverter inv11 connect the grid of the 5th MOS transistor M6, the second NAND gate
The input terminal of the output terminal connection hex inverter inv10 of nand1, the input terminal connection the 7th of the 8th phase inverter inv12 are anti-phase
The input terminal of device inv11, the output terminal of the 8th phase inverter inv12 connect the input terminal of the 9th phase inverter inv13, hex inverter
The output terminal of the output terminal of inv10 and the 9th phase inverter inv13 draw the output terminal as external clock detection unit jointly.
The first MOS transistor M4, the 3rd MOS transistor M3, the 4th MOS transistor M5, the 5th MOS transistor M6 are adopted
With N-type MOS transistor, the second MOS transistor M2, the 6th MOS transistor M7 and the 7th MOS transistor M8 use p-type MOS
Transistor.
The first three-level phase inverter X2 and the second three-level phase inverter X1 are formed using three inverter series, wherein,
First three-level phase inverter X2 is sequentially connected in series and is formed using phase inverter inv1, phase inverter inv2, phase inverter inv3, and the second three-level is anti-
Phase device X1 is sequentially connected in series and is formed using phase inverter inv5, phase inverter inv6, phase inverter inv7.First rest-set flip-flop and
Two rest-set flip-flops are formed using two nor gate interconnections, wherein, the first rest-set flip-flop be using nor gate nor5 and/or
NOT gate nor6 interconnections form, and the second rest-set flip-flop is formed using nor gate nor2 and nor gate nor3 interconnections.
The external clock processing module exports external clock id signal V_sync_h, is connect when there is external clock V_sync
When entering circuit, external clock id signal V_sync_h is drawn high until external clock V_sync is disconnected from the circuit；The vibration
The pulse width of device module output clock signal OSC is that the charging interval of the second capacitance C2 is determined by constant current source Iref,
And the clock cycle of clock signal OSC is determined by the sum of charging interval of the first capacitance C1 and the second capacitance C2.
The value magnitude of the 3rd capacitance C4 uses pico farad level, and the output terminal of such rising edge detection unit is when exterior
Narrow pulse signal SYN_CLK can be produced at the rising edge of clock V_sync.
The external clock V_sync for inputting external clock processing module carries out shaping by Schmidt trigger first, rises
The switch of the 5th MOS transistor M6 is controlled to be used as the 4th capacitance C3's along the narrow pulse signal SYN_CLK of detection unit output
Charging of the current mirroring circuit that discharge path, the 6th MOS transistor M7 and the 7th MOS transistor M8 are formed as the 4th capacitance C3
External clock V_sync, is only disconnected from the circuit and turn-off time enough 4th capacitance C3 is charged to higher than base by path
During calibration signal V_ref, the output of hex inverter inv10 is 1, so that the external clock mark of the first rest-set flip-flop output
Signal V_sync_h is low level, and narrow pulse signal SYN_CLK is also low level at this time.There is external clock V_sync working as
When, if narrow pulse signal SYN_CLK is high level, the output of hex inverter inv10 is 0, and the output of nor gate nor6 is
0, so that external clock id signal V_sync_h is high level；And if narrow pulse signal SYN_CLK is low level, external clock
Id signal V_sync_h keeps high level.
In oscillator module, it is assumed that the input terminal of external clock processing module does not access external clock V_sync and exports
Clock signal OSC be low level, then the 4th MOS transistor M5 open the second capacitance C2 repid discharges to 0, the 2nd MOS crystal
Pipe M2 is charged to more than reference signal V_ref under the control of clock frequency control signal V_rt to the first capacitance C1 so that the
One comparator OP1 upsets are 0, and carry out anti-phase rear output high level by the first three-level phase inverter X2.Due to burst pulse at this time
Signal SYN_CLK is low level, and the output of the first nor gate nor1 is to determine that the first three-level is anti-phase by the first three-level phase inverter X2
Device X2 make it that the second rest-set flip-flop resets and the clock signal OSC by being exported after the progress shaping of anti-phase Schmidt trigger is height
Level；Clock signal OSC opens the 3rd MOS transistor M3 and discharges rapidly the first capacitance C1 at this time so that first comparator OP1
To 1, then the first three-level phase inverter X2 outputs are low level for upset；And clock signal OSC closes the 4th MOS transistor M5, by perseverance
Charging is carried out to the second capacitance C2 by constant current source Iref until the second comparator OP2 upsets are 0 so that the second three-level phase inverter X1
Export as high level.The high level of second three-level phase inverter X1 outputs makes the output of the second rest-set flip-flop be 1, is then applied by anti-phase
Schmitt trigger output clock signal OSC is low level, has so been concatenated to form the clock signal OSC of fixed pulse.
The input terminal of external clock processing module has accessed external clock V_sync, the external clock mark of module output
Signal V_sync_h（High level）The first MOS transistor M4 can be opened and make it that the first three-level phase inverter X2 is low level always, and
And will not work in same period due to the output of narrow pulse signal SYN_CLK after clock signal OSC is put 1, therefore,
The pulse width of clock signal OSC is only related to the charging interval of the second capacitance C2 with constant current source Iref.
In conclusion as shown in fig. 6, due to employing constant current source Iref in oscillator module, no matter outside
Whether portion's clock processing module meets external clock V_sync, and the pulsewidth of the clock signal OSC of this clock synchronization circuit output is all
It is changeless.The clock synchronization circuit of this kind of circuit structure is more suitable for the switching power circuit of PWM modulation.
It should be noted that above-described embodiment, is not used for limiting protection scope of the present invention, in above-mentioned technical proposal
On the basis of made equivalents or replacement each fall within the scope that the claims in the present invention are protected.In the claims, it is single
Word "comprising" does not exclude the presence of element not listed in the claims.Word first, second and third use do not indicate that
Any order, can be construed to title by these words.
Claims (10)
- A kind of 1. clock synchronization circuit for maintaining fixed pulse, it is characterised in that：Including external clock processing module and oscillator Module, the external clock processing module include Schmidt trigger, rising edge detection unit, external clock detection unit and the One rest-set flip-flop, the input terminal of the Schmidt trigger draw the signal input part as external clock processing module, Shi Mi The input terminal of the output terminal connection rising edge detection unit of special trigger, the output terminal connection external clock of rising edge detection unit The input terminal of detection unit, the output terminal of external clock detection unit connect the input terminal of the first rest-set flip-flop, the first RS triggerings The output terminal of device draws the signal output part as external clock processing module；The oscillator module includes rising edge id signal generation unit, trailing edge id signal generation unit and oscillator signal Generation unit, the input terminal of the signal output part connection rising edge id signal generation unit of the external clock processing module, The output terminal of rising edge id signal generation unit connects oscillator signal production with the output terminal of trailing edge id signal generation unit The input terminal of raw unit, the input terminal of rising edge id signal generation unit and the input terminal of trailing edge id signal generation unit The output terminal of oscillator signal generation unit is connected, the output terminal of oscillator signal generation unit draws the signal as oscillator module Output terminal, the signal output part output clock signal OSC of oscillator module.
- A kind of 2. clock synchronization circuit for maintaining fixed pulse as claimed in claim 1, it is characterised in that the rising edge mark Know signal generation unit including the first MOS transistor, the first capacitance, the second MOS transistor, the 3rd MOS transistor, first to compare Device, the first three-level phase inverter, the first nor gate, the first phase inverter, the grid of the first MOS transistor is drawn to be identified as rising edge The external clock control terminal of signal generation unit simultaneously connects the signal output part of external clock processing module, the first MOS transistor Source electrode ground connection, the drain electrode of the second MOS transistor and the 3rd MOS transistor is connected to the anti-phase input of first comparator after connection altogether One end of end, the drain electrode of the first MOS transistor and the first capacitance is all connected with the inverting input of first comparator, the 2nd MOS The grid incoming clock frequency control signal V_rt of transistor, the source electrode access power supply VCC of the second MOS transistor, the first capacitance The other end and the 3rd MOS transistor source electrode ground connection, the grid of the 3rd MOS transistor draws and is used as rising edge id signal The input terminal of generation unit and the output terminal for connecting oscillator signal generation unit, the normal phase input end access benchmark of first comparator Signal V_ref, the output terminal of first comparator connect the input terminal of the first three-level phase inverter, the output terminal of the first three-level phase inverter Connect an input terminal of the first nor gate, the output of another input terminal connection rising edge detection unit of the first nor gate End, the output terminal of the first nor gate connect the input terminal of the first phase inverter, and the output terminal of the first phase inverter, which is drawn, is used as rising edge The output terminal of id signal generation unit and the input terminal for connecting oscillator signal generation unit.
- A kind of 3. clock synchronization circuit for maintaining fixed pulse as claimed in claim 2, it is characterised in that the trailing edge mark Knowing signal generation unit includes constant current source, the 4th MOS transistor, the second phase inverter, the second capacitance, the second comparator, the Two three-level phase inverters, constant current source access the drain electrode of the 4th MOS transistor, and the input terminal of the second phase inverter is drawn as decline Along id signal generation unit input terminal and connect the output terminal of oscillator signal generation unit, the output terminal of the second phase inverter connects Connect the grid of the 4th MOS transistor, the inverting input of drain electrode the second comparator of connection of the 4th MOS transistor, the 4th MOS crystalline substances The inverting input of the second comparator is accessed in the source electrode ground connection of body pipe, one end of the second capacitance, and the other end of the second capacitance is grounded, The normal phase input end access reference signal V_ref of second comparator, the output terminal of the second comparator connect the second three-level phase inverter Input terminal, the output terminal of the second three-level phase inverter is drawn to shake as the output terminal of trailing edge id signal generation unit and connection Swing the input terminal of signal generation unit.
- A kind of 4. clock synchronization circuit for maintaining fixed pulse as claimed in claim 3, it is characterised in that the oscillator signal Generation unit includes the second rest-set flip-flop, anti-phase Schmidt trigger, the reset terminal and set end point of second rest-set flip-flop Yin Chu not be as the input terminal of oscillator signal generation unit, the output terminal connection second of the rising edge id signal generation unit The reset terminal of rest-set flip-flop, the set end of output terminal the second rest-set flip-flop of connection of trailing edge id signal generation unit, second The output terminal of rest-set flip-flop connects the input terminal of anti-phase Schmidt trigger, and the output terminal of anti-phase Schmidt trigger draws conduct The output terminal of oscillator signal generation unit.
- A kind of 5. clock synchronization circuit for maintaining fixed pulse as claimed in claim 4, it is characterised in that the rising edge inspection Surveying unit includes the 3rd phase inverter, the 3rd capacitance, the first NAND gate, the 4th phase inverter, and the input terminal of the 3rd phase inverter, which is drawn, to be made For the input terminal of rising edge detection unit, the output terminal of the 3rd phase inverter connects an input terminal of the first NAND gate, first with Another input terminal of NOT gate connects the input terminal of the 3rd phase inverter, and one end of the 3rd capacitance is connected to the output of the 3rd phase inverter End, the other end ground connection of the 3rd capacitance, the output terminal of the first NAND gate connect the input terminal of the 4th phase inverter, the 4th phase inverter Output terminal draws the output terminal as rising edge detection unit.
- A kind of 6. clock synchronization circuit for maintaining fixed pulse as claimed in claim 5, it is characterised in that the external clock Detection unit includes the 5th MOS transistor, the 6th MOS transistor, the 7th MOS transistor, the 4th capacitance, the 3rd comparator, the Five phase inverters, hex inverter, the 7th phase inverter, the 8th phase inverter, the 9th phase inverter, the second NAND gate, the 5th MOS transistor Grid draw input terminal as external clock detection unit, the source electrode of the 5th MOS transistor is grounded, the 5th MOS transistor Drain electrode with the 6th MOS transistor is connected to the inverting input of the 3rd comparator, the 6th MOS transistor and the 7th after joining altogether The grid of MOS transistor accesses control voltage signal after joining altogether, the source electrode of the 6th MOS transistor and the 7th MOS transistor joins altogether Power supply VCC, the drain electrode connection control voltage signal of the 7th MOS transistor, the normal phase input end access of the 3rd comparator are accessed afterwards Reference signal, the output terminal of the 3rd comparator connect the input terminal of the 5th phase inverter, the output terminal connection second of the 5th phase inverter One input terminal of NAND gate, another input terminal of the second NAND gate connect the output terminal of the 7th phase inverter, the 7th phase inverter Input terminal connect the 5th MOS transistor grid, the second NAND gate output terminal connection hex inverter input terminal, the 8th The input terminal of phase inverter connects the input terminal of the 7th phase inverter, and the output terminal of the 8th phase inverter connects the input of the 9th phase inverter The output terminal of end, the output terminal of hex inverter and the 9th phase inverter draws the output as external clock detection unit jointly End.
- A kind of 7. clock synchronization circuit for maintaining fixed pulse as claimed in claim 6, it is characterised in that the first MOS Transistor, the 3rd MOS transistor, the 4th MOS transistor, the 5th MOS transistor use N-type MOS transistor, the 2nd MOS Transistor, the 6th MOS transistor and the 7th MOS transistor use N-type MOS transistor.
- A kind of 8. clock synchronization circuit for maintaining fixed pulse as claimed in claim 7, it is characterised in that first three-level Phase inverter and the second three-level phase inverter are formed using three inverter series, first rest-set flip-flop and the second rest-set flip-flop Formed using two nor gate interconnections.
- A kind of 9. clock synchronization circuit for maintaining fixed pulse as claimed in claim 8, it is characterised in that the external clock Processing module export external clock id signal, when have external clock access circuit when, external clock id signal draw high until External clock is disconnected from the circuit；The pulse width of the oscillator module output clock signal is to second by constant current source The charging interval of capacitance determines, and the clock cycle of clock signal is determined by the sum of charging interval of the first capacitance and the second capacitance It is fixed.
- A kind of 10. clock synchronization circuit for maintaining fixed pulse as claimed in claim 9, it is characterised in that the 3rd electricity The value magnitude of appearance is pico farad level.
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