CN105007074B - A kind of delay matching circuit for charge pump phase frequency detector - Google Patents
A kind of delay matching circuit for charge pump phase frequency detector Download PDFInfo
- Publication number
- CN105007074B CN105007074B CN201510492774.5A CN201510492774A CN105007074B CN 105007074 B CN105007074 B CN 105007074B CN 201510492774 A CN201510492774 A CN 201510492774A CN 105007074 B CN105007074 B CN 105007074B
- Authority
- CN
- China
- Prior art keywords
- input
- phase inverter
- gate
- termination
- liang
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention belongs to electronic circuit technology field, more particularly to a kind of delay matching circuit for charge pump phase frequency detector.The main technical schemes of the present invention are that the delay being output to from d type flip flop on two paths of charge pump switches pipe is accomplished to match well, while notice that the phase inverter time delay chain in upper and lower two transmission channel is full symmetric.Also it is delayed simultaneously by phase inverter and capacitor increase, the width of phase frequency detector reset pulse is widened, to solve the problems, such as charge pump phase frequency detector deadbanding.Invention has the beneficial effect that, can significantly eliminate the influence that general phase frequency detector is output to delay mismatches in the transmission path of charge pump input so that phase frequency detector precision is higher, and phaselocked loop frequency locking is more accurate.
Description
Technical field
The invention belongs to electronic circuit technology field, more particularly to a kind of delay for charge pump phase frequency detector
Match circuit.
Background technology
Charge pump phase lock loop CPPLL due to its big frequency acquisition ability and it is static when phase difference be zero the advantages that into
For the main flow of current phaselocked loop product, and as the key component of phaselocked loop, suitable for the phase frequency detector of charge pump phase lock loop
Also study hotspot is turned into.Phase frequency detector PFD, its major function are the reference signal of detection input and the frequency of feedback signal
And phase deviation, utilize phase or frequency departure to produce control signal so that voltage controlled oscillator VCO output signal is towards reducing phase
Position or the direction change of frequency departure.
The phase-locked loop circuit of the electrically charged pump of in general as shown in figure 1, because the charge switch of charge pump is generally PMOS,
Its unlatching is controlled by logic low, and discharge switch is generally NMOS tube, and its unlatching is controlled by logic high.Thus must
Surely have a signal and be output to more phase inverters in the transmission path of charge pump input from phase frequency detector, so as to cause
There is mismatch in two signals that phase frequency detector is output to charge pump switches pipe, go out voltage controlled oscillator control voltage in time
Existing ripple, so as to increase phase noise, therefore, current circuit exists and has the problem of delay in two transmission paths.
The content of the invention
It is to be solved by this invention, aiming at asking for delay mismatches present in above-mentioned conventional charge pump type phaselocked loop
Topic, propose a kind of delay matching circuit for charge pump phase frequency detector.
To achieve the above object, the present invention adopts the following technical scheme that：
A kind of delay matching circuit for charge pump phase frequency detector, including first liang input nor gate, second liang it is defeated
Enter nor gate, the 3rd liang input nor gate, the 4th liang input nor gate, the 5th liang input nor gate, the 6th liang input nor gate,
7th liang of input nor gate, the one or three input nor gate, the two or three input nor gate, four input nor gates, the first phase inverter
INV1, the second phase inverter INV2, the 3rd phase inverter INV3, the 4th phase inverter INV4, the 5th phase inverter INV5, hex inverter
It is INV6, the 7th phase inverter INV7, the 8th phase inverter INV8, the 9th phase inverter INV9, the tenth phase inverter INV10, the 11st anti-phase
Device INV11, the 12nd phase inverter INV12, the 13rd phase inverter INV13, the 14th phase inverter INV14, the 15th phase inverter
INV15, the tenth hex inverter INV16, the 17th phase inverter INV17, eighteen incompatibilities phase device INV18, the 19th phase inverter
INV19, the 20th phase inverter INV20, the 21st phase inverter INV21 and electric capacity C；
First input of first liang of input nor gate connects external timing signal, its input or non-of the second input termination the one or three
The output end of door, it exports the first input of the second input of the input nor gate of termination the one or three and second liang of input nor gate
End；The first phase inverter INV1 of the output termination input and the 4th phase inverter INV4 input of one or three input nor gate；
First phase inverter INV1 the second phase inverter INV2 of output termination input；Second phase inverter INV2 output end
Connect the 3rd phase inverter INV3 input and hex inverter INV6 input；
3rd phase inverter INV3 output end connects with the 4th phase inverter INV4 output end is followed by the 5th phase inverter INV5
Input and the 8th phase inverter INV8 input；5th phase inverter INV5 output termination hex inverter INV6 input
End；Hex inverter INV6 the 7th phase inverter INV7 of output termination input；7th phase inverter INV7 output end is nothing
Imitate signal output part；
8th phase inverter INV8 the 9th phase inverter INV9 of output termination input；9th phase inverter INV9 output end
Connect the first input end of four input nor gates；9th phase inverter INV9 output end is charge pump charging control signal output end；
The output end of second second liang of input nor gate of input termination of four input nor gates, its 3rd input termination the 5th
The output end of two input nor gates, the 15th phase inverter INV15 of its 4th input termination output end, it exports the 7th liang of termination
Input the first input end of nor gate；
Second input termination enable signal of the 7th liang of input nor gate, it exports the 21st phase inverter INV21 of termination
Input；21st phase inverter INV21 the 20th phase inverter INV20 of output termination input；21st is anti-phase
The tie point of device INV21 output ends and the 20th phase inverter INV21 inputs after electric capacity C by being grounded；
20th phase inverter INV20 the 19th phase inverter INV19 of output termination input；19th phase inverter
Second input of INV19 output the 3rd liang of input nor gate of termination, the first input end of the one or three input nor gate, the
3rd input of four liang of first input ends for inputting nor gate and the two or three input nor gate；
The output end of 3rd second liang of input nor gate of input termination of the one or three input nor gate；5th liang of input or non-
The first input end of door connects the output end of first liang of input nor gate, the output of its 5th input the 3rd liang of input nor gate of termination
End；The first input end of 3rd liang of input nor gate connects the output end of second liang of input nor gate；
The output end of second the 5th liang of input nor gate of input termination of the 4th liang of input nor gate, it exports termination second
The first input end of two input nor gates；The output of second the 6th liang of input nor gate of input termination of second liang of input nor gate
End, it exports the first input end of the input nor gate of termination the two or three；
The output end of second the 6th liang of input nor gate of input termination of the two or three input nor gate, it exports termination the 6th
First input end, the tenth phase inverter INV10 input and the 11st phase inverter INV11 input of two input nor gates；
Second input termination external feedback signal of the 6th liang of input nor gate；
11st phase inverter INV11 the 12nd phase inverter INV12 of output termination input；12nd phase inverter
INV12 the 13rd phase inverter INV13 of output termination input and the 17th phase inverter INV17 input；
13rd phase inverter INV13 output end connects that to be followed by the 14th anti-phase with the tenth phase inverter INV10 output end
The input of device INV14 input and the tenth hex inverter INV16；14th phase inverter INV14 output termination the 15th
Phase inverter INV15 input；
Tenth hex inverter INV16 the 17th phase inverter INV17 of output termination input；17th phase inverter
INV17 output termination eighteen incompatibilities phase device INV18 input；Eighteen incompatibilities phase device INV18 output end is put for charge pump
Electric control signal output end.
Invention has the beneficial effect that, can significantly eliminate the transmission path that general phase frequency detector is output to charge pump input
The influence of upper delay mismatches so that phase frequency detector precision is higher, and phaselocked loop frequency locking is more accurate.
Brief description of the drawings
Fig. 1 is the phase frequency detector circuit diagram of conventional belt charge pump；
Fig. 2 is the electrical block diagram of the delay matching circuit for charge pump phase frequency detector of the present invention；
Fig. 3 is the simulating, verifying figure of the delay matching circuit of the present invention.
Embodiment
The present invention proposes a kind of delay matching circuit suitable for charge pump phase frequency detector, it is possible to reduce phase frequency detector
The mismatch being delayed in the transmission path of charge pump input is output to, improves phaselocked loop frequency locking precision.
The physical circuit figure of the present invention is illustrated in figure 2, two input nor gate NOR2_1 first input end meets input A,
The input nor gate NOR3_1 of second input termination three output end and phase inverter INV1 and INV4 input C, output termination two
Input nor gate NOR3_1 the second input and/or two input NOT gate NOR2_2 first input end, three input nor gates
NOR3_1 first input end connects three input nor gate NOR3_2 the 3rd input and two and inputs the second of nor gate NOR2_3
The output end of input, two input nor gate NOR2_4 first input end and phase inverter INV19, three input nor gates
The NOR3_1 input nor gate NOR2_2 of the 3rd input termination two output end, two input nor gate NOR2_2 the second input
Two input nor gate NOR2_3 output end is connect, two input nor gate NOR2_3 first input end connects two input nor gates
Second input of NOR2_2 output end and four input nor gate NOR4_1, phase inverter INV1 output end meet phase inverter INV2
Input, phase inverter INV2 output end connects phase inverter INV3 input and phase inverter INV6 input, phase inverter
INV3 output end connects phase inverter INV5 input and phase inverter INV8 input with phase inverter INV4 output end, anti-phase
Device INV5 output end connects phase inverter INV6 input, and phase inverter INV6 output end connects phase inverter INV7 input, instead
Phase device INV7 output termination E, phase inverter INV8 output end connect phase inverter INV9 input, phase inverter INV9 output end
The second input termination that output end UP, two input nor gate NOR2_6 are met with four input nor gate NOR4_1 first input end is defeated
Enter B, first input end connects three input nor gate nor gate NOR3_2 output end and phase inverter INV10 and INV11 input
D, output termination or two input NOT gate NOR3_2 the second input and two input nor gate NOR2_5 the second input, three is defeated
Enter the nor gate NOR3_2 input nor gate NOR3_1 of the 3rd input termination three first input end and two input nor gate NOR2_
The output end of 3 the second input, two input nor gate NOR2_4 first input end and phase inverter INV19, three inputs or
The NOT gate NOR3_2 input nor gate NOR2_5 of the second input termination two output end, the first of two input nor gate NOR2_5 are defeated
Enter the input nor gate of termination two NOR2_4 output end, the two input nor gate NOR2_4 input nor gate of the second input termination two
3rd input of NOR2_5 output end and four input nor gate NOR4_1, phase inverter INV11 input are D, phase inverter
INV11 output end connects phase inverter INV12 input, and phase inverter INV12 output end connects phase inverter INV13 and phase inverter
INV17 input, phase inverter INV10 and phase inverter INV13 output end connect the defeated of phase inverter INV14 and phase inverter INV16
Enter end, phase inverter INV14 output end connects phase inverter INV15 input, the phase inverter INV15 input or non-of output termination four
Door NOR4_1 the 4th input, phase inverter INV16 output end connect phase inverter INV17 input, and phase inverter INV17's is defeated
Go out to hold phase inverter INV18 input, phase inverter INV18 output end is output DOWN, and four input nor gate NOR4_1's is defeated
Go out the input nor gate of termination two NOR2_7 the second input, two input nor gate NOR2_7 first input end connects input signal
EN, two input nor gate NOR2_7 output end connect phase inverter INV21 input, phase inverter INV21 output end phase inverter
INV20 input and electric capacity C top crown, electric capacity C bottom crown ground connection, phase inverter INV20 output end connect phase inverter
INV19 input.
The present invention operation principle be：
As shown in Fig. 2 A is input reference clock, B is the signal that phaselocked loop output is fed back, and EN is the frequency and phase discrimination
The enable signal of device, when EN is low, circuit normal work, UP is the charging control signal of charge pump, and DOWN is charge pump
Discharge control signal, E are the invalid signals of output.NOR2_1 and NOR3_1, NOR2_2 and NOR2_3 respectively constitute rest-set flip-flop,
The d type flip flop of rising edge triggering of the two rest-set flip-flops composition with reset terminal, A and B produce C, D letter after the d type flip flop
Number, from C, D signal to output signals UP, DOWN be the present invention core texture.As shown in Figure 2 from C signal to output signals UP
1. and 2. there are two paths, 1. the delay of Pyatyi phase inverter is passed through in path, 2. the delay of three-level phase inverter is passed through in path；Believe from D
Number there are three paths 3., 4. and 5. to output signal DOWN, 3. path is delayed by level Four phase inverter, path is 4. anti-by six grades
Phase device is delayed, 5. path is delayed by level Four phase inverter, therefore generally from D signals to output signal DOWN inverter delay chain
Length be more than inverter delay chain length from C signal to output signals UP, but shared simultaneously from C signal to output signals UP
Two paths, there are three paths from D signals to output signal DOWN, therefore can draw from D signals to output signal DOWN roads
Driving force on footpath is more than the driving force on from C signal to output signals UP path.Will delay chain length and driving force
Combine analysis, although, driving big to delay chain length on output signal DOWN path from D signals can be obtained
Ability is strong, although and on the path from C signal to output signals UP postpone chain length it is small, its driving force is weaker, passes through
Regulation to upper and lower sides phase inverter sizes at different levels, it is possible to achieve it is good between time delay and driving force to trade off, make to trigger from D
The delay that device is output on two paths of charge pump switches pipe is accomplished to match well, while notices two transmission channels up and down
On phase inverter time delay chain it is full symmetric, be the purpose of phase inverter INV5, INV6, INV7 before valid output signal E and DOWN believe
Phase inverter INV16, INV17, INV18 before number are matched, more to reduce mismatch.In addition, phase inverter INV19,
INV20, INV21 and capacitor C effects are increase delays, the width of phase frequency detector reset pulse are widened, to solve charge pump
The problem of phase frequency detector deadbanding.Fig. 3 show the simulating, verifying figure of delay matching circuit of the present invention, it can be seen that without
Delay inequality before optimization on two transmission paths is 360ps, and two transmission roads after the delay matching circuit optimization of the present invention
Delay inequality on footpath is 83ps, thus illustrate delay matching circuit proposed by the present invention have matched well on two paths when
Between postpone difference.
In summary, the present invention proposes that a kind of delay matching circuit suitable for charge pump phase frequency detector can significantly subtract
Small phase frequency detector is output to the mismatch being delayed in the transmission path of charge pump, improves phaselocked loop frequency locking precision.
Claims (1)
1. a kind of delay matching circuit for charge pump phase frequency detector, including first liang of input nor gate, second liang of input
Nor gate, the 3rd liang of input nor gate, the 4th liang of input nor gate, the 5th liang of input nor gate, the 6th liang of input nor gate, the
Seven liang input nor gates, the one or three input nor gate, the two or three input nor gate, four input nor gates, the first phase inverter INV1,
Second phase inverter INV2, the 3rd phase inverter INV3, the 4th phase inverter INV4, the 5th phase inverter INV5, hex inverter INV6,
Seven phase inverter INV7, the 8th phase inverter INV8, the 9th phase inverter INV9, the tenth phase inverter INV10, the 11st phase inverter INV11,
12nd phase inverter INV12, the 13rd phase inverter INV13, the 14th phase inverter INV14, the 15th phase inverter INV15, the tenth
It is hex inverter INV16, the 17th phase inverter INV17, eighteen incompatibilities phase device INV18, the 19th phase inverter INV19, the 20th anti-
Phase device INV20, the 21st phase inverter INV21 and electric capacity C；
First input of first liang of input nor gate connects external timing signal, its input nor gate of the second input termination the one or three
Output end, it exports the first input end of the second input of the input nor gate of termination the one or three and second liang of input nor gate；
The first phase inverter INV1 of the output termination input and the 4th phase inverter INV4 input of one or three input nor gate；
First phase inverter INV1 the second phase inverter INV2 of output termination input；Second phase inverter INV2 output termination the
Three phase inverter INV3 input and hex inverter INV6 input；
3rd phase inverter INV3 output end connects with the 4th phase inverter INV4 output end is followed by the defeated of the 5th phase inverter INV5
Enter end and the 8th phase inverter INV8 input；5th phase inverter INV5 output termination hex inverter INV6 input；
Hex inverter INV6 the 7th phase inverter INV7 of output termination input；7th phase inverter INV7 output end is invalid letter
Number output end；
8th phase inverter INV8 the 9th phase inverter INV9 of output termination input；9th phase inverter INV9 output termination four
Input the first input end of nor gate；9th phase inverter INV9 output end is charge pump charging control signal output end；
The output end of second second liang of input nor gate of input termination of four input nor gates, its 5th liang of the 3rd input termination are defeated
Enter the output end of nor gate, the 15th phase inverter INV15 of its 4th input termination output end, it exports the 7th liang of input of termination
The first input end of nor gate；
Second input termination enable signal of the 7th liang of input nor gate, it exports the defeated of the 21st phase inverter INV21 of termination
Enter end；21st phase inverter INV21 the 20th phase inverter INV20 of output termination input；21st phase inverter
The tie point of INV21 output ends and the 20th phase inverter INV21 inputs after electric capacity C by being grounded；
20th phase inverter INV20 the 19th phase inverter INV19 of output termination input；19th phase inverter INV19's
Output termination the 3rd liang of input nor gate the second input, the one or three input nor gate first input end, the 4th liang it is defeated
Enter the first input end of nor gate and the 3rd input of the two or three input nor gate；
The output end of 3rd second liang of input nor gate of input termination of the one or three input nor gate；Second liang inputs nor gate
First input end connects the output end of first liang of input nor gate, the output end of its second input the 3rd liang of input nor gate of termination；
The first input end of 3rd liang of input nor gate connects the output end of second liang of input nor gate；
The output end of second the 5th liang of input nor gate of input termination of the 4th liang of input nor gate, it is defeated that it exports the 5th liang of termination
Enter the first input end of nor gate；The output end of second the 6th liang of input nor gate of input termination of the 5th liang of input nor gate,
It exports the first input end of the input nor gate of termination the two or three；
The output end of second the 6th liang of input nor gate of input termination of the two or three input nor gate, it is defeated that it exports the 6th liang of termination
Enter the first input end, the tenth phase inverter INV10 input and the 11st phase inverter INV11 input of nor gate；6th
Second input termination external feedback signal of two input nor gates；
11st phase inverter INV11 the 12nd phase inverter INV12 of output termination input；12nd phase inverter INV12's
The 13rd phase inverter INV13 of output termination input and the 17th phase inverter INV17 input；
13rd phase inverter INV13 output end connects with the tenth phase inverter INV10 output end is followed by the 14th phase inverter
The input of INV14 input and the tenth hex inverter INV16；14th phase inverter INV14 output termination the 15th is anti-
Phase device INV15 input；
Tenth hex inverter INV16 the 17th phase inverter INV17 of output termination input；17th phase inverter INV17's
Output termination eighteen incompatibilities phase device INV18 input；Eighteen incompatibilities phase device INV18 output end is charge pump control letter
Number output end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510492774.5A CN105007074B (en) | 2015-08-12 | 2015-08-12 | A kind of delay matching circuit for charge pump phase frequency detector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510492774.5A CN105007074B (en) | 2015-08-12 | 2015-08-12 | A kind of delay matching circuit for charge pump phase frequency detector |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105007074A CN105007074A (en) | 2015-10-28 |
| CN105007074B true CN105007074B (en) | 2017-11-14 |
Family
ID=54379616
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510492774.5A Expired - Fee Related CN105007074B (en) | 2015-08-12 | 2015-08-12 | A kind of delay matching circuit for charge pump phase frequency detector |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105007074B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109274367A (en) * | 2018-09-05 | 2019-01-25 | 东南大学 | A kind of anti-charge pump mismatch pulls in the phase discriminator that range causes limitation to phaselocked loop |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000252818A (en) * | 1999-02-26 | 2000-09-14 | Nec Corp | Phase difference and current conversion circuit |
| CN1538622A (en) * | 2003-04-14 | 2004-10-20 | 沃福森微电子有限公司 | Improved phase/frequency detector and phase lock loop circuit |
| CN102007696A (en) * | 2008-04-14 | 2011-04-06 | 高通股份有限公司 | Phase to digital converter in all digital phase locked loop |
| CN102291127A (en) * | 2011-06-02 | 2011-12-21 | 西安电子科技大学 | Fully differential reset delay adjustable frequency and phase discriminator |
| CN103259539A (en) * | 2012-02-02 | 2013-08-21 | 联发科技股份有限公司 | Phase frequency detector |
| CN104682954A (en) * | 2015-02-06 | 2015-06-03 | 北京大学 | Half-rate random data phase detection circuit |
-
2015
- 2015-08-12 CN CN201510492774.5A patent/CN105007074B/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000252818A (en) * | 1999-02-26 | 2000-09-14 | Nec Corp | Phase difference and current conversion circuit |
| CN1538622A (en) * | 2003-04-14 | 2004-10-20 | 沃福森微电子有限公司 | Improved phase/frequency detector and phase lock loop circuit |
| CN102007696A (en) * | 2008-04-14 | 2011-04-06 | 高通股份有限公司 | Phase to digital converter in all digital phase locked loop |
| CN102291127A (en) * | 2011-06-02 | 2011-12-21 | 西安电子科技大学 | Fully differential reset delay adjustable frequency and phase discriminator |
| CN103259539A (en) * | 2012-02-02 | 2013-08-21 | 联发科技股份有限公司 | Phase frequency detector |
| CN104682954A (en) * | 2015-02-06 | 2015-06-03 | 北京大学 | Half-rate random data phase detection circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105007074A (en) | 2015-10-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102291127B (en) | Fully differential reset delay adjustable frequency and phase discriminator | |
| US9054681B2 (en) | High speed duty cycle correction and double to single ended conversion circuit for PLL | |
| CN104639157B (en) | Timing adjusting circuit and conductor integrated circuit device | |
| CN103546125B (en) | A kind of multiselect one burr-free clock switching circuit | |
| CN105610430B (en) | A kind of adaptive switched radiation hardening clock forming circuit of bimodulus based on phaselocked loop | |
| CN102291138B (en) | Stochastic time-digital converter | |
| CN106100617B (en) | A kind of on-line monitoring unit and its control circuit towards super wide voltage | |
| CN103888106A (en) | Method for designing trigger resistant to single event upset and single event transient pulses | |
| CN101394177B (en) | Output buffer circuit | |
| US7145375B2 (en) | Duty cycle detector with first, second, and third values | |
| WO2023077694A1 (en) | Rc oscillation circuit | |
| CN103152035B (en) | A kind of programmable delay multi-way control signals phase frequency detector for phase-locked loop | |
| WO2016030795A1 (en) | Clock gated flip-flop | |
| WO2013177759A1 (en) | Reduced dynamic power d flip-flop | |
| CN105007074B (en) | A kind of delay matching circuit for charge pump phase frequency detector | |
| CN104579259B (en) | Clock signal missing detecting circuit | |
| CN112564696A (en) | Phase frequency detector for delay phase-locked loop | |
| CN101098140B (en) | Fast locked frequency discrimination phase discriminator | |
| CN105049030B (en) | A kind of drive circuit with blanking function | |
| CN207853863U (en) | A kind of clock synchronization circuit maintaining fixed pulse | |
| CN104935333A (en) | High-speed low voltage phase frequency detector circuit | |
| CN104917517B (en) | For realize low-power consumption, Wide measuring range time-to-digit converter energy-saving circuit | |
| CN107645295A (en) | A kind of time sharing sampling holding circuit | |
| CN107967925A (en) | A kind of adaptive low-power consumption CAM matched line sensors of technique change | |
| CN208285288U (en) | Dual threshold is without comparator relaxation oscillating circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20171114 Termination date: 20200812 |