CN105007074A - Time-delay matching circuit for charge pump phase frequency detector - Google Patents
Time-delay matching circuit for charge pump phase frequency detector Download PDFInfo
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- CN105007074A CN105007074A CN201510492774.5A CN201510492774A CN105007074A CN 105007074 A CN105007074 A CN 105007074A CN 201510492774 A CN201510492774 A CN 201510492774A CN 105007074 A CN105007074 A CN 105007074A
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Abstract
The invention belongs to the technical field of electric circuits and provides a time-delay matching circuit for a charge pump phase frequency detector in particular. The technical solutions are as follows: the time delays of two channels from the output of a delay flip-flop to a charge pump switch tube well match and at the same time, phase inverter delay chains at an upper transmission channel and a lower transmission channel are completely symmetrical to each other. The circuit further increases the time delay through phase inverters and a capacitor to expand the width of phase frequency detector reset a pulse so as to solve the problem of the dead zone of a charge pump phase frequency detector. With such a circuit, the mismatching problem of time delays from the output of a delay flip-flop to a charge pump switch tube can be substantially solved, making the phase frequency detector more precise and the phase lock loops more accurate.
Description
Technical field
The invention belongs to electronic circuit technology field, relate to a kind of delay matching circuit for charge pump phase frequency detector specifically.
Background technology
Charge pump phase lock loop CPPLL due to its large frequency acquisition ability and static time phase difference be the main flow that the advantage such as zero has become current phase-locked loop product, and as the key component of phase-locked loop, the phase frequency detector being applicable to charge pump phase lock loop also becomes study hotspot.Phase frequency detector PFD, its major function detects frequency and the phase deviation of reference signal and the feedback signal inputted, utilize phase place or frequency departure to produce control signal, the direction that voltage controlled oscillator VCO is outputed signal towards reducing phase place or frequency departure changes.
The phase-locked loop circuit of general electrically charged pump as shown in Figure 1, because the charge switch of charge pump is generally PMOS, controls it and open, and discharge switch is generally NMOS tube, controls it open by logic high by logic low.So just must have a signal many inverters on the transmission path outputting to charge pump input from phase frequency detector, thus there is mismatch in time in two signals causing phase frequency detector to output to charge pump switches pipe, voltage controlled oscillator control voltage is made to occur ripple, thus increase phase noise, therefore, there is the problem having time delay at two transmission paths in current circuit.
Summary of the invention
To be solved by this invention, exactly for the problem of the delay mismatches existed in above-mentioned conventional charge pump type phase-locked loop, a kind of delay matching circuit for charge pump phase frequency detector is proposed.
For achieving the above object, the present invention adopts following technical scheme:
A kind of delay matching circuit for charge pump phase frequency detector, comprise first liang of input NOR gate, second liang of input NOR gate, 3rd liang of input NOR gate, 4th liang of input NOR gate, 5th liang of input NOR gate, 6th liang of input NOR gate, 7th liang of input NOR gate, one or three input NOR gate, two or three input NOR gate, four input NOR gate, first inverter INV1, second inverter INV2, 3rd inverter INV3, 4th inverter INV4, 5th inverter INV5, hex inverter INV6, 7th inverter INV7, 8th inverter INV8, 9th inverter INV9, tenth inverter INV10, 11 inverter INV11, 12 inverter INV12, 13 inverter INV13, 14 inverter INV14, 15 inverter INV15, tenth hex inverter INV16, 17 inverter INV17, eighteen incompatibilities phase device INV18, 19 inverter INV19, 20 inverter INV20, 21 inverter INV21 and electric capacity C,
First input of first liang of amount input NOR gate connects external timing signal, and its second input termination the or three inputs the output of NOR gate, and it exports termination the or three and inputs the second input of NOR gate and the first input end of second liang of input NOR gate; The input of output termination first inverter INV1 of the one or three input NOR gate and the input of the 4th inverter INV4;
The input of the output termination second inverter INV2 of the first inverter INV1; The input of output termination the 3rd inverter INV3 of the second inverter INV2 and the input of hex inverter INV6;
The input of the 5th inverter INV5 and the input of the 8th inverter INV8 is connect after the output of the 3rd inverter INV3 is connected with the output of the 4th inverter INV4; The input of the output termination hex inverter INV6 of the 5th inverter INV5; The input of output termination the 7th inverter INV7 of hex inverter INV6; The output of the 7th inverter INV7 is invalid signals output;
The input of output termination the 9th inverter INV9 of the 8th inverter INV8; The output termination four of the 9th inverter INV9 inputs the first input end of NOR gate; The output of the 9th inverter INV9 is charge pump charging control signal output;
The output of the second input termination second liang of input NOR gate of four input NOR gate, the output of its 3rd input termination the 5th liang of input NOR gate, its four-input terminal connects the output of the 15 inverter INV15, and it exports the first input end of termination the 7th liang input NOR gate;
Second input termination enable signal of the 7th liang of input NOR gate, it exports the input of termination the 21 inverter INV21; The input of output termination the 20 inverter INV20 of the 21 inverter INV21; The tie point of the 21 inverter INV21 output and the 20 inverter INV21 input is by ground connection after electric capacity C;
The input of output termination the 19 inverter INV19 of the 20 inverter INV20; Second input of output termination the 3rd amount input NOR gate of the 19 inverter INV19, the first input end of the one or three input NOR gate, the first input end and the two or three of the 4th liang of input NOR gate input the 3rd input of NOR gate;
The output of the 3rd input termination second liang input NOR gate of the one or three input NOR gate; The first input end of second liang of input NOR gate connects the output of first liang of input NOR gate, the output of its second input termination the 3rd liang input NOR gate; 3rd liang input NOR gate first input end connect second liang input NOR gate output;
The output of the second input termination the 5th liang input NOR gate of the 4th liang of input NOR gate, it exports the first input end of termination second liang input NOR gate; The output of the second input termination the 6th liang input NOR gate of second liang of input NOR gate, it exports the first input end that termination the two or three inputs NOR gate;
The output of the second input termination the 6th liang input NOR gate of the two or three input NOR gate, it exports termination the 6th liang input first input end of NOR gate, the input of the tenth inverter INV10 and the input of the 11 inverter INV11; Second input termination external feedback signal of the 6th liang of input NOR gate;
The input of output termination the 12 inverter INV12 of the 11 inverter INV11; The input of output termination the 13 inverter INV13 of the 12 inverter INV12 and the input of the 17 inverter INV17;
The input of the 14 inverter INV14 and the input of the tenth hex inverter INV16 is connect after the input of the 13 inverter INV13 is connected with the output of the tenth inverter INV10; The input of output termination the 15 inverter INV15 of the 14 inverter INV14;
The input of output termination the 17 inverter INV17 of the tenth hex inverter INV16; The input of the output termination eighteen incompatibilities phase device INV18 of the 17 inverter INV17; The output of eighteen incompatibilities phase device INV18 is charge pump discharge control signal output.
The beneficial effect of the invention is, significantly can eliminate the impact of delay mismatches on transmission path that general phase frequency detector outputs to charge pump input, make phase frequency detector precision higher, phase-locked loop frequency locking is more accurate.
Accompanying drawing explanation
Fig. 1 is the phase frequency detector circuit diagram of conventional belt charge pump;
Fig. 2 is the electrical block diagram of the delay matching circuit for charge pump phase frequency detector of the present invention;
Fig. 3 is the simulating, verifying figure of delay matching circuit of the present invention.
Embodiment
The present invention proposes a kind of delay matching circuit being applicable to charge pump phase frequency detector, can reduce the mismatch of time delay on transmission path that phase frequency detector outputs to charge pump input, improve phase-locked loop frequency locking precision.
Be illustrated in figure 2 physical circuit figure of the present invention, the first input end of two input NOR gate NOR2_1 meets input A, second input termination three inputs the output of NOR gate NOR3_1 and the input C of inverter INV1 and INV4, export termination two input NOR gate NOR3_1 the second input and or the first input end of two input not gate NOR2_2, the first input end of three input NOR gate NOR3_1 connects the 3rd input of three input NOR gate NOR3_2 and second input of two input NOR gate NOR2_3, the two input first input end of NOR gate NOR2_4 and the outputs of inverter INV19, the 3rd input termination two of three input NOR gate NOR3_1 inputs the output of NOR gate NOR2_2, the second input termination two of two input NOR gate NOR2_2 inputs the output of NOR gate NOR2_3, the first input end of two input NOR gate NOR2_3 connects the output of two input NOR gate NOR2_2 and second input of four input NOR gate NOR4_1, the input of the output termination inverter INV2 of inverter INV1, the input of output termination inverter INV3 of inverter INV2 and the input of inverter INV6, the output of inverter INV3 and the input of output termination inverter INV5 of inverter INV4 and the input of inverter INV8, the input of the output termination inverter INV6 of inverter INV5, the input of the output termination inverter INV7 of inverter INV6, the output termination E of inverter INV7, the input of the output termination inverter INV9 of inverter INV8, the first input end of the output of inverter INV9 and four input NOR gate NOR4_1 meets output UP, the second input termination input B of two input NOR gate NOR2_6, first input end meets the output of three input NOR gate NOR gate NOR3_2 and the input D of inverter INV10 and INV11, export second input of termination or two input not gate NOR3_2 and second input of two input NOR gate NOR2_5, the 3rd input termination three of three input NOR gate NOR3_2 inputs the first input end of NOR gate NOR3_1 and second input of two input NOR gate NOR2_3, the two input first input end of NOR gate NOR2_4 and the outputs of inverter INV19, the second input termination two of three input NOR gate NOR3_2 inputs the output of NOR gate NOR2_5, the first input end of two input NOR gate NOR2_5 connects the output of two input NOR gate NOR2_4, the second input termination two of two input NOR gate NOR2_4 inputs the output of NOR gate NOR2_5 and the 3rd input of four input NOR gate NOR4_1, the input of inverter INV11 is D, the input of the output termination inverter INV12 of inverter INV11, the output termination inverter INV13 of inverter INV12 and the input of inverter INV17, the output termination inverter INV14 of inverter INV10 and inverter INV13 and the input of inverter INV16, the input of the output termination inverter INV15 of inverter INV14, the output termination four of inverter INV15 inputs the four-input terminal of NOR gate NOR4_1, the input of the output termination inverter INV17 of inverter INV16, the input of the output inverter INV18 of inverter INV17, the output of inverter INV18 is for exporting DOWN, the output termination two of four input NOR gate NOR4_1 inputs second input of NOR gate NOR2_7, the first input end of two input NOR gate NOR2_7 meets input signal EN, the input of the output termination inverter INV21 of two input NOR gate NOR2_7, the input of output inverter INV20 of inverter INV21 and the top crown of electric capacity C, the bottom crown ground connection of electric capacity C, the input of the output termination inverter INV19 of inverter INV20.
Operation principle of the present invention is:
As shown in Figure 2, A is input reference clock, and B is the signal that phase-locked loop output feedack is returned, EN is the enable signal of this phase frequency detector, and when EN is low, circuit normally works, UP is the charging control signal of charge pump, and DOWN is the discharge control signal of charge pump, and E is the invalid signals exported.NOR2_1 and NOR3_1, NOR2_2 and NOR2_3 form rest-set flip-flop respectively, the d type flip flop of the rising edge triggering of these two rest-set flip-flop composition band reset terminals, A and B produces C, D signal after this d type flip flop, and from C, D signal to output signals UP, DOWN is core texture of the present invention.1. and 2. have two paths as shown in Figure 2 from C signal to output signals UP, path is 1. through the time delay of Pyatyi inverter, and path is 2. through the time delay of three grades of inverters, three paths are had 3. to output signal DOWN from D signal, and 5. 4., path is 3. through the time delay of level Four inverter, path is 4. through six grades of inverter time delays, path is 5. through the time delay of level Four inverter, therefore be greater than the inverter delay chain length from C signal to output signals UP from D signal to the length of the inverter delay chain of output signal DOWN generally, but have two paths from C signal to output signals UP simultaneously, three paths are had to output signal DOWN from D signal, therefore can draw from D signal and be greater than from C signal to the driving force output signals UP path to the driving force output signal DOWN path.Delay chain length and driving force are combined analysis, although can obtain large to delay chain length the path of output signal DOWN from D signal, but it is strong to play driving force, although and little to delay chain length the path of output signals UP from C signal, but its driving force is more weak, by the adjustment to upper and lower sides inverter size at different levels, good trading off between time of delay and driving force can be realized, make to accomplish good coupling from the d type flip flop time delay outputted to two paths of charge pump switches pipe, notice the inverter time delay chain full symmetric in upper and lower two transmission channels simultaneously, inverter INV5 before valid output signal E, INV6, INV7 object be with DOWN signal before inverter INV16, INV17, INV18 does and mates, to reduce mismatch more.In addition, inverter INV19, INV20, INV21 and capacitor C effect increase time delay, widens the width of phase frequency detector reset pulse, to solve the problem of charge pump phase frequency detector deadbanding.Figure 3 shows that the simulating, verifying figure of delay matching circuit of the present invention, can see that the delay inequality without optimizing on front two transmission paths is 360ps, and the delay inequality after delay matching circuit optimization of the present invention on two transmission paths is 83ps, therefore illustrate that the delay matching circuit of the present invention's proposition well have matched the difference of the time delay on two paths.
In sum, the present invention proposes the mismatch that a kind of delay matching circuit being applicable to charge pump phase frequency detector significantly can reduce time delay on transmission path that phase frequency detector outputs to charge pump, improves phase-locked loop frequency locking precision.
Claims (1)
1., for a delay matching circuit for charge pump phase frequency detector, comprise first liang of input NOR gate, second liang of input NOR gate, 3rd liang of input NOR gate, 4th liang of input NOR gate, 5th liang of input NOR gate, 6th liang of input NOR gate, 7th liang of input NOR gate, one or three input NOR gate, two or three input NOR gate, four input NOR gate, first inverter INV1, second inverter INV2, 3rd inverter INV3, 4th inverter INV4, 5th inverter INV5, hex inverter INV6, 7th inverter INV7, 8th inverter INV8, 9th inverter INV9, tenth inverter INV10, 11 inverter INV11, 12 inverter INV12, 13 inverter INV13, 14 inverter INV14, 15 inverter INV15, tenth hex inverter INV16, 17 inverter INV17, eighteen incompatibilities phase device INV18, 19 inverter INV19, 20 inverter INV20, 21 inverter INV21 and electric capacity C,
First input of first liang of amount input NOR gate connects external timing signal, and its second input termination the or three inputs the output of NOR gate, and it exports termination the or three and inputs the second input of NOR gate and the first input end of second liang of input NOR gate; The input of output termination first inverter INV1 of the one or three input NOR gate and the input of the 4th inverter INV4;
The input of the output termination second inverter INV2 of the first inverter INV1; The input of output termination the 3rd inverter INV3 of the second inverter INV2 and the input of hex inverter INV6;
The input of the 5th inverter INV5 and the input of the 8th inverter INV8 is connect after the output of the 3rd inverter INV3 is connected with the output of the 4th inverter INV4; The input of the output termination hex inverter INV6 of the 5th inverter INV5; The input of output termination the 7th inverter INV7 of hex inverter INV6; The output of the 7th inverter INV7 is invalid signals output;
The input of output termination the 9th inverter INV9 of the 8th inverter INV8; The output termination four of the 9th inverter INV9 inputs the first input end of NOR gate; The output of the 9th inverter INV9 is charge pump charging control signal output;
The output of the second input termination second liang of input NOR gate of four input NOR gate, the output of its 3rd input termination the 5th liang of input NOR gate, its four-input terminal connects the output of the 15 inverter INV15, and it exports the first input end of termination the 7th liang input NOR gate;
Second input termination enable signal of the 7th liang of input NOR gate, it exports the input of termination the 21 inverter INV21; The input of output termination the 20 inverter INV20 of the 21 inverter INV21; The tie point of the 21 inverter INV21 output and the 20 inverter INV21 input is by ground connection after electric capacity C;
The input of output termination the 19 inverter INV19 of the 20 inverter INV20; Second input of output termination the 3rd amount input NOR gate of the 19 inverter INV19, the first input end of the one or three input NOR gate, the first input end and the two or three of the 4th liang of input NOR gate input the 3rd input of NOR gate;
The output of the 3rd input termination second liang input NOR gate of the one or three input NOR gate; The first input end of second liang of input NOR gate connects the output of first liang of input NOR gate, the output of its second input termination the 3rd liang input NOR gate; 3rd liang input NOR gate first input end connect second liang input NOR gate output;
The output of the second input termination the 5th liang input NOR gate of the 4th liang of input NOR gate, it exports the first input end of termination second liang input NOR gate; The output of the second input termination the 6th liang input NOR gate of second liang of input NOR gate, it exports the first input end that termination the two or three inputs NOR gate;
The output of the second input termination the 6th liang input NOR gate of the two or three input NOR gate, it exports termination the 6th liang input first input end of NOR gate, the input of the tenth inverter INV10 and the input of the 11 inverter INV11; Second input termination external feedback signal of the 6th liang of input NOR gate;
The input of output termination the 12 inverter INV12 of the 11 inverter INV11; The input of output termination the 13 inverter INV13 of the 12 inverter INV12 and the input of the 17 inverter INV17;
The input of the 14 inverter INV14 and the input of the tenth hex inverter INV16 is connect after the input of the 13 inverter INV13 is connected with the output of the tenth inverter INV10; The input of output termination the 15 inverter INV15 of the 14 inverter INV14;
The input of output termination the 17 inverter INV17 of the tenth hex inverter INV16; The input of the output termination eighteen incompatibilities phase device INV18 of the 17 inverter INV17; The output of eighteen incompatibilities phase device INV18 is charge pump discharge control signal output.
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| CN201510492774.5A CN105007074B (en) | 2015-08-12 | 2015-08-12 | A kind of delay matching circuit for charge pump phase frequency detector |
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| CN201510492774.5A CN105007074B (en) | 2015-08-12 | 2015-08-12 | A kind of delay matching circuit for charge pump phase frequency detector |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109274367A (en) * | 2018-09-05 | 2019-01-25 | 东南大学 | A kind of anti-charge pump mismatch pulls in the phase discriminator that range causes limitation to phaselocked loop |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000252818A (en) * | 1999-02-26 | 2000-09-14 | Nec Corp | Phase difference and current conversion circuit |
| CN1538622A (en) * | 2003-04-14 | 2004-10-20 | 沃福森微电子有限公司 | Improved phase/frequency detector and phase lock loop circuit |
| CN102007696A (en) * | 2008-04-14 | 2011-04-06 | 高通股份有限公司 | Phase to digital converter in all digital phase locked loop |
| CN102291127A (en) * | 2011-06-02 | 2011-12-21 | 西安电子科技大学 | Fully differential reset delay adjustable frequency and phase discriminator |
| CN103259539A (en) * | 2012-02-02 | 2013-08-21 | 联发科技股份有限公司 | Phase frequency detector |
| CN104682954A (en) * | 2015-02-06 | 2015-06-03 | 北京大学 | Half-rate random data phase detection circuit |
-
2015
- 2015-08-12 CN CN201510492774.5A patent/CN105007074B/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000252818A (en) * | 1999-02-26 | 2000-09-14 | Nec Corp | Phase difference and current conversion circuit |
| CN1538622A (en) * | 2003-04-14 | 2004-10-20 | 沃福森微电子有限公司 | Improved phase/frequency detector and phase lock loop circuit |
| CN102007696A (en) * | 2008-04-14 | 2011-04-06 | 高通股份有限公司 | Phase to digital converter in all digital phase locked loop |
| CN102291127A (en) * | 2011-06-02 | 2011-12-21 | 西安电子科技大学 | Fully differential reset delay adjustable frequency and phase discriminator |
| CN103259539A (en) * | 2012-02-02 | 2013-08-21 | 联发科技股份有限公司 | Phase frequency detector |
| CN104682954A (en) * | 2015-02-06 | 2015-06-03 | 北京大学 | Half-rate random data phase detection circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109274367A (en) * | 2018-09-05 | 2019-01-25 | 东南大学 | A kind of anti-charge pump mismatch pulls in the phase discriminator that range causes limitation to phaselocked loop |
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