CN105610430B - A kind of adaptive switched radiation hardening clock forming circuit of bimodulus based on phaselocked loop - Google Patents
A kind of adaptive switched radiation hardening clock forming circuit of bimodulus based on phaselocked loop Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
The present invention proposes a kind of adaptive switched radiation hardening clock forming circuit of bimodulus based on phaselocked loop, is mainly made of two independent phaselocked loops, delay unit, error detection unit and clock selecting unit.Two independent phaselocked loops are the charge pump phase lock loop without radiation hardening, provide corresponding clock output respectively；The delay unit realizes the delay to pll output signal；Whether two output signals that the error detection unit is used for detecting phase frequency detector in main road phaselocked loop are correct and export corresponding indication signal；The clock selecting unit carries out selectivity output as final output to the delay output of two-way phaselocked loop.The present invention can largely eliminate interference of the single particle effect to circuit working state in radiation environment, it is ensured that stabilization of the phaselocked loop as clock signal improves the reliability of system, has many advantages, such as to realize that convenient, area is small, low in energy consumption.
Description
Technical field
The present invention relates to a kind of clock forming circuits based on phaselocked loop more particularly to a kind of adaptive switched radioresistance of bimodulus to add
Gu clock forming circuit can effectively eliminate and inhibit single-ion transient state (SET) effect.
Background technology
With the continuous diminution of integrated circuit feature size, caused for energetic particle hits in irradiation space environment
Single-ion transient state (SET) effect more can not be ignored.The system clock for stablizing high speed is to ensure that the pass of system high-speed steady running
Key, single-ion transient state (SET) effect can not only cause the output clock signal of phaselocked loop that mistake occurs, and the clock of mistake will also draw
Data transmission fault even whole system is sent out to paralyse.
For the seriousness of single particle effect, providing system clock with the phaselocked loop with radiation tolerance design seems ten
Divide necessity.According to the analysis to phaselocked loop single particle effect, non-reinforced phase-locked loop circuit inside it there are many places sensitive nodes,
The especially analog modules such as charge pump and voltage controlled oscillator once being disturbed by a single-particle, just need a period of time could
Enough it is restored to stable state.
For existing phaselocked loop radiation hardening technology, it is broadly divided into two classes：One kind is for phaselocked loop inside many places
Sensitive nodes carry out the modes such as redundancy or compensation and are reinforced.Since sensitive nodes are more inside phaselocked loop, can only will influence compared with
Big node carries out Design of Reinforcement, only SET effects is reinforced from maximum probability in this way, by lower error rate part；Separately
One kind is that system-level reinforcing is carried out to phaselocked loop, i.e. triplication redundancy is reinforced, since phaselocked loop is replicated three parts by which, consume compared with
Big power consumption and area.
Invention content
The technical problems to be solved by the invention are：When a kind of adaptive switched radiation hardening of bimodulus based on phaselocked loop is provided
Clock generative circuit had both had the consolidation effect of high reliability, while but also with the small advantage of low in energy consumption, area.
The technical scheme is that：
A kind of adaptive switched radiation hardening clock forming circuit of bimodulus based on phaselocked loop, it is characterised in that：Including main road
Phaselocked loop and bypass phaselocked loop, main road delay unit and bypass delay unit, error detection unit and clock selecting unit；Main road
Phaselocked loop and bypass phaselocked loop are the charge pump phase lock loop without radiation hardening, provide clock signal output respectively；Main road
The delay that delay unit obtains the clock signal that main road phaselocked loop exports into line delay main road pll clock signal exports；It is auxiliary
The delay that road delay unit obtains the clock signal that bypass phaselocked loop exports into line delay bypass pll clock signal exports；
The error detection unit is detected two output signals of phase frequency detector in main road phaselocked loop and exports instruction letter
Number, when two output signals of phase frequency detector are identical, the indication signal of error detection unit output is the first level signal,
When two output signal differences of phase frequency detector, the indication signal of error detection unit output is second electrical level signal；When
Clock selecting unit carries out being selected as final output to the delay output of two-way phaselocked loop, and main road pll clock signal prolongs
When output and spoke road pll clock signal delay output as clock selecting unit two clocks input, error-detecting list
The indication signal of member output is inputted as the control of clock selecting unit, when the indication signal of error detection unit is the first level
During signal, the delay output of clock selecting Unit selection main road phaselocked loop is final output, when the instruction of error detection unit
When signal is second electrical level signal, the delay output of clock selecting Unit selection bypass phaselocked loop is final output.
First level signal is high level, and second electrical level signal is low level.
The main road phaselocked loop and bypass phaselocked loop are identical unit, respectively by phase frequency detector, charge pump, filtering
Device, voltage controlled oscillator and frequency divider are formed；Two as phase frequency detector of the output signal of external reference signal and frequency divider
Input signal, the input signal of two output signal charge pumps of phase frequency detector, the output of charge pump connect the input of wave filter,
The output of wave filter connects the input of voltage controlled oscillator, the clock signal that the output of voltage controlled oscillator is exported as phaselocked loop, simultaneously
As the input of frequency divider, the input exported as phase frequency detector of frequency divider, so as to form a circuit；When phaselocked loop is steady
When working surely, two output signals of phase frequency detector are two pulse-period signals with same pulse width, and it rises
Edge and failing edge are perfectly aligned；When phase-locked loop operation exception, two output signal pulsewidths of phase frequency detector change, and become
Change amount is directly proportional to the variation of the frequency and phase of pll output signal, can directly react phase-locked loop operation abnormal conditions.
The main road delay unit and bypass delay unit are identical unit, using chain of inverters structure；Input
Signal passes through the propagation in chain of inverters so that output signal has the delay time t of corresponding time compared with input signal, wherein prolonging
Slow time t should be at least more than the time in an external reference signal period.
The error detection unit by XOR gate, filter capacitor C, the first driving circuit, NMOS tube, current source, capacitance and
Second driving circuit forms, input of two output signals of phase frequency detector as XOR gate, XOR gate in main road phaselocked loop
Output connect one end of filter capacitor C, and as the input of the first driving circuit, the other end of filter capacitor C is grounded；First drives
The output of dynamic circuit connects the grid of NMOS tube, and the drain electrode of NMOS tube is connected with the output terminal of current source, the source electrode ground connection of NMOS tube,
One end of capacitance is connected with the drain electrode of NMOS tube, and the other end ground connection of capacitance, NMOS tube is used for whether controlling current source to capacitance
It charges；Current source output is connected with power vd D；The drain electrode of NMOS tube is connected with the input terminal of the second driving circuit, the
The output terminal of two driving circuits exports the indication signal.
Clock selecting unit includes first and door, second and door, phase inverter, the first d type flip flop, the second d type flip flop, third
D type flip flop, four d flip-flop, third and door, the 4th and door and or door；
Wherein indication signal is connected, while the 4th D respectively with first with an input terminal of door and the input terminal of phase inverter
The QN terminations first of trigger and another input terminal of door, first inputs with exporting for door as the D ends of the first d type flip flop；
Main road pll clock signal delay output respectively with the first d type flip flop CK ends, third d type flip flop CK ends, third and door
One input terminal is connected；The Q ends output of first d type flip flop is connected with the D ends input of third d type flip flop, the Q ends of third d type flip flop
Output connects another input terminal with door；The output of phase inverter exports the input as second with door with the QN ends of third d type flip flop,
Second inputs with the output of door as the D ends of the second d type flip flop, and the delay of spoke road pll clock signal is exported respectively with second
The CK ends of d type flip flop are connected, the CK ends of four d flip-flop and the 4th are connected with an input terminal of door；The Q of second d type flip flop
End output is connected with the D ends input of four d flip-flop, and the Q ends output of d type flip flop is connected with another input terminal with door；Third
With door output and the 4th with door export as or door input；Or the output of door is the clock output of clock selecting unit
Signal.
The advantages of the present invention over the prior art are that：Due to the adaptive switched structure of bimodulus that the present invention uses, if electric
Main road pll output signal in road as final output signal is abnormal, and system can be immediately switched to bypass phaselocked loop
Output is as final output, and after error detection unit prompting main road phase-locked loop operation restores stable state, system can switch again
To the output of main road phaselocked loop as final output, i.e., for system by adaptive switched between two-way pll output signal, utilization is less
The resource moment ensure final output for correct clock export, have many advantages, such as realize conveniently, area it is small, low in energy consumption, in itself
There is good immunity to single-ion transient state, two cannot all be made by being happened at the single event transient pulse of inside configuration arbitrary node
Disturbance occurs simultaneously for road phase-locked loop clock output ensures that entire circuit has high anti-single particle transient state ability.
Description of the drawings
Fig. 1 is the adaptive switched radiation hardening clock forming circuit structure diagram of bimodulus based on phaselocked loop；
Fig. 2 is phaselocked loop schematic diagram；
Fig. 3 is delay unit schematic diagram；
Fig. 4 is error detection unit schematic diagram；
Fig. 5 is clock selecting cell schematics.
Specific embodiment
As shown in Figure 1, the adaptive switched radiation hardening clock forming circuit of bimodulus based on phaselocked loop, by main road phaselocked loop 1
It is formed with bypass phaselocked loop 2, main road delay unit 3 and bypass delay unit 5, error detection unit 4 and clock selecting unit 6；
Main road phaselocked loop 1 and bypass phaselocked loop 2 are the charge pump phase lock loop without radiation hardening, and it is defeated to provide clock signal respectively
Go out；The clock signal PLL-CLK1 that main road delay unit 3 exports main road phaselocked loop 1 obtains main road phase-locked loop clock into line delay
The delay output CK1 of signal；The clock signal PLL-CLK1 that bypass delay unit 5 exports bypass phaselocked loop 2 is obtained into line delay
Delay to bypass pll clock signal exports CK2；The error detection unit 4 is to frequency and phase discrimination in main road phaselocked loop 1
Two output signals UPs of device, DN are detected and export indication signal Error, when two working state signals are identical, accidentally
The indication signal Error that poor detection unit 4 exports is the first level signal, when two working state signal differences, error inspection
It is second electrical level signal to survey the indication signal Error that unit 4 exports；Clock selecting unit 6 exports the delay of two-way phaselocked loop
Be selected as final output, the delay output CK1 of main road pll clock signal and spoke road pll clock signal
Delay output CK2 is inputted as two clocks of clock selecting unit 6, and the indication signal Error that error detection unit 4 exports makees
Control for clock selecting unit 6 inputs, when the indication signal of error detection unit 4 is the first level signal, clock selecting
It is final output that unit 6, which selects the delay output CK1 of main road phaselocked loop 1, when the indication signal of error detection unit 4 is second
During level signal, it is final output that clock selecting unit 6, which selects the delay output CK2 of bypass phaselocked loop 2,.Preferably, it is described
First level signal is high level, and second electrical level signal is low level.
As shown in Fig. 2, main road phaselocked loop 1 is identical with 2 structure of bypass phaselocked loop, it is typical charge pump phase lock loop, by reflecting
Frequency phase discriminator 211, charge pump 212, wave filter 213, voltage controlled oscillator 214 and frequency divider 215 are formed.External reference signal FREF
With the input of the output signal of frequency divider 25 as phase frequency detector 211, two output UP and DN of phase frequency detector 211 are electricity
The input of lotus pump 212, the output of charge pump 212 connect the input of wave filter 213, and the output of wave filter 213 connects voltage controlled oscillator 214
Input, the output of voltage controlled oscillator 214 connects the input of frequency divider 215, and the output of frequency divider 215 takes back phase frequency detector 211
Form a circuit.Wherein when stabilized works, two output signals UPs and DN of phase frequency detector 211 are with phase
With two pulse-period signals of pulsewidth, and its rising edge and failing edge are perfectly aligned；When phase-locked loop operation exception, frequency discrimination
Two output signals UPs and DN pulsewidths of phase discriminator 211 change, the frequency and phase of variable quantity and pll output signal
Variation it is directly proportional, can directly react phase-locked loop operation abnormal conditions.
As shown in figure 3, main road delay unit 3 and bypass delay unit 5 are identical unit, chained using phase inverter
Structure.Input signal passes through the propagation in chain of inverters so that output signal has the delay time of corresponding time compared with input signal
T, wherein delay time t should be at least more than the times in a reference-input signal period, specifically can be by designing corresponding series
Metal-oxide-semiconductor design parameter realizes the design of delay time in chain of inverters and phase inverter.The phase delay time is selected, is obtained
Output signal and input signal in addition to having phase delay, be identical signal.
As shown in figure 4, the error detection unit 4 by XOR gate 311, filter capacitor C312, the first driving circuit 313,
NMOS tube 314, current source 315,316 and second driving circuit 317 of capacitance form, the two of phase frequency detector in main road phaselocked loop 1
The input of a output signals UP, DN as XOR gate 311, the output of XOR gate 311 connect one end of filter capacitor C312, and conduct
The input of first driving circuit 313, the other end ground connection of filter capacitor C312；The output of first driving circuit 313 connects NMOS tube
314 grid a1, the drain electrode a2 of NMOS tube 314 are connected with the output terminal of current source 315, the source electrode ground connection of NMOS tube 314, capacitance
316 one end is connected with the drain electrode a2 of NMOS tube 314, and the other end ground connection of capacitance 316, NMOS tube 314 is used for controlling current source
Whether 315 charge to capacitance 316；315 input terminal of current source is connected with power vd D；The drain electrode of NMOS tube 314 is driven with second
The input terminal of dynamic circuit 317 is connected, and the output terminal of the second driving circuit 317 exports the indication signal Error.When main road locks phase
During 1 steady operation of ring, UP and DOWN have identical pulsewidth, and output is low level after XOR gate 311, i.e. a0 nodes are low
Level, the output of corresponding first driving circuit 313 is also low level, and NMOS tube 314 is off state, and current source 315 is right
Capacitance 316 charges, and node a2 is high level, therefore the output of the second driving circuit 317 is high level, i.e. indication signal
Error exports high level, and the clock signal for representing main road phaselocked loop 1 normally exports.When main road 1 operation irregularity of phaselocked loop, UP
It can change with the pulsewidth of DN, the pulsewidth of the two can change, XOR gate with the variation of phase-lock-ring output frequency and phase
311 can export high impulse, and pulse width is determined by frequency and phase and the variation size of normal value；It is defeated when XOR gate 311
Going out the high impulse time lengthens number when increasing, and the charging of capacitance 312 is reached a certain level, the voltage of node a0 is more than certain threshold
Value, the output of the first driving circuit 313 become high level, open NMOS tube 314, so that node a2 after NMOS tube 314 is opened
It is connected to the ground, while the output state of the second driving circuit 317 changes, indication signal Error output low levels represent master
The output clock signal of road phaselocked loop 1 is abnormal.As phaselocked loop 1 restores lock-out state again, the pulsewidth of UP and DN become
In identical, capacitance 312 gradually discharges, and node a0 restores low level again, and the output node a1 of driving circuit 313 becomes low electricity
Flat, NMOS tube 314 turns off, and current source 315 charges again to capacitance 316, the raising of a2 node voltages, the output of driving circuit 317
For high level, error indication signal restores high level, and the recovering clock signals for representing main road phaselocked loop 1 normally export.The error
Detection unit can provide corresponding indication signal according to the working condition of phaselocked loop, when operation irregularity occurs for phaselocked loop, the list
Member can quickly make detection and provide error indication signal；When phaselocked loop is resumed work again, which, which can pass through, repeats
It is normal that detection provides the enough stabilization time recoveries of phaselocked loop.
As shown in figure 5, clock selecting unit 6 is touched including first with door 418, second and door 419, phase inverter 420, the first D
Send out device 411, the second d type flip flop 412, third d type flip flop 413, four d flip-flop 414, third and door the 415, the 4th and door 416
And or door 417；Wherein indication signal Error respectively with first and an input terminal of door 418 and the input terminal of phase inverter 420
It is connected, while the QN terminations first of four d flip-flop 414 and another input terminal of door 418, first makees with the output of door 418
D ends for the first d type flip flop 411 input；Main road pll clock signal delay output CK1 respectively with the first d type flip flop
411CK ends, third d type flip flop 413CK ends, third are connected with an input terminal of door 415；The Q ends output of first d type flip flop 411
It is connected with the D ends input of third d type flip flop 413, the Q ends output of third d type flip flop 413 connects another input terminal with door 415；Instead
As second and the input of door 419, second is defeated with door 419 for the QN ends output of the output of phase device 420 and third d type flip flop 413
Go out the D ends input as the second d type flip flop 412, the delay output CK2 of spoke road pll clock signal is triggered respectively with the 2nd D
The CK ends of device 412 are connected, the CK ends of four d flip-flop 414 and the 4th are connected with an input terminal of door 416；Second d type flip flop
412 Q ends output is connected with the input of the D ends of four d flip-flop 414, the Q ends of four d flip-flop 414 export and with door 416
Another input terminal is connected；The output of third and door 415 and the 4th with door 416 export as or door 417 input；Or door 417
Output be clock selecting unit 6 clock output signal.
Wherein error indication signal Error obtains signal~Error that Error negates, Error letters by phase inverter 420
Number with by the Error phases after timing control and the input for being used as the first d type flip flop 411, using 411 He of two-stage d type flip flop
413 timing control, the output of third d type flip flop 413 export CK1 as third with the delay of main road pll clock signal
With the input of door 415, the clock signal effectively exported when Error signals are high level is obtained；~Error signals are with passing through sequential
After control~Error phases and input as the second d type flip flop 412, using the sequential control of two-stage d type flip flop 412 and 414
It is defeated with door 416 as the 4th that the delay of system, the output of four d flip-flop 414 and spoke road pll clock signal exports CK2
Enter, obtain the clock signal effectively exported when Error signals are low level.Two-way clock signal as or door 417 input, obtain
To final clock output signal, i.e. the clock signal of final output exports CK1 signals when Error values are high, and Error values are
CK2 signals are exported when low.
Using the above-mentioned clock selecting unit with timing control, the hair occurred in clock handoff procedure can be eliminated
Thorn avoids system from causing data transmission fault because of clock signal switching.
The unspecified content of the present invention is common knowledge of the present invention.
Claims (6)
1. a kind of adaptive switched radiation hardening clock forming circuit of bimodulus based on phaselocked loop, it is characterised in that：It is locked including main road
Phase ring (1) and bypass phaselocked loop (2), main road delay unit (3) and bypass delay unit (5), error detection unit (4) and clock
Selecting unit (6)；Main road phaselocked loop (1) and bypass phaselocked loop (2) are the charge pump phase lock loop without radiation hardening, respectively
Clock signal output is provided；The clock signal that main road delay unit (3) exports main road phaselocked loop (1) obtains main road into line delay
The delay output CK1 of pll clock signal；Bypass delay unit (5) carries out the clock signal that bypass phaselocked loop (2) exports
Delay obtains the delay output CK2 of bypass pll clock signal；The error detection unit (4) is to main road phaselocked loop (1)
Two output signals UPs of middle phase frequency detector, DN are detected and export indication signal Error, when two of phase frequency detector
When output signal is identical, the indication signal Error of error detection unit (4) output is the first level signal, works as phase frequency detector
Two output signal differences when, error detection unit (4) output indication signal Error be second electrical level signal；Clock selects
It selects unit (6) the delay output of two-way phaselocked loop is carried out being selected as final output, main road pll clock signal prolongs
When output CK1 and spoke road pll clock signal delay output CK2 as clock selecting unit (6) two clocks input,
The indication signal Error of error detection unit (4) output is inputted as the control of clock selecting unit (6), when error-detecting list
When the indication signal of first (4) is the first level signal, the delay output CK1 of clock selecting unit (6) selection main road phaselocked loop (1)
For final output, when the indication signal of error detection unit (4) is second electrical level signal, clock selecting unit (6) selection
The delay output CK2 of bypass phaselocked loop (2) is final output.
2. the adaptive switched radiation hardening clock forming circuit of the bimodulus according to claim 1 based on phaselocked loop, feature
It is：First level signal is high level, and second electrical level signal is low level.
3. the adaptive switched radiation hardening clock forming circuit of the bimodulus according to claim 1 based on phaselocked loop, feature
It is：The main road phaselocked loop (1) and bypass phaselocked loop (2) are identical unit, respectively by phase frequency detector (211), electricity
Lotus pump (212), wave filter (213), voltage controlled oscillator (214) and frequency divider (215) are formed；External reference signal FREF and frequency dividing
Two input signals of the output signal of device as phase frequency detector (211), two output signals UPs of phase frequency detector (211)
With the input signal that DN is charge pump (212), the output of charge pump (212) connects the input of wave filter (213), wave filter (213)
Output connect the inputs of voltage controlled oscillator (214), the clock signal that the output of voltage controlled oscillator (214) is exported as phaselocked loop
PLL-CK, while as the input of frequency divider (215), the input of the output of frequency divider (215) as phase frequency detector (211),
So as to form a circuit；When stabilized works, two output signals UPs of phase frequency detector (211), DN be with
Two pulse-period signals of same pulse width, and its rising edge and failing edge are perfectly aligned；When phase-locked loop operation exception, mirror
Two output signals UPs, the DN pulsewidths of frequency phase discriminator (211) change, the frequency and phase of variable quantity and pll output signal
The variation of position is directly proportional, can directly react phase-locked loop operation abnormal conditions.
4. the adaptive switched radiation hardening clock forming circuit of the bimodulus according to claim 1 based on phaselocked loop, feature
It is：The main road delay unit (3) and bypass delay unit (5) are identical unit, using chain of inverters structure；It is defeated
Entering signal and pass through the propagation in chain of inverters so that output signal has the delay time t of corresponding time compared with input signal, wherein
Delay time t should be at least more than the time in an external reference signal period.
5. the adaptive switched radiation hardening clock forming circuit of the bimodulus according to claim 1 based on phaselocked loop, feature
It is：The error detection unit (4) is by XOR gate (311), filter capacitor C (312), the first driving circuit (313), NMOS tube
(314), current source (315), capacitance (316) and the second driving circuit (317) form, phase frequency detector in main road phaselocked loop (1)
Two output signals UPs, inputs of the DN as XOR gate (311), the output of XOR gate (311) connects filter capacitor C's (312)
One end, and as the input of the first driving circuit (313), the other end of filter capacitor C (312) is grounded；First driving circuit
(313) output connects the grid a1 of NMOS tube (314), the output terminal phase of the drain electrode a2 and current source (315) of NMOS tube (314)
Even, the source electrode ground connection of NMOS tube (314), one end of capacitance (316) are connected with the drain electrode a2 of NMOS tube (314), capacitance (316)
The other end is grounded, and NMOS tube (314) is for controlling whether current source (315) charges to capacitance (316)；Current source (315)
Input terminal is connected with power vd D；The drain electrode of NMOS tube (314) is connected with the input terminal of the second driving circuit (317), the second driving
The output terminal of circuit (317) exports the indication signal Error.
6. the adaptive switched radiation hardening clock forming circuit of the bimodulus according to claim 1 based on phaselocked loop, feature
It is：Clock selecting unit (6) includes first and door (418), second and door (419), phase inverter (420), the first d type flip flop
(411), the second d type flip flop (412), third d type flip flop (413), four d flip-flop (414), third and door (415), the 4th with
Door (416) and or door (417)；
Wherein indication signal Error respectively with first and an input terminal of door (418) and the input terminal phase of phase inverter (420)
Even, while the QN of four d flip-flop (414) terminations first and another input terminal of door (418), first is defeated with door (418)
Go out the D ends input as the first d type flip flop (411)；The delay output CK1 of main road pll clock signal is touched respectively with the first D
Hair device (411) CK ends, third d type flip flop (413) CK ends, third are connected with an input terminal of door (415)；First d type flip flop
(411) Q ends output is connected with the D ends input of third d type flip flop (413), and the Q ends output of third d type flip flop (413) connects and door
(415) another input terminal；The output of phase inverter (420) and the QN ends output of third d type flip flop (413) are used as second and door
(419) input, second inputs with the D ends of the output of door (419) as the second d type flip flop (412), spoke road phase-locked loop clock letter
Number delay output CK2 be connected respectively with the CK ends of the second d type flip flop (412), the CK ends of four d flip-flop (414) and the
Four are connected with an input terminal of door (416)；The Q ends output of second d type flip flop (412) is defeated with the D ends of four d flip-flop (414)
Enter connected, the output of the Q ends of d type flip flop (414) is connected with another input terminal of door (416)；The output of third and door (415) and
4th with the output of door (416) as or door (417) input；Or the output of door (417) be clock selecting unit (6) when
Clock output signal.
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| CN105610430B true CN105610430B (en) | 2018-07-06 |
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| CN106936426A (en) * | 2016-12-29 | 2017-07-07 | 北京时代民芯科技有限公司 | A kind of triplication redundancy radiation hardening clock forming circuit based on phaselocked loop |
| CN108365845B (en) * | 2017-01-26 | 2020-11-24 | 综合器件技术公司 | Fast-response reference-free frequency detector |
| CN108418581B (en) * | 2017-02-10 | 2021-09-14 | 中芯国际集成电路制造(上海)有限公司 | Circuit for generating clock signal |
| CN107222205A (en) * | 2017-05-09 | 2017-09-29 | 长沙中部芯空微电子研究所有限公司 | A kind of NOR gate circuit and Antiradiation chip |
| CN107241093B (en) * | 2017-05-23 | 2020-12-01 | 中国人民解放军国防科学技术大学 | Anti-irradiation dual-mode phase-locked loop circuit |
| CN108418578B (en) * | 2018-03-02 | 2020-06-30 | 湖南大学 | Frequency divider circuit resisting single particle reinforcement |
| CN110212894A (en) * | 2019-07-12 | 2019-09-06 | 深圳市泛海数据科技有限公司 | A kind of clock frequency switching circuit |
| CN111464182A (en) * | 2020-04-29 | 2020-07-28 | 四川玖越机器人科技有限公司 | Inspection robot |
| CN117134746A (en) * | 2022-05-19 | 2023-11-28 | 上海韦尔半导体股份有限公司 | Clock generating circuit |
| CN118017998B (en) * | 2024-04-08 | 2024-06-11 | 深圳中微电科技有限公司 | Frequency division clock switching circuit without burr and zero time delay |
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