CN117134746A - Clock generating circuit - Google Patents

Clock generating circuit Download PDF

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Publication number
CN117134746A
CN117134746A CN202210553159.0A CN202210553159A CN117134746A CN 117134746 A CN117134746 A CN 117134746A CN 202210553159 A CN202210553159 A CN 202210553159A CN 117134746 A CN117134746 A CN 117134746A
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CN
China
Prior art keywords
level
sense terminal
signal
clock signal
capacitor
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Pending
Application number
CN202210553159.0A
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Chinese (zh)
Inventor
木村宏之
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Will Semiconductor Ltd
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Will Semiconductor Ltd
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Filing date
Publication date
Application filed by Will Semiconductor Ltd filed Critical Will Semiconductor Ltd
Priority to CN202210553159.0A priority Critical patent/CN117134746A/en
Priority to US17/833,995 priority patent/US11669125B1/en
Publication of CN117134746A publication Critical patent/CN117134746A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/00006—Changing the frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

The clock generating circuit of the present invention outputs a clock signal of a fixed period by repeating operations of immediately rising the clock signal when the enable signal is at the H level, gradually rising the voltage of the sense terminal via the 1 st capacitor to the L level and then via the resistor, gradually rising the voltage of the sense terminal when the sense terminal reaches a specific potential, gradually lowering the voltage of the sense terminal by flowing a current via the resistor after the clock signal is at the H level, gradually rising the voltage of the sense terminal via the 1 st capacitor to the L level when the sense terminal reaches a specific potential, gradually rising the voltage of the sense terminal via the resistor, gradually rising the voltage of the sense terminal via the L level when the sense terminal reaches a specific potential, and gradually lowering the voltage of the sense terminal via the L level when the sense terminal reaches a specific potential.

Description

Clock generating circuit
Technical Field
The present invention relates to a clock generation circuit using a capacitor and a resistor.
Background
Previously, a clock generation circuit is known that generates a clock signal of a fixed frequency by charging and discharging a capacitor.
The clock generation circuit has a problem in that a relatively long time is required until a clock signal of a stable period is generated.
Accordingly, a circuit that can generate a stable clock earlier is desired.
Disclosure of Invention
The clock generation circuit of the present invention includes:
an AND gate, an enable signal is input to one end and a clock signal is output;
the 1 st converter is connected with the output end of the AND gate at one end and inverts and outputs a clock signal;
a 1 st capacitor, the inversion clock signal from the 1 st converter being supplied to one end, and the other end being connected to one end of the 2 nd capacitor;
a resistor, the clock signal from the AND gate is supplied to one end, and the other end is connected to a sensing end which is a connection point of the 1 st capacitor and the 2 nd capacitor; a kind of electronic device with high-pressure air-conditioning system
A 2 nd converter, one end of which is connected with the induction end, and the other end of which is connected with the other end of the AND gate; and is also provided with
The clock signal of a fixed period is outputted by repeating the operations of immediately rising the clock signal when the enable signal is at the H level, making the sense terminal be at the L level via the 1 st capacitor, then gradually rising the voltage of the sense terminal via the resistor, making the sense terminal be at the H level by making the output of the 2 nd converter be at the L level, making the clock signal be at the L level, and making the sense terminal be at the H level by inverting the clock signal,
then, the voltage at the sense terminal is gradually decreased by flowing a current through the resistor, and when the sense terminal reaches a specific potential, the output of the 2 nd converter is at H level, the clock signal is at H level, the sense terminal is at L level through the 1 st capacitor, and thereafter, the voltage at the sense terminal is gradually increased through the resistor, and when the sense terminal reaches a specific potential, the output of the 2 nd converter is at L level, and the clock signal is at L level.
According to the clock generating circuit of the present invention, a stable clock signal can be generated early.
Drawings
Fig. 1 is a block diagram showing the configuration of a clock generation circuit according to an embodiment.
Fig. 2 is a timing chart illustrating the operation of the clock generation circuit according to the embodiment.
Fig. 3 is a block diagram showing the configuration of the clock generation circuit of modification 1.
Fig. 4 is a timing chart illustrating the operation of modification 1.
Fig. 5 is a block diagram showing the configuration of the clock generation circuit of modification 2.
Fig. 6 is a timing chart illustrating the operation of modification 2.
Detailed Description
Hereinafter, embodiments of the present invention will be described with reference to the drawings. The following embodiments are not limited to the present invention, and a configuration in which a plurality of examples are selectively combined is also included in the present invention.
Circuit structure
Fig. 1 is a block diagram showing the configuration of a clock generation circuit according to an embodiment. The enable signal EN is input to one end of the AND gate AND 1. The signal input to the other end will be described below.
The clock signal CLKout is obtained in the output of the AND gate AND1, AND the AND gate AND1 outputs the clock signal CLKout. An output terminal of the AND gate AND1 is connected to the inverter INV1, AND the clock signal CLKout is inverted by the inverter INV1 to become an inverted clock signal CIN. An output end of the inverter INV1 is connected to one end of the capacitor C2, and the other end of the capacitor C2 is connected to the ground GND. The junction of the capacitor C1 and the capacitor C2 is the SENSE terminal S, where the voltage is the signal SENSE. The inverter INV1 is referred to as a 1 st inverter, the inverter INV2 is referred to as a 2 nd inverter, the capacitor C1 is referred to as a 1 st capacitor, and the capacitor C2 is referred to as a 2 nd capacitor.
The output terminal of the AND gate AND1 is connected to the sense terminal S, which is the connection point between the capacitor C1 AND the capacitor C2, via the resistor R1.
Accordingly, the inverted clock signal CIN is supplied to the sense terminal S through the capacitor C1, and the clock signal CLKout is supplied through the resistor R1.
The other end of the AND gate AND1 is connected to the sense terminal S via the inverter INV 2. Thus, the inverted signal of the signal SENSE is supplied to the other input terminal of the AND gate AND 1.
Fig. 2 is a timing chart illustrating the operation of the clock generation circuit of the embodiment of fig. 1. In the following description, H level=vmax=vdd, L level=vmin=gnd=0v, but the present invention is not limited thereto.
First, in a state where the enable signal EN is at the L level, the clock signal CLKout is at the L level. Therefore, the sense terminal S connected to the output terminal of CLKout via the resistor R1 is also at the L level. The inversion clock signal CIN is at H level, and one end of the capacitor C1 is at H level, and the other end is at L level, and is in a charged state. Here, the H level of each signal is Vdd, the L level is ground gnd=0v, and the capacitor C1 charges only Vdd.
Further, an inverted signal of the signal SENSE is input to the other end of the AND gate AND1, AND thus the H level is input.
In this state, when the enable signal EN is at the H level, the output of the AND gate AND1, that is, the clock signal CLKout is at the H level. Thus, the inverted clock signal CIN is at the L level, and the voltage at one end of the capacitor C1 drops by Vdd only.
Here, in a state where the enable signal EN is at the L level, the clock signal CLKout is at the L level, and the sense terminal S is also at the L level. In addition, the sensing terminal S is connected to the ground GND through the capacitor C2, and the voltage of the sensing terminal S drops Vdd/2, v0= -Vdd/2 by only dropping Vdd at one end of the capacitor C1 so that both the capacitors C1 and C2 are in a state of being charged with Vdd/2. When the capacitances of the capacitors C1 and C2 are c1=c2, the voltage of the sense terminal S becomes Vdd/2, and when the capacitance is not c1=c2, the voltage of the sense terminal S becomes vdd·c1/(c1+c2).
At this time, the input at the other end of the AND gate AND1 is maintained at the H level without change. On the other hand, the H level of the clock signal CLKout causes a current to flow through the resistor R1 to the sense terminal S, and the voltage of the sense terminal S gradually rises.
When the voltage at the sense terminal S exceeds Vdd/2, the output of the inverter INV2 is inverted, the other end of the AND gate AND1 is input at the L level, AND the clock signal CLKout is at the L level. Thus, the inversion clock signal CIN is at H level, and only Vdd is raised, and the voltage of the sense terminal S rises by Vdd/2 to Vdd.
The period t1 of the first H level of the clock signal CLKout is a period of-Vdd/2 to +vdd/2.
In this state, CLKout is at L level, the sense terminal S is at Vdd, a current flows to the CLKout output terminal via the resistor R1, and the voltage of the sense terminal S gradually decreases. Then, when the voltage of the sensing terminal S is lower than Vdd/2, the output of the inverter INV2 is inverted, the other end of the AND gate AND1 is input to the H level, AND the clock signal CLKout is at the H level. The signal SENSE at SENSE terminal S is GND. The period t2 of the first L level of the clock signal CLKout is a period of Vdd/2 to +vdd/2.
The H level of the clock signal CLKout causes a current to flow through the resistor R1 to the sense terminal S, and the voltage of the sense terminal S gradually rises. Then, when the voltage of the sense terminal S exceeds Vdd/2, the output of the inverter INV2 is inverted, the other end of the AND gate AND1 is input at the L level, AND the clock signal CLKout is at the L level. The period t1 of the two H levels of the clock signal CLKout is a period t3 of Vdd to +vdd/2, and t2=t3.
Thereafter, the same operation as the period of t2 and t3 is repeated, whereby the clock signal CLKout having a duty ratio of 50% is output. Further, the enable signal EN is L level and the clock signal CLKout is L level, and the sensing terminal S is discharged to 0V.
Thus, the clock signal CLKout repeats the H level and the L level by the current flowing from the sense terminal S to the CLKout output terminal via the resistor R1. The same amount of current flows through the resistor R1 when the directions are opposite, and the duty ratio of the clock signal CLKout is 50% when the first H level is removed. The period of the clock signal CLKout is set by the capacitance of the capacitor C2 and the resistance value of the resistor R1.
In the present embodiment, when the enable signal EN is at the H level, the output of the clock signal CLKout is immediately started.
Here, a time t1 of the first H level of the clock signal CLKout will be described.
Further, c=c1=c2, vmax=vdd, vmin=0, v0= -Vdd/2, and t=2r1×c is the time constant when the sense terminal S is charged and discharged through the resistor R1.
First, the first current to reach Vdd/2 is a current flowing to the sense terminal S via R1, rising from-Vdd/2 to Vdd/2 (v1=3vdd/2).
Thus, the first and second substrates are bonded together,
Vdd/2＝V1＊[1－exp(－t1/T)]－V0
t1＝－T＊ln[1－Vdd/((3/2)＊Vdd)]
t1＝－T＊ln(1/3)
＝2R1＊C＊ln3
next, a time t2 of the L level of the clock signal CLKout will be described. At this time, the voltage of the sense terminal S is reduced from Vdd to Vdd/2
Thus, the first and second substrates are bonded together,
Vdd/2＝Vdd＊exp(－t2/T)
1/2＝exp(－t2/T)
t2＝T＊ln2
t2＝2R1C＊ln2。
construction of variation 1
Fig. 3 is a block diagram showing the configuration of the clock generation circuit of modification 1. In this example, the other end (lower end) of the capacitor C2 is not connected to GND, and the enable signal EN is supplied thereto via the inverters INV3 and INV 4. Further, by providing 2 inverters INV3 and INV4, it is possible to supply sufficient electric power to the other end of the capacitor C2.
Fig. 4 is a timing chart illustrating the operation of variation 1 of fig. 3. Thus, by supplying the enable signal EN to the other end of the capacitor C2, the voltage of the sense terminal S is not-Vdd/2 but is close to 0V when the enable signal EN is at the H level. Although the initial voltage is shown to be somewhat lower than 0V, the initial voltage is made substantially 0V by providing the inverters INV3 and INV4 with sufficient capacity, whereby the clock signal CLKout having a duty ratio of 50% can be obtained from the beginning.
Construction of variation 2
Fig. 5 is a block diagram showing the configuration of the clock generation circuit of modification 2.
In the clock generating circuits according to the above embodiments and the modification 1, when the enable signal EN changes from the H level to the L level, signals having different duty ratios are output. In variation 2, the output of the signal is prevented.
The clock generation unit 10 is a clock generation circuit shown in fig. 1. In addition, although the circuit of fig. 3 may be used, in modification 2, even if the circuit described in fig. 1 is used, the first H level time is the same as the other H level time, and therefore, the circuit of fig. 3 is not required to be used.
The clock generator 10 receives a signal ENI as an enable signal EN. Further, the clock generation section 10 outputs the clock signal CLKout as a signal CKI.
The signal CKI is input to a frequency dividing circuit composed of 2 flip-flops FF1, FF 2. That is, the signal CKI is inversely input to the clock terminal of the flip-flop FF1 and directly input to the clock terminal of the FF 2. The Q output (signal Q1) of flip-flop FF1 is input to the D input of flip-flop FF 2. The inverted Q output of flip-flop FF2, qn, is supplied to the D input of flip-flop FF 1. The signal Fout as a clock signal is output from the Q output terminal of the flip-flop FF 2.
The signal q1, the signal Fout, and the clock generation enable signal clkgen_en are input to the OR gate OR1, and the signal ENI is output from the OR gate OR 1.
In this circuit, a clock generation enable signal clkgen_en is supplied as a signal indicating the start and end of clock generation.
Fig. 6 is a timing diagram illustrating the operation of the circuit of fig. 5.
First, when the clock generation enable signal clkgen_en is at the L level, the signal CKI that is the output signal of the clock generation circuit is at the L level. Further, with the flip-flops FF1, FF2, both are set to the L level at the time when the signal ENI falls, and both are set to the L level at the time when the clock generation enable signal clkgen_en rises from the L level to the H level.
When the clock generation enable signal clkgen_en rises from the L level to the H level, the signal ENI as the output of the OR gate OR1 is the H level, and the signal CKI as the output of the clock generation section 10 starts to alternately output the H level and the L level.
The Q output (Q1) of the flip-flop FF1 is taken in by the flip-flop FF2 by the rising of the signal CK1, but the signal Q1 is still at the L level. By the falling of the signal CKI, the flip-flop FF1 takes in the H level of the inverted Q output Qn of the flip-flop FF2, and the signal Q1 becomes the H level.
The signal CKI falls to thereby input Q1 to the flip-flop FF2, and the signal Fout output as Q becomes H level.
The Q output (Q1) of the flip-flop FF1 is taken in by the flip-flop FF2 by the rising of the signal CK1, but the signal Q1 is at the H level. The flip-flop FF1 takes in the L level of the inverted Q output Qn of the flip-flop FF2 by the next fall of the signal CKI, and the signal Q1 becomes the L level.
Thus, after the second rising of the signal EKI, the signal Fout of 2 times the period of the signal CKI is outputted from the Q output of the flip-flop FF 2.
Although the clock generation enable signal clkgen_en falls from the H level to the L level, signals q1, fout are input to the OR gate OR 1. Therefore, the signal ENI falls at the point when both the signals q1 and Fout are at the L level, and the output of the signal CKI is stopped (not at the H level) at this point. Even if a signal having a short period is output to the signal CKI, a signal having a different period is not output to the signal Fout.
The flip-flops FF1 and FF2 may be reset to the L level by the falling or rising of the signal ENI.
As described above, in variation 2, the signal Fout is always outputted at the start and end of the fixed period regardless of the timing of the start and end of the H level period of the clock generation enable signal clkgen_en.

Claims (3)

1. A clock generation circuit, comprising:
an AND gate, an enable signal is input to one end and a clock signal is output;
the 1 st converter is connected with the output end of the AND gate at one end and inverts and outputs a clock signal;
a 1 st capacitor, the inversion clock signal from the 1 st converter being supplied to one end, and the other end being connected to one end of the 2 nd capacitor;
a resistor, the clock signal from the AND gate is supplied to one end, and the other end is connected to a sensing end which is a connection point of the 1 st capacitor and the 2 nd capacitor; a kind of electronic device with high-pressure air-conditioning system
A 2 nd converter, one end of which is connected with the induction end, and the other end of which is connected with the other end of the AND gate; and is also provided with
The clock signal of a fixed period is outputted by repeating the operations of immediately rising the clock signal when the enable signal is at the H level, making the sense terminal be at the L level via the 1 st capacitor, then gradually rising the voltage of the sense terminal via the resistor, making the sense terminal be at the H level by making the output of the 2 nd converter be at the L level, making the clock signal be at the L level, and making the sense terminal be at the H level by inverting the clock signal,
then, the voltage at the sense terminal is gradually decreased by flowing a current through the resistor, and when the sense terminal reaches a specific potential, the output of the 2 nd converter is at H level, the clock signal is at H level, the sense terminal is at L level through the 1 st capacitor, and thereafter, the voltage at the sense terminal is gradually increased through the resistor, and when the sense terminal reaches a specific potential, the output of the 2 nd converter is at L level, and the clock signal is at L level.
2. The clock generation circuit of claim 1, wherein
By supplying an enable signal to the other end of the 2 nd capacitor, a voltage drop at the sense terminal at the time of the rise of the enable signal is suppressed.
3. The clock generation circuit according to claim 1, having a frequency dividing circuit that divides the clock signal, and
the output of the frequency dividing circuit is ended by turning off the enable signal, thereby removing the unnecessary signal after the enable signal is turned off.
CN202210553159.0A 2022-05-19 2022-05-19 Clock generating circuit Pending CN117134746A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202210553159.0A CN117134746A (en) 2022-05-19 2022-05-19 Clock generating circuit
US17/833,995 US11669125B1 (en) 2022-05-19 2022-06-07 Clock generation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210553159.0A CN117134746A (en) 2022-05-19 2022-05-19 Clock generating circuit

Publications (1)

Publication Number Publication Date
CN117134746A true CN117134746A (en) 2023-11-28

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Application Number Title Priority Date Filing Date
CN202210553159.0A Pending CN117134746A (en) 2022-05-19 2022-05-19 Clock generating circuit

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CN (1) CN117134746A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07131304A (en) * 1993-10-29 1995-05-19 Sanyo Electric Co Ltd Clock generating circuit
CN105610430A (en) * 2015-12-23 2016-05-25 北京时代民芯科技有限公司 Dual-mode self switching radiation hardening clock generation circuit based on phase-locked loops
WO2018230338A1 (en) * 2017-06-13 2018-12-20 ソニーセミコンダクタソリューションズ株式会社 Clock enabler circuit
CN113328732A (en) * 2021-06-15 2021-08-31 西安微电子技术研究所 Dead time generation method and circuit with controllable delay time

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8837639B2 (en) * 2010-06-18 2014-09-16 Ati Technologies Ulc Parallel synchronizing cell with improved mean time between failures

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07131304A (en) * 1993-10-29 1995-05-19 Sanyo Electric Co Ltd Clock generating circuit
CN105610430A (en) * 2015-12-23 2016-05-25 北京时代民芯科技有限公司 Dual-mode self switching radiation hardening clock generation circuit based on phase-locked loops
WO2018230338A1 (en) * 2017-06-13 2018-12-20 ソニーセミコンダクタソリューションズ株式会社 Clock enabler circuit
CN113328732A (en) * 2021-06-15 2021-08-31 西安微电子技术研究所 Dead time generation method and circuit with controllable delay time

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